feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for t

feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb

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fix(intel): update checking for memcpy and memset

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA C

fix(intel): update checking for memcpy and memset

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA Crypto Service does
not exceed the maximum of expected data size and does not meet the
minimum of expected data size.

Signed-off-by: Phui Kei Wong <phui.kei.wong@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb18f05c18d9142fbe703c3f4075341d179d8bad

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feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loo

feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0618dfcdc86a7c1e0c8047b7214d369866dd2281

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fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19

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feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signe

feat(intel): implement timer init divider via CPU frequency for N5X

Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed

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Merge "feat(intel): fix bridge disable and reset" into integration

Merge "fix(intel): update boot scratch to indicate to Uboot is PSCI ON" into integration

fix(intel): flash dcache before mmio read

Flash dcache before mmio read to avoid reading old/previous value.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ifd5a63a3c0f20b3e673be62

fix(intel): flash dcache before mmio read

Flash dcache before mmio read to avoid reading old/previous value.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ifd5a63a3c0f20b3e673be62ff5c3b6c4cf69df51

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fix(intel): fix the pointer of block memory to fill in and bytes being set

Fix on the pointer of the block memory to fill in and the number of
bytes to be set. So it can clear the exact address with

fix(intel): fix the pointer of block memory to fill in and bytes being set

Fix on the pointer of the block memory to fill in and the number of
bytes to be set. So it can clear the exact address with exact number
of bytes.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb8bda446ecd4c1d85d1ec9802bdcb020904c6c1

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feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tie

feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db

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fix(intel): update boot scratch to indicate to Uboot is PSCI ON

There is a use case where kernel requested ATF to power off/on only CPU0.
However, after ATF power off/on CPU0, CPU0 did not back into

fix(intel): update boot scratch to indicate to Uboot is PSCI ON

There is a use case where kernel requested ATF to power off/on only CPU0.
However, after ATF power off/on CPU0, CPU0 did not back into the state
to wait for ATF. Instead, CPU0 continue to reentry SPL boot sequence
because CPU0 is master/primary core. This causing the system reboot from
SPL again, while the slave core still in kernel.

To resolve this, ATF is set the boot scratch register 8 bit 17 whenever
it is a request from kernel to power off/on only CPU0. So, if this boot
scratch bit is set, CPU 0 will be able to put into a state to wait for
ATF.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia0228c5396beaa479858f5bd02fc05139efd2423

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refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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Merge "fix(intel): add mailbox error return status for FCS_DECRYPTION" into integration

fix(intel): add mailbox error return status for FCS_DECRYPTION

Add 2 more mailbox error return status for FCS_DECRYPTION when sending
mailbox command to SDM

Signed-off-by: Sieu Mun Tang <sieu.mun.t

fix(intel): add mailbox error return status for FCS_DECRYPTION

Add 2 more mailbox error return status for FCS_DECRYPTION when sending
mailbox command to SDM

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifff4faa397232cc0080f9fca6f6948ac305915c4

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fix(intel): missing NCORE CCU snoop filter fix in BL2

Clear Ncore CCU snoop filter. There is hardware bug in NCORE CCU IP
and it is causing an issue in the coherent directory tracking of
outstanding

fix(intel): missing NCORE CCU snoop filter fix in BL2

Clear Ncore CCU snoop filter. There is hardware bug in NCORE CCU IP
and it is causing an issue in the coherent directory tracking of
outstanding cache lines.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9ee67c94e6379d318516ae8f660a62323ce8d563

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Merge "feat(intel): extending to support SMMU in FCS" into integration

Merge "fix(intel): fix fcs_client crashed when increased param size" into integration

Merge changes Ia8f1471a,I6b95c19d into integration

* changes:
fix(intel): agilex bitstream pre-authenticate
fix(intel): mailbox store QSPI ref clk in scratch reg

fix(intel): fix fcs_client crashed when increased param size

No overflow buffer checking for param size. There is a security threat.
Update code to check for param size according to cryto param mode

fix(intel): fix fcs_client crashed when increased param size

No overflow buffer checking for param size. There is a security threat.
Update code to check for param size according to cryto param mode.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I37a2d047edd9ff835b3f0986d85309c402887bef

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feat(intel): extending to support SMMU in FCS

This patch is to extend support SMMU in FCS GET_DIGEST, MAC_VERIFY,
ECDSA_SHA2_DATA_SIGNING and ECDSA_SHA2_DATA_SIGNATURE_VERIFY.
It also will change to

feat(intel): extending to support SMMU in FCS

This patch is to extend support SMMU in FCS GET_DIGEST, MAC_VERIFY,
ECDSA_SHA2_DATA_SIGNING and ECDSA_SHA2_DATA_SIGNATURE_VERIFY.
It also will change to use asynchronous mailbox send command to improve
fcs_client timing performance.
Increase the SIP_SVC_VERSION_MAJOR because SMMU support is not backward
compatible.
Increase the SIP_SVC_VERSION_MINOR because 8 news function IDs are
introduced.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I15e619e246531b065451f9b201646f3c50e26307

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Merge "fix(intel): fix print out ERROR when encounter SEU_Err" into integration

Merge changes I8667f362,Ia0bd832c into integration

* changes:
feat(intel): setup FPGA interface for Agilex
fix(intel): fix pinmux handoff bug on Agilex

Merge "fix(intel): fix sp_timer0 is not disabled in firewall on Agilex" into integration

fix(intel): agilex bitstream pre-authenticate

HSD #15012010816: To add in bitstream pre-authentication checking.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8f1471a674ba169729

fix(intel): agilex bitstream pre-authenticate

HSD #15012010816: To add in bitstream pre-authentication checking.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8f1471a674ba16972927084f5fdc27c4ba93103

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