fix(intel): remove invalid SDM SMMU Stream ID register from bypass list

The register is SDM-owned and not accessible by HPS.
It was added by mistakein v2.7.0.
Removing it ensures correct access cont

fix(intel): remove invalid SDM SMMU Stream ID register from bypass list

The register is SDM-owned and not accessible by HPS.
It was added by mistakein v2.7.0.
Removing it ensures correct access control.

Change-Id: I76d27e5b53bfb115ace6011dbb79f2fac049bb4e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): prevent invalid register rejection on non-A5F4 devices

Move TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 handling outside the
main switch to ensure non-A5F4 devices (e.g., A5F0) evaluate
other val

fix(intel): prevent invalid register rejection on non-A5F4 devices

Move TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 handling outside the
main switch to ensure non-A5F4 devices (e.g., A5F0) evaluate
other valid registers.

Previously, TSN cases were inside the switch and followed
by a `break` if not A5F4, causing early exit and -1 return.
Valid registers (e.g., ECC_INTMASK_x)were rejected, blocking boot.

Now, A5F4 TSN registers are handled conditionally
and fallthrough is clean for all other devices.

Change-Id: I1339e0e3951ccb68f02dc437f25db6c27d2a0877
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id:

fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id: I74bd296c4c050fb61d4df5c1bd5b57449b3a13e3
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): match declaration with definition

Patch 2fcb37db8 changed the alignment to 8, but the `extern` definition
remained at 32 so bring in line. Also use the same macro for the size of
the arr

fix(intel): match declaration with definition

Patch 2fcb37db8 changed the alignment to 8, but the `extern` definition
remained at 32 so bring in line. Also use the same macro for the size of
the array.

Change-Id: I95149f5e3428a58c464e616c385250b10eda2834
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359

fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): undo setting USB 3.1 reset pulse bit in BL2" into integration

Merge "fix(intel): update the AES GCM/GCM_GHASH modes return data size" into integration

Merge "fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks" into integration

fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks

Update SCR1 register (0xFA000004) programming to:
- Set NSNUMSMRGO[14:8] = 0x20 to allocate 32 Stream Mapping Register
groups

fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks

Update SCR1 register (0xFA000004) programming to:
- Set NSNUMSMRGO[14:8] = 0x20 to allocate 32 Stream Mapping Register
groups for non-secure context.
- Set NSNUMCBO[5:0] = 0x10 to allocate 16 Context Banks for non-secure
context.

This change aligns with the requirement for SDM SMMU AFRL in Linux to
use 32 Context Banks. Secure and non-secure resources are now balanced,
with indices 0–31 reserved for non-secure and the rest for secure.

Change-Id: I6466a36278040d95b877f66a3800f13339d13bc8
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is

fix(intel): update the AES GCM/GCM_GHASH modes return data size

On the Agilex5 platform, in FCS AES method if block mode is
GCM/GCM_GHASH mode then the data size written to the destination
buffer is at index[7] instead of [3] as in other cases.

Change-Id: Ide664f594ea63aaee7f74d21e8e2986de48e94a2
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attach

fix(intel): undo setting USB 3.1 reset pulse bit in BL2

During testing of USB 3.1 in FreeRTOS, it is reported, setting
the reset pulse override bit is affecting the enumeration of
USB devices attached to the USB 3.1 controller. Hence,
reverting the bit change to its default state.

Change-Id: I5746a7ff6b579c39416a462ebef6696f4aa57051
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): correct condition to process unused entries" into integration

Merge "fix(intel): add missing cache flush operation for hmac" into integration

fix(intel): correct condition to process unused entries

A logic error in the response queue handling caused available
entries to be skipped after an upstream change inverted the
flag check. This fix

fix(intel): correct condition to process unused entries

A logic error in the response queue handling caused available
entries to be skipped after an upstream change inverted the
flag check. This fix restores the intended logic so that unused
response slots are correctly detected and processed.

Change-Id: I253f098573c3c84dc43f48cff893c410684322a2
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): iossm v2 enhancement refactor

This patch is to used to update iossm v2 enhancement.
The major change is to replace io_mb_req to
mmio_read.
Next is to refactor the code.

Change-Id: Id084

fix(intel): iossm v2 enhancement refactor

This patch is to used to update iossm v2 enhancement.
The major change is to replace io_mb_req to
mmio_read.
Next is to refactor the code.

Change-Id: Id0842392f362e30252f1ac9f32797d8d3a419997
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): add missing cache flush operation for hmac

Add missing cache flush operation for HMAC verify
operation.Also update the code to query the correct
buffer for the final result of HMAC veri

fix(intel): add missing cache flush operation for hmac

Add missing cache flush operation for HMAC verify
operation.Also update the code to query the correct
buffer for the final result of HMAC verify operation.

Change-Id: I85208765313b9048cfef13727d280dca8af6d548
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): select the DFI interface based on the hand-off data" into integration

Merge "fix(intel): set BIT2 of system manager MPFE Interface Select" into integration

Merge "fix(intel): flush the mailbox response buffer in SiPSVC V3" into integration

Merge "fix(intel): fix iossm driver timeout in agilex5" into integration

Merge "fix(intel): unexpected DDR reset type value observed on Agilex5" into integration

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data.

Change-Id: I097b7f84874368a5ed265d8fa7fff193f430b245
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual i

fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual issue.

agilex5_iossm_mailbox.c: corrected divisor
for read_count in inline_ecc_bist_mem_init. Wrong
divisor will cause read_count to be 0. The same
value is also used in out_of_band_ecc_bist_mem_init.

Change-Id: I4c85d251b7e88f3176902917450572adb574b33a
Signed-off-by: Goh Shun Jing <shun.jing.goh@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Sig

fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguish

fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguishes all possible DDR_RESET_TYPE values, including 0x4
and any future additions.

Change-Id: I8f1abdc8269b0de68733e5fcb3f12b4a5640770e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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