1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U 18 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 19 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 20 21 #define FCS_RANDOM_EXT_OFFSET 3 22 23 #define FCS_MODE_DECRYPT 0x0 24 #define FCS_MODE_ENCRYPT 0x1 25 #define FCS_ENCRYPTION_DATA_0 0x10100 26 #define FCS_DECRYPTION_DATA_0 0x10102 27 #define FCS_OWNER_ID_OFFSET 0xC 28 #define FCS_CRYPTION_CRYPTO_HEADER 0x07000000 29 #define FCS_CRYPTION_RESP_WORD_SIZE 4U 30 #define FCS_CRYPTION_RESP_SIZE_OFFSET 3U 31 32 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 33 #define PSGSIGMA_SESSION_ID_ONE 0x1 34 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 35 36 #define RESERVED_AS_ZERO 0x0 37 /* FCS Single cert */ 38 39 #define FCS_BIG_CNTR_SEL 0x1 40 41 #define FCS_SVN_CNTR_0_SEL 0x2 42 #define FCS_SVN_CNTR_1_SEL 0x3 43 #define FCS_SVN_CNTR_2_SEL 0x4 44 #define FCS_SVN_CNTR_3_SEL 0x5 45 46 #define FCS_BIG_CNTR_VAL_MAX 495U 47 #define FCS_SVN_CNTR_VAL_MAX 64U 48 49 /* FCS Attestation Cert Request Parameter */ 50 51 #define FCS_ATTEST_FIRMWARE_CERT 0x01 52 #define FCS_ATTEST_DEV_ID_SELF_SIGN_CERT 0x02 53 #define FCS_ATTEST_DEV_ID_ENROLL_CERT 0x04 54 #define FCS_ATTEST_ENROLL_SELF_SIGN_CERT 0x08 55 #define FCS_ATTEST_ALIAS_CERT 0x10 56 #define FCS_ATTEST_CERT_MAX_REQ_PARAM 0xFF 57 58 /* FCS Crypto Service */ 59 60 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 61 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 62 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 63 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 64 65 #define FCS_CS_FIELD_SIZE_MASK 0xFFFF 66 #define FCS_CS_FIELD_FLAG_OFFSET 24 67 #define FCS_CS_FIELD_FLAG_INIT BIT(0) 68 #define FCS_CS_FIELD_FLAG_UPDATE BIT(1) 69 #define FCS_CS_FIELD_FLAG_FINALIZE BIT(2) 70 71 #define FCS_AES_MAX_DATA_SIZE 0x10000000 /* 256 MB */ 72 #define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */ 73 #define FCS_AES_CMD_MAX_WORD_SIZE 15U 74 75 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U 76 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U 77 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U 78 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U 79 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U 80 81 #define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE 5U 82 #define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE 7U 83 #define FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE 43U 84 #define FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE 17U 85 #define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U 86 #define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U 87 88 #define FCS_CRYPTO_ECB_BUFFER_SIZE 12U 89 #define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U 90 #define FCS_CRYPTO_BLOCK_MODE_MASK 0x07 91 #define FCS_CRYPTO_ECB_MODE 0x00 92 #define FCS_CRYPTO_CBC_MODE 0x01 93 #define FCS_CRYPTO_CTR_MODE 0x02 94 95 /* FCS Payload Structure */ 96 typedef struct fcs_rng_payload_t { 97 uint32_t session_id; 98 uint32_t context_id; 99 uint32_t crypto_header; 100 uint32_t size; 101 } fcs_rng_payload; 102 103 typedef struct fcs_encrypt_payload_t { 104 uint32_t first_word; 105 uint32_t src_addr; 106 uint32_t src_size; 107 uint32_t dst_addr; 108 uint32_t dst_size; 109 } fcs_encrypt_payload; 110 111 typedef struct fcs_decrypt_payload_t { 112 uint32_t first_word; 113 uint32_t owner_id[2]; 114 uint32_t src_addr; 115 uint32_t src_size; 116 uint32_t dst_addr; 117 uint32_t dst_size; 118 } fcs_decrypt_payload; 119 120 typedef struct fcs_encrypt_ext_payload_t { 121 uint32_t session_id; 122 uint32_t context_id; 123 uint32_t crypto_header; 124 uint32_t src_addr; 125 uint32_t src_size; 126 uint32_t dst_addr; 127 uint32_t dst_size; 128 } fcs_encrypt_ext_payload; 129 130 typedef struct fcs_decrypt_ext_payload_t { 131 uint32_t session_id; 132 uint32_t context_id; 133 uint32_t crypto_header; 134 uint32_t owner_id[2]; 135 uint32_t src_addr; 136 uint32_t src_size; 137 uint32_t dst_addr; 138 uint32_t dst_size; 139 } fcs_decrypt_ext_payload; 140 141 typedef struct psgsigma_teardown_msg_t { 142 uint32_t reserved_word; 143 uint32_t magic_word; 144 uint32_t session_id; 145 } psgsigma_teardown_msg; 146 147 typedef struct fcs_cntr_set_preauth_payload_t { 148 uint32_t first_word; 149 uint32_t counter_value; 150 } fcs_cntr_set_preauth_payload; 151 152 typedef struct fcs_cs_key_payload_t { 153 uint32_t session_id; 154 uint32_t reserved0; 155 uint32_t reserved1; 156 uint32_t key_id; 157 } fcs_cs_key_payload; 158 159 typedef struct fcs_crypto_service_data_t { 160 uint32_t session_id; 161 uint32_t context_id; 162 uint32_t key_id; 163 uint32_t crypto_param_size; 164 uint64_t crypto_param; 165 uint8_t is_updated; 166 } fcs_crypto_service_data; 167 168 typedef struct fcs_crypto_service_aes_data_t { 169 uint32_t session_id; 170 uint32_t context_id; 171 uint32_t param_size; 172 uint32_t key_id; 173 uint32_t crypto_param[7]; 174 uint8_t is_updated; 175 } fcs_crypto_service_aes_data; 176 177 /* Functions Definitions */ 178 179 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 180 uint32_t *mbox_error); 181 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id, 182 uint32_t size, uint32_t *send_id); 183 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 184 uint32_t *send_id); 185 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 186 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, 187 int32_t counter_value, 188 uint32_t test_bit, 189 uint32_t *mbox_error); 190 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 191 uint32_t dst_addr, uint32_t dst_size, 192 uint32_t *send_id); 193 194 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 195 uint32_t dst_addr, uint32_t dst_size, 196 uint32_t *send_id); 197 198 int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id, 199 uint32_t src_addr, uint32_t src_size, 200 uint32_t dst_addr, uint32_t *dst_size, 201 uint32_t *mbox_error); 202 int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id, 203 uint32_t src_addr, uint32_t src_size, 204 uint32_t dst_addr, uint32_t *dst_size, 205 uint32_t *mbox_error); 206 207 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 208 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 209 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 210 uint64_t dst_addr, uint32_t *dst_size, 211 uint32_t *mbox_error); 212 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 213 uint64_t dst_addr, uint32_t *dst_size, 214 uint32_t *mbox_error); 215 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 216 uint32_t *mbox_error); 217 218 int intel_fcs_create_cert_on_reload(uint32_t cert_request, 219 uint32_t *mbox_error); 220 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, 221 uint32_t *dst_size, uint32_t *mbox_error); 222 223 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 224 uint32_t *mbox_error); 225 int intel_fcs_close_crypto_service_session(uint32_t session_id, 226 uint32_t *mbox_error); 227 228 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 229 uint32_t *mbox_error); 230 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 231 uint64_t dst_addr, uint32_t *dst_size, 232 uint32_t *mbox_error); 233 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 234 uint32_t *mbox_error); 235 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 236 uint64_t dst_addr, uint32_t *dst_size, 237 uint32_t *mbox_error); 238 239 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id, 240 uint32_t key_id, uint32_t param_size, 241 uint64_t param_data, uint32_t *mbox_error); 242 int intel_fcs_get_digest_update_finalize(uint32_t session_id, uint32_t context_id, 243 uint32_t src_addr, uint32_t src_size, 244 uint64_t dst_addr, uint32_t *dst_size, 245 uint8_t is_finalised, uint32_t *mbox_error); 246 247 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id, 248 uint32_t key_id, uint32_t param_size, 249 uint64_t param_data, uint32_t *mbox_error); 250 int intel_fcs_mac_verify_update_finalize(uint32_t session_id, uint32_t context_id, 251 uint32_t src_addr, uint32_t src_size, 252 uint64_t dst_addr, uint32_t *dst_size, 253 uint32_t data_size, uint8_t is_finalised, 254 uint32_t *mbox_error); 255 256 int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id, 257 uint32_t key_id, uint32_t param_size, 258 uint64_t param_data, uint32_t *mbox_error); 259 int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id, 260 uint32_t src_addr, uint32_t src_size, 261 uint64_t dst_addr, uint32_t *dst_size, 262 uint32_t *mbox_error); 263 264 int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id, 265 uint32_t key_id, uint32_t param_size, 266 uint64_t param_data, uint32_t *mbox_error); 267 int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id, 268 uint32_t src_addr, uint32_t src_size, 269 uint64_t dst_addr, uint32_t *dst_size, 270 uint32_t *mbox_error); 271 272 int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id, 273 uint32_t context_id, uint32_t key_id, 274 uint32_t param_size, uint64_t param_data, 275 uint32_t *mbox_error); 276 int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id, 277 uint32_t context_id, uint32_t src_addr, 278 uint32_t src_size, uint64_t dst_addr, 279 uint32_t *dst_size, uint8_t is_finalised, 280 uint32_t *mbox_error); 281 282 int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id, 283 uint32_t context_id, uint32_t key_id, 284 uint32_t param_size, uint64_t param_data, 285 uint32_t *mbox_error); 286 int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id, 287 uint32_t context_id, uint32_t src_addr, 288 uint32_t src_size, uint64_t dst_addr, 289 uint32_t *dst_size, uint32_t data_size, 290 uint8_t is_finalised, uint32_t *mbox_error); 291 292 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id, 293 uint32_t key_id, uint32_t param_size, 294 uint64_t param_data, uint32_t *mbox_error); 295 int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id, 296 uint64_t dst_addr, uint32_t *dst_size, 297 uint32_t *mbox_error); 298 299 int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id, 300 uint32_t key_id, uint32_t param_size, 301 uint64_t param_data, uint32_t *mbox_error); 302 int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id, 303 uint32_t src_addr, uint32_t src_size, 304 uint64_t dst_addr, uint32_t *dst_size, 305 uint32_t *mbox_error); 306 307 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id, 308 uint32_t key_id, uint64_t param_addr, 309 uint32_t param_size, uint32_t *mbox_error); 310 int intel_fcs_aes_crypt_update_finalize(uint32_t session_id, 311 uint32_t context_id, uint64_t src_addr, 312 uint32_t src_size, uint64_t dst_addr, 313 uint32_t dst_size, uint8_t is_finalised, 314 uint32_t *send_id); 315 316 #endif /* SOCFPGA_FCS_H */ 317