Merge pull request #1653 from JackyBai/master

Add NXP i.MX8MQ basic support

Merge pull request #1702 from MISL-EBU-System-SW/patches-18.12

Update code with latest changes from Marvell LSP 18.12

ble: ap807: Switch to PLL mode and update CPU frequency

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0

ble: ap807: Switch to PLL mode and update CPU frequency

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: add tzc380 support

Add tzc380 support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>

Merge pull request #1679 from pangupta/master

ccn: Introduce API to set and read value of node register

ccn: Introduce API to set and read value of node register

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

drivers/tzc-dmc620: add driver to setup DMC-620 TZC controller

ARM CoreLink DMC-620 Dynamic Memory Controller includes a TZC controller
to setup secure or non-secure regions of DRAM memory. The TZC

drivers/tzc-dmc620: add driver to setup DMC-620 TZC controller

ARM CoreLink DMC-620 Dynamic Memory Controller includes a TZC controller
to setup secure or non-secure regions of DRAM memory. The TZC controller
allows to setup upto eight such regions of memory in DRAM. This driver
provides helper functions to setup the TZC controller within DMC-620.

Change-Id: Iee7692417c2080052bdb7b1c2873a024bc5d1d10
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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Merge pull request #1682 from MISL-EBU-System-SW/migrate-multi-console

Marvell: Migrate to multi console API

plat/marvell: Migrate to multi-console API

Migrate Marvell platforms from legacy console API to
multi-console API.

Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c
Signed-off-by: Konstantin Por

plat/marvell: Migrate to multi-console API

Migrate Marvell platforms from legacy console API to
multi-console API.

Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: st: update console driver to support MULTI_CONSOLE_API

Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add a new file for UART registers definition

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge pull request #1676 from Yann-lms/static_analysis

Correct some issues found with static analysis tools

cadence: uart: comply to console_register prototype

Signed-off-by: Alexei Colin <acolin@isi.edu>

stm32mp1: remove duplicate function declaration

It is already in include/drivers/st/stm32mp1_ddr_helpers.h.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: correct some static analysis tools issues

These issues wer found by sparse:

drivers/st/clk/stm32mp1_clk.c:1524:19:
warning: incorrect type in assignment (different base types)
expect

stm32mp1: correct some static analysis tools issues

These issues wer found by sparse:

drivers/st/clk/stm32mp1_clk.c:1524:19:
warning: incorrect type in assignment (different base types)
expected restricted fdt32_t const [usertype] *pkcs_cell
got unsigned int const [usertype] *

plat/st/stm32mp1/plat_image_load.c:13:6:
warning: symbol 'plat_flush_next_bl_params' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:21:16:
warning: symbol 'plat_get_bl_image_load_info' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:29:13:
warning: symbol 'plat_get_next_bl_params' was not declared.
Should it be static?

plat/st/stm32mp1/bl2_io_storage.c:40:10:
warning: symbol 'block_buffer' was not declared. Should it be static?

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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plat/arm: Fix types of constants in headers

Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2

Allwinner/pmic v2

meson: console: Introduce console driver

It has only been tested with a system clock of 24 MHz.

It has only been implemented for the multi console API.

Signed-off-by: Antonio Nino Diaz <antonio.ni

meson: console: Introduce console driver

It has only been tested with a system clock of 24 MHz.

It has only been implemented for the multi console API.

Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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tzc: Fix MISRA defects

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int b

tzc: Fix MISRA defects

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.

Also, fix some address definitions in arm_def.h.

Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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allwinner: Add RSB driver

The "Reduced Serial Bus" is an Allwinner specific bus, bearing many
similarities with I2C. It sports a much higher bus frequency, though,
(typically 3 MHz) and requires muc

allwinner: Add RSB driver

The "Reduced Serial Bus" is an Allwinner specific bus, bearing many
similarities with I2C. It sports a much higher bus frequency, though,
(typically 3 MHz) and requires much less handholding for the typical
task of manipulating slave registers (fire-and-forget).
On most A64 boards this bus is used to connect the PMIC to the SoC.

This driver provides basic primitives to read and write slave registers,
it will be later used by the PMIC code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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stm32mp1: add an IO to read MMC devices

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the bo

stm32mp1: add an IO to read MMC devices

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the boot time would be very bad.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add an IO to read STM32IMAGE binaries

This IO is required to read binaries with STM32 header.
This header is added with the stm32image tool.

Signed-off-by: Yann Gautier <yann.gautier@st.c

stm32mp1: add an IO to read STM32IMAGE binaries

This IO is required to read binaries with STM32 header.
This header is added with the stm32image tool.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Add new defines for STM32MP1 platform

To boot on eMMC or SD-cards, STM32MP1 platform needs:
- GPT_IMAGE_ID to read GPT table on those devices
- STM32_IMAGE_ID and IO_TYPE_STM32IMAGE to read images w

Add new defines for STM32MP1 platform

To boot on eMMC or SD-cards, STM32MP1 platform needs:
- GPT_IMAGE_ID to read GPT table on those devices
- STM32_IMAGE_ID and IO_TYPE_STM32IMAGE to read images with STM32 header
- IO_TYPE_MMC to have a IO for MMC devices

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add sdmmc2 driver

This driver is for the STMicroelectronics sdmmc2 IP
which is in STM32MP1 SoC.
It uses the MMC framework, and can address either eMMC or SD-card.

Signed-off-by: Yann Gaut

stm32mp1: add sdmmc2 driver

This driver is for the STMicroelectronics sdmmc2 IP
which is in STM32MP1 SoC.
It uses the MMC framework, and can address either eMMC or SD-card.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

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