xref: /rk3399_ARM-atf/plat/hisilicon/poplar/bl31_plat_setup.c (revision 6f7dba4b24ee8e6c134a5237b5af461c9898501e)
1 /*
2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <bl31.h>
11 #include <bl_common.h>
12 #include <cortex_a53.h>
13 #include <debug.h>
14 #include <errno.h>
15 #include <generic_delay_timer.h>
16 #include <mmio.h>
17 #include <pl011.h>
18 #include <platform.h>
19 #include <platform_def.h>
20 #include <stddef.h>
21 #include <string.h>
22 #include "hi3798cv200.h"
23 #include "plat_private.h"
24 
25 /* Memory ranges for code and RO data sections */
26 #define BL31_RO_BASE	(unsigned long)(&__RO_START__)
27 #define BL31_RO_LIMIT	(unsigned long)(&__RO_END__)
28 
29 /* Memory ranges for coherent memory section */
30 #define BL31_COHERENT_RAM_BASE	(unsigned long)(&__COHERENT_RAM_START__)
31 #define BL31_COHERENT_RAM_LIMIT	(unsigned long)(&__COHERENT_RAM_END__)
32 
33 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
34 
35 static entry_point_info_t bl32_image_ep_info;
36 static entry_point_info_t bl33_image_ep_info;
37 static console_pl011_t console;
38 
39 static void hisi_tzpc_sec_init(void)
40 {
41 	mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE);
42 }
43 
44 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
45 {
46 	entry_point_info_t *next_image_info;
47 
48 	assert(sec_state_is_valid(type));
49 	next_image_info = (type == NON_SECURE)
50 			? &bl33_image_ep_info : &bl32_image_ep_info;
51 	/*
52 	 * None of the images on the ARM development platforms can have 0x0
53 	 * as the entrypoint
54 	 */
55 	if (next_image_info->pc)
56 		return next_image_info;
57 	else
58 		return NULL;
59 }
60 
61 /*******************************************************************************
62  * Perform any BL31 early platform setup common to ARM standard platforms.
63  * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
64  * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
65  * done before the MMU is initialized so that the memory layout can be used
66  * while creating page tables. BL2 has flushed this information to memory, so
67  * we are guaranteed to pick up good data.
68  ******************************************************************************/
69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
70 				u_register_t arg2, u_register_t arg3)
71 {
72 	void *from_bl2;
73 
74 	from_bl2 = (void *) arg0;
75 
76 	console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
77 			       PL011_BAUDRATE, &console);
78 
79 	/* Init console for crash report */
80 	plat_crash_console_init();
81 
82 	/*
83 	 * Check params passed from BL2 should not be NULL,
84 	 */
85 	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
86 
87 	assert(params_from_bl2 != NULL);
88 	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
89 	assert(params_from_bl2->h.version >= VERSION_2);
90 
91 	bl_params_node_t *bl_params = params_from_bl2->head;
92 
93 	/*
94 	 * Copy BL33 and BL32 (if present), entry point information.
95 	 * They are stored in Secure RAM, in BL2's address space.
96 	 */
97 	while (bl_params) {
98 		if (bl_params->image_id == BL32_IMAGE_ID)
99 			bl32_image_ep_info = *bl_params->ep_info;
100 
101 		if (bl_params->image_id == BL33_IMAGE_ID)
102 			bl33_image_ep_info = *bl_params->ep_info;
103 
104 		bl_params = bl_params->next_params_info;
105 	}
106 
107 	if (bl33_image_ep_info.pc == 0)
108 		panic();
109 }
110 
111 void bl31_platform_setup(void)
112 {
113 	/* Init arch timer */
114 	generic_delay_timer_init();
115 
116 	/* Init GIC distributor and CPU interface */
117 	poplar_gic_driver_init();
118 	poplar_gic_init();
119 
120 	/* Init security properties of IP blocks */
121 	hisi_tzpc_sec_init();
122 }
123 
124 void bl31_plat_runtime_setup(void)
125 {
126 	/* do nothing */
127 }
128 
129 void bl31_plat_arch_setup(void)
130 {
131 	plat_configure_mmu_el3(BL31_BASE,
132 			       (BL31_LIMIT - BL31_BASE),
133 			       BL31_RO_BASE,
134 			       BL31_RO_LIMIT,
135 			       BL31_COHERENT_RAM_BASE,
136 			       BL31_COHERENT_RAM_LIMIT);
137 
138 	INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
139 	     bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
140 }
141