1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <debug.h> 11 #include <desc_image_load.h> 12 #include <dw_mmc.h> 13 #include <errno.h> 14 #include <generic_delay_timer.h> 15 #include <mmc.h> 16 #include <mmio.h> 17 #include <optee_utils.h> 18 #include <partition/partition.h> 19 #include <pl011.h> 20 #include <platform.h> 21 #include <string.h> 22 #include "hi3798cv200.h" 23 #include "plat_private.h" 24 25 /* Memory ranges for code and read only data sections */ 26 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 27 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 28 29 /* Memory ranges for coherent memory section */ 30 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 31 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 32 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 static console_pl011_t console; 35 36 /******************************************************************************* 37 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 38 * Return 0 on success, -1 otherwise. 39 ******************************************************************************/ 40 int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 41 { 42 /* 43 * This platform has no SCP_BL2 yet 44 */ 45 return 0; 46 } 47 48 /******************************************************************************* 49 * Gets SPSR for BL32 entry 50 ******************************************************************************/ 51 uint32_t poplar_get_spsr_for_bl32_entry(void) 52 { 53 /* 54 * The Secure Payload Dispatcher service is responsible for 55 * setting the SPSR prior to entry into the BL3-2 image. 56 */ 57 return 0; 58 } 59 60 /******************************************************************************* 61 * Gets SPSR for BL33 entry 62 ******************************************************************************/ 63 #ifndef AARCH32 64 uint32_t poplar_get_spsr_for_bl33_entry(void) 65 { 66 unsigned long el_status; 67 unsigned int mode; 68 uint32_t spsr; 69 70 /* Figure out what mode we enter the non-secure world in */ 71 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 72 el_status &= ID_AA64PFR0_ELX_MASK; 73 74 mode = (el_status) ? MODE_EL2 : MODE_EL1; 75 76 /* 77 * TODO: Consider the possibility of specifying the SPSR in 78 * the FIP ToC and allowing the platform to have a say as 79 * well. 80 */ 81 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 82 return spsr; 83 } 84 #else 85 uint32_t poplar_get_spsr_for_bl33_entry(void) 86 { 87 unsigned int hyp_status, mode, spsr; 88 89 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 90 91 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 92 93 /* 94 * TODO: Consider the possibility of specifying the SPSR in 95 * the FIP ToC and allowing the platform to have a say as 96 * well. 97 */ 98 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 99 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 100 return spsr; 101 } 102 #endif /* AARCH32 */ 103 104 int poplar_bl2_handle_post_image_load(unsigned int image_id) 105 { 106 int err = 0; 107 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 108 #ifdef SPD_opteed 109 bl_mem_params_node_t *pager_mem_params = NULL; 110 bl_mem_params_node_t *paged_mem_params = NULL; 111 #endif 112 113 assert(bl_mem_params); 114 115 switch (image_id) { 116 #ifdef AARCH64 117 case BL32_IMAGE_ID: 118 #ifdef SPD_opteed 119 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 120 assert(pager_mem_params); 121 122 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 123 assert(paged_mem_params); 124 125 err = parse_optee_header(&bl_mem_params->ep_info, 126 &pager_mem_params->image_info, 127 &paged_mem_params->image_info); 128 if (err != 0) { 129 WARN("OPTEE header parse error.\n"); 130 } 131 132 /* 133 * OP-TEE expect to receive DTB address in x2. 134 * This will be copied into x2 by dispatcher. 135 * Set this (arg3) if necessary 136 */ 137 /* bl_mem_params->ep_info.args.arg3 = PLAT_HIKEY_DT_BASE; */ 138 #endif 139 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); 140 break; 141 #endif 142 143 case BL33_IMAGE_ID: 144 /* BL33 expects to receive the primary CPU MPID (through r0) */ 145 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 146 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); 147 break; 148 149 #ifdef SCP_BL2_BASE 150 case SCP_BL2_IMAGE_ID: 151 /* The subsequent handling of SCP_BL2 is platform specific */ 152 err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info); 153 if (err) { 154 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 155 } 156 break; 157 #endif 158 default: 159 /* Do nothing in default case */ 160 break; 161 } 162 163 return err; 164 } 165 166 /******************************************************************************* 167 * This function can be used by the platforms to update/use image 168 * information for given `image_id`. 169 ******************************************************************************/ 170 int bl2_plat_handle_post_image_load(unsigned int image_id) 171 { 172 return poplar_bl2_handle_post_image_load(image_id); 173 } 174 175 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, 176 u_register_t arg2, u_register_t arg3) 177 { 178 struct meminfo *mem_layout = (struct meminfo *)arg1; 179 #if !POPLAR_RECOVERY 180 struct mmc_device_info info; 181 182 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 183 #endif 184 185 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, 186 PL011_BAUDRATE, &console); 187 188 /* Enable arch timer */ 189 generic_delay_timer_init(); 190 191 bl2_tzram_layout = *mem_layout; 192 193 #if !POPLAR_RECOVERY 194 /* SoC-specific emmc register are initialized/configured by bootrom */ 195 INFO("BL2: initializing emmc\n"); 196 info.mmc_dev_type = MMC_IS_EMMC; 197 dw_mmc_init(¶ms, &info); 198 #endif 199 200 plat_io_setup(); 201 } 202 203 void bl2_plat_arch_setup(void) 204 { 205 plat_configure_mmu_el1(bl2_tzram_layout.total_base, 206 bl2_tzram_layout.total_size, 207 BL2_RO_BASE, 208 BL2_RO_LIMIT, 209 BL2_COHERENT_RAM_BASE, 210 BL2_COHERENT_RAM_LIMIT); 211 } 212 213 void bl2_platform_setup(void) 214 { 215 } 216 217 uintptr_t plat_get_ns_image_entrypoint(void) 218 { 219 #ifdef PRELOADED_BL33_BASE 220 return PRELOADED_BL33_BASE; 221 #else 222 return PLAT_POPLAR_NS_IMAGE_OFFSET; 223 #endif 224 } 225