1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <dw_ufs.h> 13 #include <errno.h> 14 #include <generic_delay_timer.h> 15 #include <gicv2.h> 16 #include <hi3660.h> 17 #include <interrupt_props.h> 18 #include <mmio.h> 19 #include <pl011.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 41 /* Data structure which holds the extents of the trusted RAM for BL1 */ 42 static meminfo_t bl1_tzram_layout; 43 static console_pl011_t console; 44 45 /****************************************************************************** 46 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 47 * interrupts. 48 *****************************************************************************/ 49 static const interrupt_prop_t g0_interrupt_props[] = { 50 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 51 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 52 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 53 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 54 }; 55 56 const gicv2_driver_data_t hikey960_gic_data = { 57 .gicd_base = GICD_REG_BASE, 58 .gicc_base = GICC_REG_BASE, 59 .interrupt_props = g0_interrupt_props, 60 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 61 }; 62 63 meminfo_t *bl1_plat_sec_mem_layout(void) 64 { 65 return &bl1_tzram_layout; 66 } 67 68 /* 69 * Perform any BL1 specific platform actions. 70 */ 71 void bl1_early_platform_setup(void) 72 { 73 unsigned int id, uart_base; 74 75 generic_delay_timer_init(); 76 hikey960_read_boardid(&id); 77 if (id == 5300) 78 uart_base = PL011_UART5_BASE; 79 else 80 uart_base = PL011_UART6_BASE; 81 /* Initialize the console to provide early debug support */ 82 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 83 PL011_BAUDRATE, &console); 84 85 /* Allow BL1 to see the whole Trusted RAM */ 86 bl1_tzram_layout.total_base = BL1_RW_BASE; 87 bl1_tzram_layout.total_size = BL1_RW_SIZE; 88 89 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 90 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 91 } 92 93 /* 94 * Perform the very early platform specific architecture setup here. At the 95 * moment this only does basic initialization. Later architectural setup 96 * (bl1_arch_setup()) does not do anything platform specific. 97 */ 98 void bl1_plat_arch_setup(void) 99 { 100 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 101 bl1_tzram_layout.total_size, 102 BL1_RO_BASE, 103 BL1_RO_LIMIT, 104 BL_COHERENT_RAM_BASE, 105 BL_COHERENT_RAM_END); 106 } 107 108 static void hikey960_ufs_reset(void) 109 { 110 unsigned int data, mask; 111 112 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 113 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 114 do { 115 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 116 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 117 /* use abb clk */ 118 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 119 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 120 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 121 mdelay(1); 122 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 123 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 124 125 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 126 do { 127 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 128 } while ((data & PERI_UFS_BIT) == 0); 129 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 130 mdelay(1); 131 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 132 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 133 MASK_UFS_DEVICE_RESET); 134 /* clear SC_DIV_UFS_PERIBUS */ 135 mask = SC_DIV_UFS_PERIBUS << 16; 136 mmio_write_32(CRG_CLKDIV17_REG, mask); 137 /* set SC_DIV_UFSPHY_CFG(3) */ 138 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 139 data = SC_DIV_UFSPHY_CFG(3); 140 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 141 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 142 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 143 data |= 0x39; 144 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 145 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 146 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 147 MASK_UFS_CLK_GATE_BYPASS); 148 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 149 150 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 151 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 152 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 153 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 154 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 155 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 156 mdelay(1); 157 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 158 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 159 mdelay(20); 160 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 161 0x03300330); 162 163 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 164 do { 165 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 166 } while (data & PERI_UFS_BIT); 167 } 168 169 static void hikey960_ufs_init(void) 170 { 171 dw_ufs_params_t ufs_params; 172 173 memset(&ufs_params, 0, sizeof(ufs_params)); 174 ufs_params.reg_base = UFS_REG_BASE; 175 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 176 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 177 178 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 179 hikey960_ufs_reset(); 180 dw_ufs_init(&ufs_params); 181 } 182 183 /* 184 * Function which will perform any remaining platform-specific setup that can 185 * occur after the MMU and data cache have been enabled. 186 */ 187 void bl1_platform_setup(void) 188 { 189 hikey960_clk_init(); 190 hikey960_pmu_init(); 191 hikey960_regulator_enable(); 192 hikey960_tzc_init(); 193 hikey960_peri_init(); 194 hikey960_ufs_init(); 195 hikey960_pinmux_init(); 196 hikey960_gpio_init(); 197 hikey960_io_setup(); 198 } 199 200 /* 201 * The following function checks if Firmware update is needed, 202 * by checking if TOC in FIP image is valid or not. 203 */ 204 unsigned int bl1_plat_get_next_image_id(void) 205 { 206 unsigned int mode, ret; 207 208 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 209 switch (mode & BOOT_MODE_MASK) { 210 case BOOT_MODE_RECOVERY: 211 ret = NS_BL1U_IMAGE_ID; 212 break; 213 default: 214 WARN("Invalid boot mode is found:%d\n", mode); 215 panic(); 216 } 217 return ret; 218 } 219 220 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 221 { 222 unsigned int index = 0; 223 224 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 225 if (bl1_tbbr_image_descs[index].image_id == image_id) 226 return &bl1_tbbr_image_descs[index]; 227 index++; 228 } 229 230 return NULL; 231 } 232 233 void bl1_plat_set_ep_info(unsigned int image_id, 234 entry_point_info_t *ep_info) 235 { 236 unsigned int data = 0; 237 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 238 239 if (image_id != NS_BL1U_IMAGE_ID) 240 panic(); 241 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 242 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 243 NS_BL1U_SIZE); 244 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 245 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 246 /* Initialize the GIC driver, cpu and distributor interfaces */ 247 gicv2_driver_init(&hikey960_gic_data); 248 gicv2_distif_init(); 249 gicv2_pcpu_distif_init(); 250 gicv2_cpuif_enable(); 251 /* CNTFRQ is read-only in EL1 */ 252 write_cntfrq_el0(plat_get_syscnt_freq2()); 253 data = read_cpacr_el1(); 254 do { 255 data |= 3 << 20; 256 write_cpacr_el1(data); 257 data = read_cpacr_el1(); 258 } while ((data & (3 << 20)) != (3 << 20)); 259 INFO("cpacr_el1:0x%x\n", data); 260 261 ep_info->args.arg0 = 0xffff & read_mpidr(); 262 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 263 DISABLE_ALL_EXCEPTIONS); 264 } 265