1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <debug.h> 12 #include <errno.h> 13 #include <gicv2.h> 14 #include <hi6220.h> 15 #include <hikey_def.h> 16 #include <hisi_ipc.h> 17 #include <hisi_pwrc.h> 18 #include <interrupt_props.h> 19 #include <mmio.h> 20 #include <pl011.h> 21 #include <platform_def.h> 22 23 #include "hikey_private.h" 24 25 /* 26 * The next 2 constants identify the extents of the code & RO data region. 27 * These addresses are used by the MMU setup code and therefore they must be 28 * page-aligned. It is the responsibility of the linker script to ensure that 29 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 30 */ 31 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 32 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 33 34 /* 35 * The next 2 constants identify the extents of the coherent memory region. 36 * These addresses are used by the MMU setup code and therefore they must be 37 * page-aligned. It is the responsibility of the linker script to ensure that 38 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 39 * page-aligned addresses. 40 */ 41 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 42 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 43 44 static entry_point_info_t bl32_ep_info; 45 static entry_point_info_t bl33_ep_info; 46 static console_pl011_t console; 47 48 /****************************************************************************** 49 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 50 * interrupts. 51 *****************************************************************************/ 52 static const interrupt_prop_t g0_interrupt_props[] = { 53 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 54 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 55 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 56 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 57 }; 58 59 /* 60 * Ideally `arm_gic_data` structure definition should be a `const` but it is 61 * kept as modifiable for overwriting with different GICD and GICC base when 62 * running on FVP with VE memory map. 63 */ 64 gicv2_driver_data_t hikey_gic_data = { 65 .gicd_base = PLAT_ARM_GICD_BASE, 66 .gicc_base = PLAT_ARM_GICC_BASE, 67 .interrupt_props = g0_interrupt_props, 68 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 69 }; 70 71 static const int cci_map[] = { 72 CCI400_SL_IFACE3_CLUSTER_IX, 73 CCI400_SL_IFACE4_CLUSTER_IX 74 }; 75 76 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 77 { 78 entry_point_info_t *next_image_info; 79 80 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 81 82 /* None of the images on this platform can have 0x0 as the entrypoint */ 83 if (next_image_info->pc) 84 return next_image_info; 85 return NULL; 86 } 87 88 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 89 u_register_t arg2, u_register_t arg3) 90 { 91 void *from_bl2; 92 93 from_bl2 = (void *) arg0; 94 95 /* Initialize the console to provide early debug support */ 96 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 97 PL011_BAUDRATE, &console); 98 99 /* Initialize CCI driver */ 100 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 101 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 102 103 /* 104 * Check params passed from BL2 should not be NULL, 105 */ 106 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 107 assert(params_from_bl2 != NULL); 108 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 109 assert(params_from_bl2->h.version >= VERSION_2); 110 111 bl_params_node_t *bl_params = params_from_bl2->head; 112 113 /* 114 * Copy BL33 and BL32 (if present), entry point information. 115 * They are stored in Secure RAM, in BL2's address space. 116 */ 117 while (bl_params) { 118 if (bl_params->image_id == BL32_IMAGE_ID) 119 bl32_ep_info = *bl_params->ep_info; 120 121 if (bl_params->image_id == BL33_IMAGE_ID) 122 bl33_ep_info = *bl_params->ep_info; 123 124 bl_params = bl_params->next_params_info; 125 } 126 127 if (bl33_ep_info.pc == 0) 128 panic(); 129 } 130 131 void bl31_plat_arch_setup(void) 132 { 133 hikey_init_mmu_el3(BL31_BASE, 134 BL31_LIMIT - BL31_BASE, 135 BL31_RO_BASE, 136 BL31_RO_LIMIT, 137 BL31_COHERENT_RAM_BASE, 138 BL31_COHERENT_RAM_LIMIT); 139 } 140 141 /* Initialize EDMAC controller with non-secure mode. */ 142 static void hikey_edma_init(void) 143 { 144 int i; 145 uint32_t non_secure; 146 147 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 148 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 149 150 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) { 151 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 152 } 153 } 154 155 void bl31_platform_setup(void) 156 { 157 /* Initialize the GIC driver, cpu and distributor interfaces */ 158 gicv2_driver_init(&hikey_gic_data); 159 gicv2_distif_init(); 160 gicv2_pcpu_distif_init(); 161 gicv2_cpuif_enable(); 162 163 hikey_edma_init(); 164 165 hisi_ipc_init(); 166 hisi_pwrc_setup(); 167 } 168 169 void bl31_plat_runtime_setup(void) 170 { 171 } 172