1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <desc_image_load.h> 13 #include <dw_ufs.h> 14 #include <errno.h> 15 #include <generic_delay_timer.h> 16 #include <hi3660.h> 17 #include <mmio.h> 18 #ifdef SPD_opteed 19 #include <optee_utils.h> 20 #endif 21 #include <pl011.h> 22 #include <platform_def.h> 23 #include <string.h> 24 #include <ufs.h> 25 26 #include "hikey960_def.h" 27 #include "hikey960_private.h" 28 29 /* 30 * The next 2 constants identify the extents of the code & RO data region. 31 * These addresses are used by the MMU setup code and therefore they must be 32 * page-aligned. It is the responsibility of the linker script to ensure that 33 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 34 */ 35 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 36 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 37 38 #define BL2_RW_BASE (BL2_RO_LIMIT) 39 40 /* 41 * The next 2 constants identify the extents of the coherent memory region. 42 * These addresses are used by the MMU setup code and therefore they must be 43 * page-aligned. It is the responsibility of the linker script to ensure that 44 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 45 * page-aligned addresses. 46 */ 47 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 48 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 49 50 static meminfo_t bl2_el3_tzram_layout; 51 static console_pl011_t console; 52 extern int load_lpm3(void); 53 54 enum { 55 BOOT_MODE_RECOVERY = 0, 56 BOOT_MODE_NORMAL, 57 BOOT_MODE_MASK = 1, 58 }; 59 60 /******************************************************************************* 61 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 62 * Return 0 on success, -1 otherwise. 63 ******************************************************************************/ 64 int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 65 { 66 int i; 67 int *buf; 68 69 assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE); 70 71 INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); 72 73 INFO("BL2: SCP_BL2: 0x%lx@0x%x\n", 74 scp_bl2_image_info->image_base, 75 scp_bl2_image_info->image_size); 76 77 buf = (int *)scp_bl2_image_info->image_base; 78 79 INFO("BL2: SCP_BL2 HEAD:\n"); 80 for (i = 0; i < 64; i += 4) 81 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 82 buf[i], buf[i+1], buf[i+2], buf[i+3]); 83 84 buf = (int *)(scp_bl2_image_info->image_base + 85 scp_bl2_image_info->image_size - 256); 86 87 INFO("BL2: SCP_BL2 TAIL:\n"); 88 for (i = 0; i < 64; i += 4) 89 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 90 buf[i], buf[i+1], buf[i+2], buf[i+3]); 91 92 INFO("BL2: SCP_BL2 transferred to SCP\n"); 93 94 load_lpm3(); 95 (void)buf; 96 97 return 0; 98 } 99 100 static void hikey960_ufs_reset(void) 101 { 102 unsigned int data, mask; 103 104 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 105 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 106 do { 107 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 108 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 109 /* use abb clk */ 110 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 111 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 112 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 113 mdelay(1); 114 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 115 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 116 117 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 118 do { 119 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 120 } while ((data & PERI_UFS_BIT) == 0); 121 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 122 mdelay(1); 123 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 124 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 125 MASK_UFS_DEVICE_RESET); 126 /* clear SC_DIV_UFS_PERIBUS */ 127 mask = SC_DIV_UFS_PERIBUS << 16; 128 mmio_write_32(CRG_CLKDIV17_REG, mask); 129 /* set SC_DIV_UFSPHY_CFG(3) */ 130 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 131 data = SC_DIV_UFSPHY_CFG(3); 132 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 133 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 134 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 135 data |= 0x39; 136 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 137 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 138 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 139 MASK_UFS_CLK_GATE_BYPASS); 140 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 141 142 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 143 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 144 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 145 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 146 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 147 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 148 mdelay(1); 149 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 150 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 151 mdelay(20); 152 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 153 0x03300330); 154 155 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 156 do { 157 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 158 } while (data & PERI_UFS_BIT); 159 } 160 161 static void hikey960_init_ufs(void) 162 { 163 dw_ufs_params_t ufs_params; 164 165 memset(&ufs_params, 0, sizeof(ufs_params_t)); 166 ufs_params.reg_base = UFS_REG_BASE; 167 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 168 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 169 hikey960_ufs_reset(); 170 dw_ufs_init(&ufs_params); 171 } 172 173 /******************************************************************************* 174 * Gets SPSR for BL32 entry 175 ******************************************************************************/ 176 uint32_t hikey960_get_spsr_for_bl32_entry(void) 177 { 178 /* 179 * The Secure Payload Dispatcher service is responsible for 180 * setting the SPSR prior to entry into the BL3-2 image. 181 */ 182 return 0; 183 } 184 185 /******************************************************************************* 186 * Gets SPSR for BL33 entry 187 ******************************************************************************/ 188 #ifndef AARCH32 189 uint32_t hikey960_get_spsr_for_bl33_entry(void) 190 { 191 unsigned int mode; 192 uint32_t spsr; 193 194 /* Figure out what mode we enter the non-secure world in */ 195 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 196 197 /* 198 * TODO: Consider the possibility of specifying the SPSR in 199 * the FIP ToC and allowing the platform to have a say as 200 * well. 201 */ 202 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 203 return spsr; 204 } 205 #else 206 uint32_t hikey960_get_spsr_for_bl33_entry(void) 207 { 208 unsigned int hyp_status, mode, spsr; 209 210 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 211 212 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 213 214 /* 215 * TODO: Consider the possibility of specifying the SPSR in 216 * the FIP ToC and allowing the platform to have a say as 217 * well. 218 */ 219 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 220 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 221 return spsr; 222 } 223 #endif /* AARCH32 */ 224 225 int hikey960_bl2_handle_post_image_load(unsigned int image_id) 226 { 227 int err = 0; 228 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 229 #ifdef SPD_opteed 230 bl_mem_params_node_t *pager_mem_params = NULL; 231 bl_mem_params_node_t *paged_mem_params = NULL; 232 #endif 233 assert(bl_mem_params); 234 235 switch (image_id) { 236 #ifdef AARCH64 237 case BL32_IMAGE_ID: 238 #ifdef SPD_opteed 239 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 240 assert(pager_mem_params); 241 242 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 243 assert(paged_mem_params); 244 245 err = parse_optee_header(&bl_mem_params->ep_info, 246 &pager_mem_params->image_info, 247 &paged_mem_params->image_info); 248 if (err != 0) { 249 WARN("OPTEE header parse error.\n"); 250 } 251 #endif 252 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry(); 253 break; 254 #endif 255 256 case BL33_IMAGE_ID: 257 /* BL33 expects to receive the primary CPU MPID (through r0) */ 258 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 259 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry(); 260 break; 261 262 #ifdef SCP_BL2_BASE 263 case SCP_BL2_IMAGE_ID: 264 /* The subsequent handling of SCP_BL2 is platform specific */ 265 err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info); 266 if (err) { 267 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 268 } 269 break; 270 #endif 271 default: 272 /* Do nothing in default case */ 273 break; 274 } 275 276 return err; 277 } 278 279 /******************************************************************************* 280 * This function can be used by the platforms to update/use image 281 * information for given `image_id`. 282 ******************************************************************************/ 283 int bl2_plat_handle_post_image_load(unsigned int image_id) 284 { 285 return hikey960_bl2_handle_post_image_load(image_id); 286 } 287 288 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 289 u_register_t arg3, u_register_t arg4) 290 { 291 unsigned int id, uart_base; 292 293 generic_delay_timer_init(); 294 hikey960_read_boardid(&id); 295 if (id == 5300) 296 uart_base = PL011_UART5_BASE; 297 else 298 uart_base = PL011_UART6_BASE; 299 /* Initialize the console to provide early debug support */ 300 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 301 PL011_BAUDRATE, &console); 302 /* 303 * Allow BL2 to see the whole Trusted RAM. 304 */ 305 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 306 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 307 } 308 309 void bl2_el3_plat_arch_setup(void) 310 { 311 hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base, 312 bl2_el3_tzram_layout.total_size, 313 BL2_RO_BASE, 314 BL2_RO_LIMIT, 315 BL2_COHERENT_RAM_BASE, 316 BL2_COHERENT_RAM_LIMIT); 317 } 318 319 void bl2_platform_setup(void) 320 { 321 /* disable WDT0 */ 322 if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { 323 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); 324 mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0); 325 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0); 326 } 327 hikey960_clk_init(); 328 hikey960_pmu_init(); 329 hikey960_regulator_enable(); 330 hikey960_tzc_init(); 331 hikey960_peri_init(); 332 hikey960_pinmux_init(); 333 hikey960_gpio_init(); 334 hikey960_init_ufs(); 335 hikey960_io_setup(); 336 } 337