1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <debug.h> 11 #include <dw_mmc.h> 12 #include <errno.h> 13 #include <generic_delay_timer.h> 14 #include <mmc.h> 15 #include <mmio.h> 16 #include <pl011.h> 17 #include <pl061_gpio.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <tbbr_img_def.h> 22 #include "../../bl1/bl1_private.h" 23 #include "hi3798cv200.h" 24 #include "plat_private.h" 25 26 /* Data structure which holds the extents of the trusted RAM for BL1 */ 27 static meminfo_t bl1_tzram_layout; 28 static meminfo_t bl2_tzram_layout; 29 static console_pl011_t console; 30 31 /* 32 * Cannot use default weak implementation in bl1_main.c because BL1 RW data is 33 * not at the top of the secure memory. 34 */ 35 int bl1_plat_handle_post_image_load(unsigned int image_id) 36 { 37 image_desc_t *image_desc; 38 entry_point_info_t *ep_info; 39 40 if (image_id != BL2_IMAGE_ID) 41 return 0; 42 43 /* Get the image descriptor */ 44 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 45 assert(image_desc != NULL); 46 47 /* Get the entry point info */ 48 ep_info = &image_desc->ep_info; 49 50 bl2_tzram_layout.total_base = BL2_BASE; 51 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; 52 53 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); 54 55 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout; 56 57 VERBOSE("BL1: BL2 memory layout address = %p\n", 58 (void *)&bl2_tzram_layout); 59 60 return 0; 61 } 62 63 void bl1_early_platform_setup(void) 64 { 65 /* Initialize the console to provide early debug support */ 66 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, 67 PL011_BAUDRATE, &console); 68 69 /* Allow BL1 to see the whole Trusted RAM */ 70 bl1_tzram_layout.total_base = BL1_RW_BASE; 71 bl1_tzram_layout.total_size = BL1_RW_SIZE; 72 73 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 74 BL1_RAM_LIMIT - BL1_RAM_BASE); 75 } 76 77 void bl1_plat_arch_setup(void) 78 { 79 plat_configure_mmu_el3(bl1_tzram_layout.total_base, 80 bl1_tzram_layout.total_size, 81 BL1_RO_BASE, /* l-loader and BL1 ROM */ 82 BL1_RO_LIMIT, 83 BL_COHERENT_RAM_BASE, 84 BL_COHERENT_RAM_END); 85 } 86 87 void bl1_platform_setup(void) 88 { 89 int i; 90 #if !POPLAR_RECOVERY 91 struct mmc_device_info info; 92 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 93 #endif 94 95 generic_delay_timer_init(); 96 97 pl061_gpio_init(); 98 for (i = 0; i < GPIO_MAX; i++) 99 pl061_gpio_register(GPIO_BASE(i), i); 100 101 #if !POPLAR_RECOVERY 102 /* SoC-specific emmc register are initialized/configured by bootrom */ 103 INFO("BL1: initializing emmc\n"); 104 info.mmc_dev_type = MMC_IS_EMMC; 105 dw_mmc_init(¶ms, &info); 106 #endif 107 108 plat_io_setup(); 109 } 110 111 unsigned int bl1_plat_get_next_image_id(void) 112 { 113 return BL2_IMAGE_ID; 114 } 115