1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <debug.h> 11 #include <dw_mmc.h> 12 #include <errno.h> 13 #include <hi6220.h> 14 #include <hikey_def.h> 15 #include <hikey_layout.h> 16 #include <mmc.h> 17 #include <mmio.h> 18 #include <pl011.h> 19 #include <platform.h> 20 #include <string.h> 21 #include <tbbr/tbbr_img_desc.h> 22 23 #include "../../bl1/bl1_private.h" 24 #include "hikey_private.h" 25 26 /* Data structure which holds the extents of the trusted RAM for BL1 */ 27 static meminfo_t bl1_tzram_layout; 28 static console_pl011_t console; 29 30 enum { 31 BOOT_NORMAL = 0, 32 BOOT_USB_DOWNLOAD, 33 BOOT_UART_DOWNLOAD, 34 }; 35 36 meminfo_t *bl1_plat_sec_mem_layout(void) 37 { 38 return &bl1_tzram_layout; 39 } 40 41 /* 42 * Perform any BL1 specific platform actions. 43 */ 44 void bl1_early_platform_setup(void) 45 { 46 /* Initialize the console to provide early debug support */ 47 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 48 PL011_BAUDRATE, &console); 49 50 /* Allow BL1 to see the whole Trusted RAM */ 51 bl1_tzram_layout.total_base = BL1_RW_BASE; 52 bl1_tzram_layout.total_size = BL1_RW_SIZE; 53 54 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 55 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 56 } 57 58 /* 59 * Perform the very early platform specific architecture setup here. At the 60 * moment this only does basic initialization. Later architectural setup 61 * (bl1_arch_setup()) does not do anything platform specific. 62 */ 63 void bl1_plat_arch_setup(void) 64 { 65 hikey_init_mmu_el3(bl1_tzram_layout.total_base, 66 bl1_tzram_layout.total_size, 67 BL1_RO_BASE, 68 BL1_RO_LIMIT, 69 BL_COHERENT_RAM_BASE, 70 BL_COHERENT_RAM_END); 71 } 72 73 /* 74 * Function which will perform any remaining platform-specific setup that can 75 * occur after the MMU and data cache have been enabled. 76 */ 77 void bl1_platform_setup(void) 78 { 79 dw_mmc_params_t params; 80 struct mmc_device_info info; 81 82 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && 83 ((SRAM_BASE + SRAM_SIZE) >= 84 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE))); 85 hikey_sp804_init(); 86 hikey_gpio_init(); 87 hikey_pmussi_init(); 88 hikey_hi6553_init(); 89 90 hikey_rtc_init(); 91 92 hikey_mmc_pll_init(); 93 94 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 95 params.reg_base = DWMMC0_BASE; 96 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; 97 params.desc_size = 1 << 20; 98 params.clk_rate = 24 * 1000 * 1000; 99 params.bus_width = MMC_BUS_WIDTH_8; 100 params.flags = MMC_FLAG_CMD23; 101 info.mmc_dev_type = MMC_IS_EMMC; 102 dw_mmc_init(¶ms, &info); 103 104 hikey_io_setup(); 105 } 106 107 /* 108 * The following function checks if Firmware update is needed, 109 * by checking if TOC in FIP image is valid or not. 110 */ 111 unsigned int bl1_plat_get_next_image_id(void) 112 { 113 int32_t boot_mode; 114 unsigned int ret; 115 116 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 117 switch (boot_mode) { 118 case BOOT_USB_DOWNLOAD: 119 case BOOT_UART_DOWNLOAD: 120 ret = NS_BL1U_IMAGE_ID; 121 break; 122 default: 123 WARN("Invalid boot mode is found:%d\n", boot_mode); 124 panic(); 125 } 126 return ret; 127 } 128 129 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 130 { 131 unsigned int index = 0; 132 133 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 134 if (bl1_tbbr_image_descs[index].image_id == image_id) 135 return &bl1_tbbr_image_descs[index]; 136 137 index++; 138 } 139 140 return NULL; 141 } 142 143 void bl1_plat_set_ep_info(unsigned int image_id, 144 entry_point_info_t *ep_info) 145 { 146 uint64_t data = 0; 147 148 if (image_id == BL2_IMAGE_ID) 149 panic(); 150 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 151 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 152 do { 153 data |= 3 << 20; 154 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data)); 155 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 156 } while ((data & (3 << 20)) != (3 << 20)); 157 INFO("cpacr_el1:0x%llx\n", data); 158 159 ep_info->args.arg0 = 0xffff & read_mpidr(); 160 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 161 DISABLE_ALL_EXCEPTIONS); 162 } 163