| 265f1483 | 13-Oct-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(measured-boot): enable dynamic hash provisioning
Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algor
feat(measured-boot): enable dynamic hash provisioning
Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algorithm metadata at runtime. Add mboot_find_event_log_metadata() as a
common helper for resolving image metadata. Update the Event Log build
logic to use MAX_DIGEST_SIZE and MAX_HASH_COUNT, deprecate legacy
MBOOT_EL_HASH_ALG, and warn when it is used. Adjust MbedTLS
configuration to enable hash algorithms automatically when Measured Boot
is enabled.
Change-Id: I704e1a5005f6caad3d51d868bacc53699b6dd64f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 7bbb0086 | 09-Dec-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
feat: add TPM/TCG hashing helper to crypto module
Introduce crypto_mod_tcg_hash(), a helper that maps TPM/TCG algorithm
identifiers to the platform crypto backend. This ensures that Event Log
measur
feat: add TPM/TCG hashing helper to crypto module
Introduce crypto_mod_tcg_hash(), a helper that maps TPM/TCG algorithm
identifiers to the platform crypto backend. This ensures that Event Log
measurements use the same digest implementation as the platform PCR
backend regardless of whether hashing is performed in software,
hardware, or a discrete TPM. Update the measured boot design document,
expose the new API via public headers, and implement the helper in the
common crypto module.
Change-Id: Id4f7f1d0014ab42064c46819965417daef71555b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 8f7edf81 | 23-Jul-2025 |
Matthew Ellis <Matthew.Ellis@arm.com> |
refactor(tpm): remove TPM code from TF-A
git rm of TPM source and header files from platform tree.
Change-Id: I4d50d138166fe25b4d51bb3f1955797aa3d025ab
Signed-off-by: Matthew Ellis <Matthew.Ellis@a
refactor(tpm): remove TPM code from TF-A
git rm of TPM source and header files from platform tree.
Change-Id: I4d50d138166fe25b4d51bb3f1955797aa3d025ab
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>
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| 6963f715 | 11-Dec-2025 |
Matthew Ellis <Matthew.Ellis@arm.com> |
feat(tpm): changes to support TPM lib
The build system sets TPM_INTERFACE to FIFO_SPI, but this cannot be
tested by the C preprocessor. So, create new build define
TPM_INTERFACE_FIFO_SPI. Correct th
feat(tpm): changes to support TPM lib
The build system sets TPM_INTERFACE to FIFO_SPI, but this cannot be
tested by the C preprocessor. So, create new build define
TPM_INTERFACE_FIFO_SPI. Correct the #if statements to use it.
Make spi_init() in rpi3_spi.c static.
Pass timer functions as ops structure to TPM.
Remove implicit interface between TPM library and main firmware by
introducing explicit interface to allow firmware to pass structure
of function pointers to setup a timer and check whether it has elapsed.
Update build system for new TPM lib location.
Change #include statements in TPM source and header files to allow
for new directory structure.
Change-Id: Ie16b2e402b963161d7d4f35a187b9bd2765a1faa
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>
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| e9f69b9f | 02-Dec-2025 |
Kamlesh Gurudasani <kamlesh@ti.com> |
feat(clk): add get_possible_parents_num callback
This callback will be used to get number of possible parents if
the underlying clock driver supports this option.
Change-Id: I9459c878dd2155ff24b72c
feat(clk): add get_possible_parents_num callback
This callback will be used to get number of possible parents if
the underlying clock driver supports this option.
Change-Id: I9459c878dd2155ff24b72cef6851180e105be432
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
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| a6d29969 | 25-Nov-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
fix(gicv5): align IWB_WDOMAINR to the EAC spec
The offset changed from 0x6000 to 0x8000.
Change-Id: I3a95e16c5379e2bb200a1ffaf40e3bae73288c5a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> |
| 1c63cd61 | 06-Nov-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "qti-rb3gen2" into integration
* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio
Merge changes from topic "qti-rb3gen2" into integration
* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot
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| 8f64ed92 | 30-Oct-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "upstream_deassert_ddr_reset" into integration
* changes:
feat(s32g274ardb): add DDR clock source support
feat(s32g274ardb): add mc_rgm_release_periph func |
| d3e47fb7 | 18-Oct-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR
Rename this register to be aligned with the reference manual.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change
feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR
Rename this register to be aligned with the reference manual.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ia10c287bf4068742a7add9016c1a87e300eebff0
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| 8934c7b0 | 26-Feb-2025 |
Maxime Méré <maxime.mere@foss.st.com> |
feat(st-drivers): add RIFSC driver
RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:
-RISC registers(slave periph
feat(st-drivers): add RIFSC driver
RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:
-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.
This doesn't support semaphore acquisition.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iba4cdbf53243292fa0b42cad8392c43734dd9bc2
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| 867cd155 | 08-Mar-2021 |
Pankaj Dev <pankaj.dev@st.com> |
feat(st-usb): add USB DWC3 driver
Initial patch for usb-dwc3 driver in STM32MP2 for USB-DFU Mode
Change-Id: Ia63bd7fcd77403c7fe2dca2709021cab31b3b508
Signed-off-by: Maxime Méré <maxime.mere@foss.st
feat(st-usb): add USB DWC3 driver
Initial patch for usb-dwc3 driver in STM32MP2 for USB-DFU Mode
Change-Id: Ia63bd7fcd77403c7fe2dca2709021cab31b3b508
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
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| c0cbf5ad | 01-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
i
feat(s32g274ardb): add DDR clock source support
Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.
These utilities are required before
initializing the DDR subsystem.
Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| 684952d1 | 27-Dec-2024 |
Kamlesh Gurudasani <kamlesh@ti.com> |
feat(scmi): add support for discovering and changing parent clocks
Add base support for discovering and changing parent clocks
This is the part of SCMI platform design document version 3.2,
which i
feat(scmi): add support for discovering and changing parent clocks
Add base support for discovering and changing parent clocks
This is the part of SCMI platform design document version 3.2,
which introduces SCMI clock protocol version 3.0
Add mandatory support for CLOCK_CONFIG_GET which is needed
for SCMI clock protocol version 3.0
Also, add support for clock_enable_delay parameter which got
introduced as new parameter in return values for command
CLOCK_ATTRIBUTES in same SCMI Platform design document v3.2
Change-Id: Ie5cba83dad27bf1e3b51c11c0218259a44c1af59
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
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|
| 292ffc06 | 25-Sep-2025 |
Sumit Garg <sumit.garg@oss.qualcomm.com> |
feat(qti): introduce basic XPU driver
Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.
Change-Id: I2b5ad50c
feat(qti): introduce basic XPU driver
Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.
Change-Id: I2b5ad50c57b0112302d3568e0e0bcf2116d3e259
Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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|
| 1b9f8ec7 | 25-Sep-2025 |
Sumit Garg <sumit.garg@oss.qualcomm.com> |
refactor(qti): refactor RNG as a proper driver
Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.
Change-Id: I
refactor(qti): refactor RNG as a proper driver
Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.
Change-Id: I4c1f23b7ea2f17fdb71792319b4c403db542b757
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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|
| 5affb6a7 | 16-Oct-2025 |
Slava Andrianov <slava.andrianov@arm.com> |
feat(mbedtls): update mbedtls to version 3.6.5
Change-Id: Ia5366faa71007024e098a05ee391a2ff8e8676c0
Signed-off-by: Slava Andrianov <slava.andrianov@arm.com> |
| 7b370c19 | 21-Aug-2025 |
Vincent Jardin <vjardin@free.fr> |
feat(flexspi): add 128Mbytes flash info
Those 4 nor flash have the same geometry:
Micron MT25QU01GBBB
GigaDevice GD55LB01GF
Macronix MX66U1G45G
Winbond W25Q01NW
Signed-off-by: Vincent Jardi
feat(flexspi): add 128Mbytes flash info
Those 4 nor flash have the same geometry:
Micron MT25QU01GBBB
GigaDevice GD55LB01GF
Macronix MX66U1G45G
Winbond W25Q01NW
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Change-Id: Iff74461ef3b252fc0f07745317d9860bd42c1ba1
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| 6f7f8b18 | 29-Jun-2025 |
Girisha Dengi <girisha.dengi@altera.com> |
fix(intel): update nand driver to enable Linux OS boot
Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.
Change-Id: If592680ef359
fix(intel): update nand driver to enable Linux OS boot
Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.
Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| 1f866fc9 | 18-Sep-2025 |
Amr Mohamed <amr.mohamed@arm.com> |
feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
co
feat(dsu): enable PMU registers access at EL1
- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.
Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
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| 0d65d5a4 | 19-Feb-2025 |
David Hu <david.hu2@arm.com> |
feat(gicv3): add GIC-720AE model id
Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.
Change-Id: Id6ca8144b0c02
feat(gicv3): add GIC-720AE model id
Add GIC-720AE model id to power up its Redistributor in BL31 GIC
initialization.
No use case so far for multichip support on GIC-720AE.
Change-Id: Id6ca8144b0c02557ba7569a536cece37e4c1fe98
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| 3537dad5 | 16-Jul-2025 |
Xialin Liu <xialin.liu@arm.com> |
feat(guid-partition): platform hook to log corrupted GPT
Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information
feat(guid-partition): platform hook to log corrupted GPT
Notification of the GPT corruption can be beneficial,
using the handoff structure from BL2 to
BL32 for logging the GPT corruption information
Change-Id: Ie1af7eb6d97ec76f3f6d1cffad292782bdedda21
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
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| 24d6ed9f | 14-Jul-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
feat(mbedtls): update mbedtls to version 3.6.4
In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locatio
feat(mbedtls): update mbedtls to version 3.6.4
In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locations of some helper functions. This is currently an open
issue for mbedtls: https://github.com/Mbed-TLS/mbedtls/issues/10376
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I57c9c14aabe75a51c74dcf2a33faf59f95ce2386
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| b67e9846 | 13-May-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
build(measured-boot)!: move to ext event log lib
Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, an
build(measured-boot)!: move to ext event log lib
Removes in-tree Event Log library implementation and updates all
references to use the external submodule. Updates include paths,
Makefile macros, and platform integration logic to link with lib as a
static library.
If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:
git submodule update --init --recursive
BREAKING-CHANGE: LibEventLog is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.
Change-Id: I723f493033c178759a45ea04118e7cc295dc2438
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| b32a1111 | 26-Aug-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration
* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra viol
Merge changes from topic "xlnx_misra_fix_gen_gicv3" into integration
* changes:
fix(gicv3): typecast operands to match data type
fix(gicv3): add missing curly braces
fix(gicv3): fix misra violation 12.1
fix(gicv3): match function definition and declaration
fix(gicv3): typecast operands to match data type
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| eaa454ac | 17-Mar-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(gicv3): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di
fix(gicv3): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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