Merge "fix(cpus): workaround for Cortex-A65AE erratum 1638571" into integration

fix(cpus): workaround for Cortex-A65AE erratum 1638571

Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A65AE erratum 1638571

Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest

Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): remove C1-Premium erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Premium erratum 3651221 [2] support.

fix(cpus): remove C1-Premium erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Premium erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111078/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I40b37ec62788884ae5c0a0bb3eb4b924622ffe55

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fix(cpus): remove C1-Ultra erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1]

fix(cpus): remove C1-Ultra erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111077/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If7ea433e4614f92333e788e3f6b366db22c92f0d

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fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

Fix the CVE-2024-7881 [1] workaround for C1-Pro. The previously
implemented erratum 3684268 [2] programmed the same control bit

fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

Fix the CVE-2024-7881 [1] workaround for C1-Pro. The previously
implemented erratum 3684268 [2] programmed the same control bit and
overlapped functionally with the CVE workaround, so the duplicate
erratum is removed.

Reference:
[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-3273080/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6207c49486e4020f34c862ad40ec3137bd3684cc

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fix(security): add workaround for CVE-2025-0647

This workaround fixes an issue with the CPP RCTX instruction by
issuing an instruction patch sequence to trap uses of the CPP RCTX
instruction from EL

fix(security): add workaround for CVE-2025-0647

This workaround fixes an issue with the CPP RCTX instruction by
issuing an instruction patch sequence to trap uses of the CPP RCTX
instruction from EL0, EL1, and EL2 to EL3 and perform a workaround
procedure using the implementation defined trap handler to ensure
the correct behavior of the system. In addition, it includes an EL3
API to be used if EL3 firmware needs to use the CPP RCTX instruction.
This saves the overhead of exception handling, and EL3 does not
generically support trapping EL3->EL3, and adding support for that
is not trivial due to the implications for context management.

The issue affects the following CPUs:

C1-Premium
C1-Ultra
Cortex-A710
Cortex-X2
Cortex-X3
Cortex-X4
Cortex-X925
Neoverse N2
Neoverse V2
Neoverse V3
Neoverse V3AE (handled same as V3 CPU in TF-A CPU-Lib)

Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546

Change-Id: I5e7589afbeb69ebb79c01bec80e29f572aff3d89
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): enable Neoverse-V2 external LLC support

Change-Id: I9582c7405db6862e77db240822e241d4082966f2
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

Merge "fix(build): use ARM_ARCH_FEATURE instead of -march directly" into integration

Merge changes from topic "xl/n2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-N2 erratum 2138953
fix(cpus): workaround for Neoverse-N2 erratum 4302970
fix(cpus): worka

Merge changes from topic "xl/n2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-N2 erratum 2138953
fix(cpus): workaround for Neoverse-N2 erratum 4302970
fix(cpus): workaround for Neoverse-N2 erratum 3888123
refactor(cpus): reorder the errratum build flag for Neoverse-N2

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Merge changes from topic "xl/cortex-x3-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 4302966
fix(cpus): workaround for Cortex-X3 erratum 3888125

Merge changes from topic "xl/cortex-x2-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 4302969
fix(cpus): workaround for Cortex-X2 erratum 3888122

fix(cpus): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 that applies to revisions
r0p0, r0p1, r0p2 and r0p3, and is still open.

The erratum can be avoided by executing a s

fix(cpus): workaround for Neoverse-N2 erratum 2138953

Neoverse-N2 erratum 2138953 that applies to revisions
r0p0, r0p1, r0p2 and r0p3, and is still open.

The erratum can be avoided by executing a specific instruction
sequence when disabling the hardware prefetcher.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: Ie465328e87754a1ec511a2f77243b4b0b09134cc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-N2 erratum 4302970

Neoverse-N2 erratum 4302970 that applies to revisions
r0p0, r0p1, r0p2, r0p3, and is still open.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Neoverse-N2 erratum 4302970

Neoverse-N2 erratum 4302970 that applies to revisions
r0p0, r0p1, r0p2, r0p3, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I2436b11a36be204d549522f1176fcd49658c044c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-N2 erratum 3888123

Neoverse-N2 erratum 3888123 that applies to r0p0, r0p1,
r0p2 and r0p3, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] t

fix(cpus): workaround for Neoverse-N2 erratum 3888123

Neoverse-N2 erratum 3888123 that applies to r0p0, r0p1,
r0p2 and r0p3, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I6240d263fb5d153721b5b84a37df2f24e3d02d86
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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refactor(cpus): reorder the errratum build flag for Neoverse-N2

The erratum build flag is not in ascending for Neoverse-N2 cpu.
Reorder the build flag.

Change-Id: Ifb736adf8f06bf6202784bdeac51c0251

refactor(cpus): reorder the errratum build flag for Neoverse-N2

The erratum build flag is not in ascending for Neoverse-N2 cpu.
Reorder the build flag.

Change-Id: Ifb736adf8f06bf6202784bdeac51c02512519782
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1

fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I284ee7fe611c4c9861696fde62f796e6fae6dff6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting

fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I5c01dfcffc6e56163aba03428e21fedee8cc7042
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/v2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 4302968
fix(cpus): workaround for Neoverse-V2 erratum 3888126

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FE

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FEATURE. Setting -march directly can lead to unexpected results
when using the above flags and is generally not recommended within tfa.

This patch migrates all instances of -march=armv8-a+crc to
ARM_ARCH_FEATURE=crc. Arm platforms (via arm_common.mk) are checked and
those that support cores greater than arm8.1 do not get the flag as it
is automatically pulled in.

Change-Id: I846f97367eab9529524a2805d5b87d34cce2360f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): workaround for Cortex-A76AE erratum 2753838" into integration

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_E

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I42b27e19d61a7f9c57efe1b5f5336d165eb98210
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[2

fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I4068aa73d38a70c00d66bb894169be2659d67de7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I6c5de5843f2199fa697f8336558fa56a87ee846d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[

fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I368cfdd216ea5875b81640415ff71b15f46ea953
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by addin

fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by adding a DSB instruction before
the ISB of the power-down code sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/latest/

Change-Id: I338834a21c14879faee5280876a59153d549cb7b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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