1# 2# Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Making sure the Morello platform type is specified 8ifeq ($(filter ${TARGET_PLATFORM}, fvp soc),) 9 $(error TARGET_PLATFORM must be fvp or soc) 10endif 11 12MORELLO_BASE := plat/arm/board/morello 13 14PLAT_INCLUDES := -I${MORELLO_BASE}/include 15 16MORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S 17 18# GIC-600 configuration 19USE_GIC_DRIVER := 3 20GICV3_SUPPORT_GIC600 := 1 21# FEAT_CRC32 is impelemented in the armv8.0 core 22ARM_ARCH_FEATURE := crc 23 24PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \ 25 ${MORELLO_BASE}/aarch64/morello_helper.S 26 27BL1_SOURCES := ${MORELLO_CPU_SOURCES} \ 28 ${MORELLO_BASE}/morello_err.c \ 29 ${MORELLO_BASE}/morello_trusted_boot.c \ 30 ${MORELLO_BASE}/morello_bl1_setup.c \ 31 drivers/arm/sbsa/sbsa.c 32 33BL2_SOURCES := ${MORELLO_BASE}/morello_security.c \ 34 ${MORELLO_BASE}/morello_err.c \ 35 ${MORELLO_BASE}/morello_trusted_boot.c \ 36 ${MORELLO_BASE}/morello_bl2_setup.c \ 37 ${MORELLO_BASE}/morello_image_load.c \ 38 lib/utils/mem_region.c \ 39 drivers/arm/css/sds/sds.c 40 41BL31_SOURCES := ${MORELLO_CPU_SOURCES} \ 42 ${MORELLO_BASE}/morello_bl31_setup.c \ 43 ${MORELLO_BASE}/morello_pm.c \ 44 ${MORELLO_BASE}/morello_topology.c \ 45 ${MORELLO_BASE}/morello_security.c \ 46 drivers/arm/css/sds/sds.c 47 48FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts \ 49 ${MORELLO_BASE}/fdts/morello_fw_config.dts \ 50 ${MORELLO_BASE}/fdts/morello_tb_fw_config.dts \ 51 ${MORELLO_BASE}/fdts/morello_nt_fw_config.dts 52 53FW_CONFIG := ${BUILD_PLAT}/fdts/morello_fw_config.dtb 54HW_CONFIG := ${BUILD_PLAT}/fdts/morello-${TARGET_PLATFORM}.dtb 55TB_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_tb_fw_config.dtb 56NT_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_nt_fw_config.dtb 57 58# Add the FW_CONFIG to FIP and specify the same to certtool 59$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 60# Add the HW_CONFIG to FIP and specify the same to certtool 61$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 62# Add the TB_FW_CONFIG to FIP and specify the same to certtool 63$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 64# Add the NT_FW_CONFIG to FIP and specify the same to certtool 65$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) 66 67MORELLO_FW_NVCTR_VAL := 0 68TFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL} 69NTFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL} 70 71# TF-A not required to load the SCP Images 72override CSS_LOAD_SCP_IMAGES := 0 73 74override NEED_BL2U := no 75 76# 32 bit mode not supported 77override CTX_INCLUDE_AARCH32_REGS := 0 78 79override ARM_PLAT_MT := 1 80 81override ARM_BL31_IN_DRAM := 1 82 83override PSCI_EXTENDED_STATE_ID := 1 84override ARM_RECOM_STATE_ID_ENC := 1 85 86# Errata workarounds: 87ERRATA_N1_1868343 := 1 88 89# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 90# SCP during power management operations and for SCP RAM Firmware transfer. 91CSS_USE_SCMI_SDS_DRIVER := 1 92 93# System coherency is managed in hardware 94HW_ASSISTED_COHERENCY := 1 95 96# When building for systems with hardware-assisted coherency, there's no need to 97# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 98USE_COHERENT_MEM := 0 99 100# Add TARGET_PLATFORM to differentiate between Morello FVP and Morello SoC platform 101$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) 102 103# Add MORELLO_FW_NVCTR_VAL 104$(eval $(call add_define,MORELLO_FW_NVCTR_VAL)) 105 106include plat/arm/common/arm_common.mk 107include plat/arm/css/common/css_common.mk 108include plat/arm/board/common/board_common.mk 109