1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45- ``WORKAROUND_CVE_2025_0647``: Enables mitigation for `CVE-2025-0647`. 46 This build option should be set to 1 if the target platform contains at 47 least 1 CPU that requires this mitigation. Defaults to 1. 48 49.. _arm_cpu_macros_errata_workarounds: 50 51CPU Errata Workarounds 52---------------------- 53 54TF-A exports a series of build flags which control the errata workarounds that 55are applied to each CPU by the reset handler. The errata details can be found 56in the CPU specific errata documents published by Arm: 57For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 58 59The errata workarounds are implemented for a particular revision or a set of 60processor revisions. This is checked by the reset handler at runtime. Each 61errata workaround is identified by its ``ID`` as specified in the processor's 62errata notice document. The format of the define used to enable/disable the 63errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 64is for example ``A57`` for the ``Cortex_A57`` CPU. 65 66Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 67write errata workaround functions. 68 69All workarounds are disabled by default. The platform is responsible for 70enabling these workarounds according to its requirement by defining the 71errata workaround build flags in the platform specific makefile. In case 72these workarounds are enabled for the wrong CPU revision then the errata 73workaround is not applied. In the DEBUG build, this is indicated by 74printing a warning to the crash console. 75 76In the current implementation, a platform which has more than 1 variant 77with different revisions of a processor has no runtime mechanism available 78for it to specify which errata workarounds should be enabled or not. 79 80The value of the build flags is 0 by default, that is, disabled. A value of 1 81will enable it. 82 83For Cortex-A9, the following errata build flags are defined : 84 85- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 86 CPU. This needs to be enabled for all revisions of the CPU. 87 88For Cortex-A15, the following errata build flags are defined : 89 90- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 91 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 92 93- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 94 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 95 96For Cortex-A17, the following errata build flags are defined : 97 98- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 99 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 100 101- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 102 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 103 104For Cortex-A35, the following errata build flags are defined : 105 106- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 107 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 108 109For Cortex-A53, the following errata build flags are defined : 110 111- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 112 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 113 114- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 115 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 116 117- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 118 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 119 120- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 121 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 122 123- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 124 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 125 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 126 sections. 127 128- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 129 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 130 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 131 ``A53_DISABLE_NON_TEMPORAL_HINT``. 132 133- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 134 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 135 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 136 which are 4kB aligned. 137 138- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 139 CPUs. Though the erratum is present in every revision of the CPU, 140 this workaround is only applied to CPUs from r0p3 onwards, which feature 141 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 142 Earlier revisions of the CPU have other errata which require the same 143 workaround in software, so they should be covered anyway. 144 145- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 146 revisions of Cortex-A53 CPU. 147 148For Cortex-A55, the following errata build flags are defined : 149 150- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 151 CPU. This needs to be enabled only for revision r0p0 of the CPU. 152 153- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 154 CPU. This needs to be enabled only for revision r0p0 of the CPU. 155 156- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 157 CPU. This needs to be enabled only for revision r0p0 of the CPU. 158 159- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 160 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 161 162- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 163 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 164 165- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 166 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 167 168- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 169 revisions of Cortex-A55 CPU. 170 171For Cortex-A57, the following errata build flags are defined : 172 173- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 174 CPU. This needs to be enabled only for revision r0p0 of the CPU. 175 176- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 177 CPU. This needs to be enabled only for revision r0p0 of the CPU. 178 179- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 180 CPU. This needs to be enabled only for revision r0p0 of the CPU. 181 182- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 183 CPU. This needs to be enabled only for revision r0p0 of the CPU. 184 185- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 186 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 187 188- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 189 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 190 191- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 192 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 193 194- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 195 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 196 197- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 198 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 199 200- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 201 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 202 203- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 204 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 205 206- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 207 revisions of Cortex-A57 CPU. 208 209For Cortex-A65, the following errata build flags are defined : 210 211- ``ERRATA_A65_1179935``: This applies errata 1179935 workaround to Cortex-A65 212 CPU. This needs to be enabled only for revision r0p0 of the CPU, and is fixed 213 in r1p0. 214 215- ``ERRATA_A65_1227419``: This applies errata 1227419 workaround to Cortex-A65 216 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU and 217 is fixed in r1p1. 218 219- ``ERRATA_A65_1541130``: This applies errata 1541130 workaround to r0p0, r1p0, 220 r1p1, r1p2 revisions of the CPU and is still open. 221 222For Cortex-A65AE, the following errata build flags are defined : 223 224- ``ERRATA_A65AE_1638571``: This applies errata 1638571 workaround to Cortex-A65AE 225 CPU. This needs to be enabled r0p0, r1p0, r1p1 revisions of the CPU and is still 226 open. 227 228For Cortex-A72, the following errata build flags are defined : 229 230- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 231 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 232 233- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 234 revisions of Cortex-A72 CPU. 235 236For Cortex-A73, the following errata build flags are defined : 237 238- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 239 CPU. This needs to be enabled only for revision r0p0 of the CPU. 240 241- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 242 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 243 244For Cortex-A75, the following errata build flags are defined : 245 246- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 247 CPU. This needs to be enabled only for revision r0p0 of the CPU. 248 249- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 250 CPU. This needs to be enabled only for revision r0p0 of the CPU. 251 252For Cortex-A76, the following errata build flags are defined : 253 254- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 255 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 256 257- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 258 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 259 260- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 261 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 262 263- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 264 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 265 266- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 267 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 268 269- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 270 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 271 272- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 273 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 274 275- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 276 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 277 278- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 279 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 280 limitation of errata framework this errata is applied to all revisions 281 of Cortex-A76 CPU. 282 283- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 284 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 285 286- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 287 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 288 289- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 290 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 291 still open. 292 293For Cortex-A76AE, the following errata build flags are defined : 294 295- ``ERRATA_A76AE_1931427``: This applies errata 1931427 workaround to Cortex-A76AE 296 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 297 fixed in r1p1. 298 299- ``ERRATA_A76AE_1931435``: This applies errata 1931435 workaround to Cortex-A76AE 300 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 301 fixed in r1p1. 302 303- ``ERRATA_A76AE_1969401``: This applies errata 1969401 workaround to Cortex-A76AE 304 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 305 fixed in r1p1. 306 307- ``ERRATA_A76AE_2371140``: This applies errata 2371140 workaround to Cortex-A76AE 308 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 309 still open. 310 311- ``ERRATA_A76AE_2753838``: This applies errata 2753838 workaround to Cortex-A76AE 312 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 313 still open. 314 315For Cortex-A77, the following errata build flags are defined : 316 317- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 318 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 319 320- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 321 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 322 323- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 324 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 325 326- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 327 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 328 329- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 330 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 331 332 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 333 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 334 335 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 336 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 337 338For Cortex-A78, the following errata build flags are defined : 339 340- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 341 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 342 343- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 344 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 345 346- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 347 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 348 issue but there is no workaround for that revision. 349 350- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 351 CPU. This needs to be enabled for revisions r0p0 and r1p0. 352 353- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 354 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 355 356- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 357 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 358 is present in r0p0 but there is no workaround. It is still open. 359 360- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 361 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 362 it is still open. 363 364- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 365 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 366 it is still open. 367 368- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 369 CPU, this erratum affects system configurations that do not use an ARM 370 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 371 and r1p2 and it is still open. 372 373- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 374 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 375 it is still open. 376 377- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 378 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 379 it is still open. 380 381- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 382 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 383 it is still open. 384 385For Cortex-A78AE, the following errata build flags are defined : 386 387- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 388 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 389 This erratum is still open. 390 391- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 392 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 393 erratum is still open. 394 395- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 396 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 397 This erratum is still open. 398 399- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 400 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 401 erratum is still open. 402 403- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 404 Cortex-A78AE CPU. This erratum affects system configurations that do not use 405 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 406 r0p2. This erratum is still open. 407 408For Cortex-A78C, the following errata build flags are defined : 409 410- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 411 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 412 fixed in r0p1. 413 414- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 415 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 416 fixed in r0p1. 417 418- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 419 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 420 it is still open. 421 422- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 423 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 424 erratum is still open. 425 426- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 427 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 428 erratum is still open. 429 430- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 431 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 432 erratum is still open. 433 434- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 435 Cortex-A78C CPU, this erratum affects system configurations that do not use 436 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 437 and is still open. 438 439- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 440 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 441 This erratum is still open. 442 443- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 444 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 445 This erratum is still open. 446 447- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 448 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 449 This erratum is still open. 450 451For Cortex-X1 CPU, the following errata build flags are defined: 452 453- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 454 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 455 456- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 457 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 458 459- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 460 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 461 462For Neoverse N1, the following errata build flags are defined : 463 464- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 465 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 466 467- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 468 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 469 470- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 471 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 472 473- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 474 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 475 476- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 477 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 478 479- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 480 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 481 482- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 483 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 484 485- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 486 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 487 488- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 489 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 490 491- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 492 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 493 494- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 495 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 496 497- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 498 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 499 500- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 501 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 502 revisions r0p0, r1p0, and r2p0 there is no workaround. 503 504- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 505 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 506 still open. 507 508- ``ERRATA_N1_3324349``: This applies errata 3324349 workaround to Neoverse-N1 509 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 510 still open. 511 512For Neoverse V1, the following errata build flags are defined : 513 514- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 515 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 516 r1p0. 517 518- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 519 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 520 in r1p1. 521 522- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 523 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 524 in r1p1. 525 526- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 527 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 528 in r1p1. 529 530- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 531 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 532 533- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 534 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 535 CPU. 536 537- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 538 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 539 issue is present in r0p0 as well but there is no workaround for that 540 revision. It is still open. 541 542- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 543 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 544 CPU. It is still open. 545 546- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 547 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 548 issue is present in r0p0 as well but there is no workaround for that 549 revision. It is still open. 550 551- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 552 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 553 the CPU. 554 555- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 556 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 557 It has been fixed in r1p2. 558 559- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 560 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 561 It is still open. 562 563- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 564 CPU, this erratum affects system configurations that do not use an ARM 565 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 566 It has been fixed in r1p2. 567 568- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 569 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 570 CPU. It is still open. 571 572- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 573 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 574 CPU. It is still open. 575 576- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 577 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 578 CPU. It is still open. 579 580For Neoverse V2, the following errata build flags are defined : 581 582- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 583 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 584 r0p2. 585 586- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 587 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 588 r0p2. 589 590- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 591 CPU, this affects system configurations that do not use and ARM interconnect 592 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 593 in r0p2. 594 595- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 596 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 597 r0p2. 598 599- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 600 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 601 r0p2. 602 603- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 604 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 605 r0p2. 606 607- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 608 CPU, this affects all configurations. This needs to be enabled for revisions 609 r0p0 and r0p1. It has been fixed in r0p2. 610 611- ``ERRATA_V2_3442699``: This applies errata 3442699 workaround to Neoverse-V2 612 CPU. This needs to be enabled for revision r0p0 - r0p2 and is still open. 613 614- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 615 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 616 still open. 617 618- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 619 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 620 the CPU. It is fixed in r0p2. 621 622- ``ERRATA_V2_3888126``: This applies errata 3888126 workaround to Neoverse-V2 623 CPU. This needs to be enabled only for revisions r0p0, r0p1, r0p2 of 624 the CPU. It is still open. 625 626- ``ERRATA_V2_4302968``: This applies errata 4302968 workaround to Neoverse-V2 627 CPU. This needs to be enabled only for revisions r0p0, r0p1, r0p2 of 628 the CPU. It is still open. 629 630For Neoverse V3, the following errata build flags are defined : 631 632- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 633 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 634 635- ``ERRATA_V3_3312417``: This applies errata 3312417 workaround to Neoverse-V3 636 CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and is 637 fixed in r0p2. 638 639- ``ERRATA_V3_3696307``: This applies errata 3696307 workaround to Neoverse-V3 640 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 641 r0p2. 642 643- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 644 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 645 is still open. 646 647- ``ERRATA_V3_3734562``: This applies errata 3734562 workaround to Neoverse-V3 648 CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and 649 is fixed in r0p2. 650 651- ``ERRATA_V3_3782181``: This applies errata 3782181 workaround to Neoverse-V3 652 CPU. This needs to be enabled for revision r0p1 of the CPU and is fixed in 653 r0p2. 654 655- ``ERRATA_V3_3864536``: This applies errata 3864536 workaround to Neoverse-V3 656 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and 657 is still open. 658 659- ``ERRATA_V3_3878291``: This applies errata 3878291 workaround to Neoverse-V3 660 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and 661 is still open. 662 663For Cortex-A710, the following errata build flags are defined : 664 665- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 666 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 667 been fixed in r2p0. 668 669- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 670 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 671 It has been fixed in r2p0. 672 673- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 674 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 675 It has been fixed in r2p0. 676 677- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 678 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 679 It has been fixed in r2p0. 680 681- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 682 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 683 r2p0 of the CPU. It is still open. 684 685- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 686 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 687 r2p0 of the CPU. It is still open. 688 689- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 690 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 691 and is still open. 692 693- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 694 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 695 of the CPU and is still open. 696 697- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 698 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 699 is still open. 700 701- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 702 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 703 of the CPU and is fixed in r2p1. 704 705- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 706 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 707 of the CPU and is fixed in r2p1. 708 709- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 710 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 711 and is fixed in r2p1. 712 713- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 714 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 715 of the CPU and is fixed in r2p1. 716 717- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 718 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 719 r2p1 of the CPU and is still open. 720 721- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 722 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 723 of the CPU and is fixed in r2p1. 724 725- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 726 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 727 of the CPU and is fixed in r2p1. 728 729- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 730 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 731 of the CPU and is fixed in r2p1. 732 733- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 734 CPU, and applies to system configurations that do not use and ARM 735 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 736 is still open. 737 738- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 739 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 740 r2p1 of the CPU and is still open. 741 742- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 743 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 744 r2p1 of the CPU and is still open. 745 746- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 747 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 748 CPU and is still open. 749 750- ``ERRATA_A710_3324338``: This applies errata 3324338 workaround to 751 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 752 r2p1 of the CPU and is still open. 753 754- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 755 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 756 CPU and is still open. 757 758For Neoverse N2, the following errata build flags are defined : 759 760- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 761 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 762 763- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 764 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 765 766- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 767 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 768 769- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 770 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 771 772- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 773 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3 of the 774 Neoverse N2 cpu and is still open. 775 776- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 777 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 778 779- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 780 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 781 782- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 783 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 784 785- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 786 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 787 788- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 789 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 790 791- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 792 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 793 794- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 795 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 796 r0p1. 797 798- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 799 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 800 r0p1. 801 802- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 803 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 804 it is fixed in r0p3. 805 806- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 807 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 808 809- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 810 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 811 r0p1. 812 813- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 814 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 815 in r0p3. 816 817- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 818 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 819 in r0p3. 820 821- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 822 CPU, this erratum affects system configurations that do not use and ARM 823 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 824 It is fixed in r0p3. 825 826- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 827 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 828 in r0p3. 829 830- ``ERRATA_N2_3324339``: This applies errata 3324339 workaround to Neoverse-N2 831 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 832 still open. 833 834- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 835 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 836 still open. 837 838- ``ERRATA_N2_3888123``: This applies errata 3888123 workaround to Neoverse-N2 839 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 840 still open. 841 842- ``ERRATA_N2_4302970``: This applies errata 4302970 workaround to Neoverse-N2 843 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 844 still open. 845 846For Neoverse N3, the following errata build flags are defined : 847 848- ``ERRATA_N3_3456111``: This applies errata 3456111 workaround to Neoverse-N3 849 CPU. This needs to be enabled for revisions r0p0 and r0p1 and is still open. 850 851- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 852 CPU. This needs to be enabled for revisions r0p0 and is still open. 853 854For Cortex-X2, the following errata build flags are defined : 855 856- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 857 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 858 859- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 860 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 861 is fixed in r2p0. 862 863- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 864 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 865 is fixed in r2p0. 866 867- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 868 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 869 is fixed in r2p0. 870 871- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 872 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 873 in r2p0. 874 875- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 876 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 877 CPU, it is fixed in r2p1. 878 879- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 880 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 881 CPU, it is fixed in r2p1. 882 883- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 884 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 885 CPU, it is fixed in r2p1. 886 887- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 888 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 889 in r2p1. 890 891- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 892 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 893 CPU, it is fixed in r2p1. 894 895- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 896 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 897 in r2p1. 898 899- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 900 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 901 CPU, it is fixed in r2p1. 902 903- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 904 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 905 CPU, it is fixed in r2p1. 906 907- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 908 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 909 CPU and is still open. 910 911- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 912 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 913 CPU, it is fixed in r2p1. 914 915- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 916 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 917 CPU, it is fixed in r2p1. 918 919- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 920 CPU and affects system configurations that do not use an Arm interconnect IP. 921 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 922 still open. 923 924- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 925 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 926 CPU and is still open. 927 928- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 929 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 930 CPU and is still open. 931 932- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 933 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 934 CPU and is still open. 935 936- ``ERRATA_X2_3324338``: This applies errata 3324338 workaround to Cortex-X2 937 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 938 CPU and is still open. 939 940- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 941 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 942 CPU and is still open. 943 944- ``ERRATA_X2_3888122``: This applies errata 3888122 workaround to Cortex-X2 945 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 946 CPU and is still open. 947 948- ``ERRATA_X2_4302969``: This applies errata 4302969 workaround to Cortex-X2 949 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 950 CPU and is still open. 951 952For Cortex-X3, the following errata build flags are defined : 953 954- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 955 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 956 is fixed in r1p1. 957 958- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 959 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 960 fixed in r1p2. 961 962- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 963 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 964 of the CPU, it is fixed in r1p1. 965 966- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 967 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 968 of the CPU, it is fixed in r1p1. 969 970- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 971 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 972 CPU, it is fixed in r1p2. 973 974- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 975 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 976 It is fixed in r1p1. 977 978- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 979 CPU and affects system configurations that do not use an ARM interconnect 980 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 981 in r1p2. 982 983- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 984 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 985 r1p1. It is fixed in r1p2. 986 987- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 988 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 989 fixed in r1p2. 990 991- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 992 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 993 CPU. It is fixed in r1p2. 994 995- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 996 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 997 of the CPU. It is still open. 998 999- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 1000 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 1001 of the CPU. It is still open. 1002 1003- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 1004 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 1005 of the CPU and it is still open. 1006 1007- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 1008 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 1009 the CPU. It is fixed in r1p2. 1010 1011- ``ERRATA_X3_3888125``: This applies errata 3888125 workaround to Cortex-X3 1012 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 1013 of the CPU. It is still open. 1014 1015- ``ERRATA_X3_4302966``: This applies errata 4302966 workaround to Cortex-X3 1016 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 1017 of the CPU. It is still open. 1018 1019For Cortex-X4, the following errata build flags are defined : 1020 1021- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 1022 CPU and affects system configurations that do not use an Arm interconnect IP. 1023 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 1024 The workaround for this erratum is not implemented in EL3, but the flag can 1025 be enabled/disabled at the platform level. The flag is used when the errata ABI 1026 feature is enabled and can assist the Kernel in the process of 1027 mitigation of the erratum. 1028 1029- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 1030 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 1031 r0p2. 1032 1033- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 1034 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 1035 in r0p2. 1036 1037- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 1038 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1039 1040- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 1041 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1042 1043- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 1044 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1045 1046- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 1047 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1048 1049- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 1050 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1051 1052- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 1053 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1054 1055- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 1056 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 1057 1058- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 1059 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 1060 It is still open. 1061 1062- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 1063 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 1064 It is still open. 1065 1066For Cortex-X925, the following errata build flags are defined : 1067 1068- ``ERRATA_X925_2921199``: This applies errata 2921199 workaround to Cortex-X925 1069 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1070 1071- ``ERRATA_X925_2922378``: This applies errata 2922378 workaround to Cortex-X925 1072 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1073 1074- ``ERRATA_X925_2933290``: This applies errata 2933290 workaround to Cortex-X925 1075 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1076 1077- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 1078 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1079 1080- ``ERRATA_X925_3324334``: This applies errata 3324334 workaround to Cortex-X925 1081 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1082 1083- ``ERRATA_X925_3692980``: This applies errata 3692980 workaround to Cortex-X925 1084 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1085 1086- ``ERRATA_X925_3730893``: This applies errata 3730893 workaround to Cortex-X925 1087 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1088 1089- ``ERRATA_X925_3865185``: This applies errata 3865185 workaround to Cortex-X925 1090 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1091 1092- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 1093 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 1094 1095For Cortex-A510, the following errata build flags are defined : 1096 1097- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 1098 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1099 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 1100 1101- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 1102 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1103 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1104 1105- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 1106 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 1107 r0p2, it is fixed in r0p3. 1108 1109- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 1110 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 1111 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 1112 workaround for those revisions. 1113 1114- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 1115 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 1116 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 1117 workaround for those revisions. 1118 1119- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 1120 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1121 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1122 1123- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 1124 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 1125 in r1p1. 1126 1127- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 1128 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1129 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 1130 ENABLE_MPMM=1. 1131 1132- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 1133 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1134 r0p3 and r1p0, it is fixed in r1p1. 1135 1136- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 1137 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1138 r0p3 and r1p0, it is fixed in r1p1. 1139 1140- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 1141 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1142 r0p3, r1p0 and r1p1. It is fixed in r1p2. 1143 1144- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 1145 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1146 r0p3, r1p0, r1p1, and is fixed in r1p2. 1147 1148- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1149 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1150 fixed in r1p2. 1151 1152- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1153 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1154 r0p3, r1p0, r1p1. It is fixed in r1p2. 1155 1156- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1157 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1158 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1159 1160- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1161 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1162 r1p0, r1p1, r1p2 and r1p3 and is still open. 1163 1164- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1165 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1166 r1p0, r1p1, r1p2 and r1p3 and is still open. 1167 1168- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1169 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1170 r1p0, r1p1, r1p2 and r1p3 and is still open. 1171 1172For Cortex-A520, the following errata build flags are defined : 1173 1174- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1175 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1176 CPU and is still open. 1177 1178- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1179 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1180 It is still open. 1181 1182- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1183 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1184 It is fixed in r0p2. 1185 1186For Cortex-A715, the following errata build flags are defined : 1187 1188- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1189 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1190 It is fixed in r1p1. 1191 1192- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1193 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1194 fixed in r1p1. 1195 1196- ``ERRATA_A715_2376701``: This applies errata 2376701 workaround to 1197 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1198 fixed in r1p1. 1199 1200- ``ERRATA_A715_2409570``: This applies errata 2409570 workaround to 1201 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1202 It is fixed in r1p1. This errata also applies to r0p0 but that revision has a 1203 different workaround, and since r0p0 is not used in production hardware it is 1204 not implemented. 1205 1206- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1207 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1208 when SPE(Statistical profiling extension)=True. The errata is fixed 1209 in r1p1. 1210 1211- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1212 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1213 It is fixed in r1p1. 1214 1215- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1216 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1217 workaround for revision r0p0. It is fixed in r1p1. 1218 1219- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1220 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1221 It is fixed in r1p1. 1222 1223- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1224 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1225 and r1p1. It is fixed in r1p2. 1226 1227- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1228 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1229 r1p1 and r1p2. It is fixed in r1p3. 1230 1231- ``ERRATA_A715_3456084``: This applies errata 3456084 workaround to 1232 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1233 r1p1, r1p2 and r1p3. It is still open. 1234 1235- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1236 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1237 r1p2 and r1p3. It is still open. 1238 1239- ``ERRATA_A715_3711916``: This applies errata 3711916 workaround to 1240 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1241 r1p1, r1p2 and r1p3. It is still open. 1242 1243For Cortex-A720, the following errata build flags are defined : 1244 1245- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1246 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1247 It is fixed in r0p2. 1248 1249- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1250 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1251 It is fixed in r0p2. 1252 1253- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1254 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1255 It is fixed in r0p2. 1256 1257- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1258 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1259 It is fixed in r0p2. 1260 1261- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1262 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1263 It is fixed in r0p2. 1264 1265- ``ERRATA_A720_3456091``: This applies errata 3456091 workaround to 1266 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1267 and r0p2. It is still open. 1268 1269- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1270 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1271 and r0p2. It is still open. 1272 1273- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1274 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1275 and r0p2. It is still open. 1276 1277For Cortex-A720_AE, the following errata build flags are defined : 1278 1279- ``ERRATA_A720_AE_3456103``: This applies errata 3456103 workaround to 1280 Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0 and r0p1. It 1281 is still open. 1282 1283- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1284 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1285 It is still open. 1286 1287For Cortex-A725, the following errata build flags are defined : 1288 1289- ``ERRATA_A725_2874943``: This applies errata 2874943 workaround to 1290 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 when 1291 FEAT_SPE is enabled. It is fixed in r0p1. 1292 1293- ``ERRATA_A725_2936490``: This applies errata 2936490 workaround to 1294 Cortex-A725 CPU. This needs to be enabled for revisions r0p0. 1295 It is fixed in r0p1. 1296 1297- ``ERRATA_A725_3456106``: This applies errata 3456106 workaround to 1298 Cortex-A725 CPU. This needs to be enabled for revisions r0p0, r0p1 1299 and r0p2. It is still open. 1300 1301- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1302 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1303 It is fixed in r0p2. 1304 1305- ``ERRATA_A725_3711914``: This applies errata 3711914 workaround to 1306 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1307 It is fixed in r0p2. 1308 1309For C1-Ultra, the following errata build flags are defined : 1310 1311- ``ERRATA_C1ULTRA_3324333``: This applies erratum 3324333 workaround to 1312 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is fixed 1313 in r1p0. 1314 1315- ``ERRATA_C1ULTRA_3502731``: This applies erratum 3502731 workaround to 1316 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1317 fixed in r1p0. 1318 1319- ``ERRATA_C1ULTRA_3658374``: This applies erratum 3658374 workaround to 1320 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1321 is still open. 1322 1323- ``ERRATA_C1ULTRA_3684152``: This applies erratum 3684152 workaround to 1324 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1325 fixed in r1p0. 1326 1327- ``ERRATA_C1ULTRA_3705939``: This applies erratum 3705939 workaround to 1328 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1329 is still open. 1330 1331- ``ERRATA_C1ULTRA_3815514``: This applies erratum 3815514 workaround to 1332 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1333 is still open. 1334 1335- ``ERRATA_C1ULTRA_3865171``: This applies erratum 3865171 workaround to 1336 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1337 is still open. 1338 1339- ``ERRATA_C1ULTRA_3926381``: This applies erratum 3926381 workaround to 1340 C1-Ultra CPU. This needs to be enabled for revision r1p0 and is still 1341 open. 1342 1343- ``ERRATA_C1ULTRA_4102704``: This applies erratum 4102704 workaround to 1344 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1345 is still open. 1346 1347For C1-Premium, the following errata build flags are defined : 1348 1349- ``ERRATA_C1PREMIUM_3324333``: This applies errata 3324333 workaround to 1350 C1-Premium CPU. This needs to be enabled for revision r0p0, and is 1351 fixed in r1p0. 1352 1353- ``ERRATA_C1PREMIUM_3502731``: This applies errata 3502731 workaround to 1354 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1355 in r1p0. 1356 1357- ``ERRATA_C1PREMIUM_3684152``: This applies errata 3684152 workaround to 1358 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1359 in r1p0. 1360 1361- ``ERRATA_C1PREMIUM_3705939``: This applies errata 3705939 workaround to 1362 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1363 is still open. 1364 1365- ``ERRATA_C1PREMIUM_3815514``: This applies errata 3815514 workaround to 1366 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1367 is still open. 1368 1369- ``ERRATA_C1PREMIUM_3865171``: This applies errata 3865171 workaround to 1370 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1371 is still open. 1372 1373- ``ERRATA_C1PREMIUM_3926381``: This applies errata 3926381 workaround to 1374 C1-Premium CPU. This needs to be enabled for revision r1p0 and is 1375 still open. 1376 1377- ``ERRATA_C1PREMIUM_4102704``: This applies errata 4102704 workaround to 1378 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1379 is still open. 1380 1381For C1-Pro, the following errata build flags are defined : 1382 1383- ``ERRATA_C1PRO_3619847``: This applies errata 3619847 workaround to C1-Pro 1384 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1385 1386- ``ERRATA_C1PRO_3338470``: This applies errata 3338470 workaround to C1-Pro 1387 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1388 1389- ``ERRATA_C1PRO_3362007``: This applies errata 3362007 workaround to C1-Pro 1390 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1391 1392- ``ERRATA_C1PRO_3686597``: This applies errata 3686597 workaround to C1-Pro 1393 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1394 is fixed in r1p1. 1395 1396- ``ERRATA_C1PRO_3694158``: This applies errata 3694158 workaround to C1-Pro 1397 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 and is 1398 fixed in r1p2. 1399 1400- ``ERRATA_C1PRO_3706576``: This applies errata 3706576 workaround to C1-Pro 1401 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1402 is fixed in r1p1. 1403 1404- ``ERRATA_C1PRO_3300099``: This applies errata 3300099 workaround to C1-Pro 1405 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1406 is fixed in r1p1. 1407 1408For C1-Nano, the following errata build flags are defined : 1409 1410- ``ERRATA_C1NANO_3392149``: This applies errata 3392149 workaround to 1411 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1412 in r0p1. 1413 1414- ``ERRATA_C1NANO_3419531``: This applies errata 3419531 workaround to 1415 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1416 in r0p1. 1417 1418- ``ERRATA_C1NANO_3437202``: This applies errata 3437202 workaround to 1419 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1420 in r0p1. 1421 1422- ``ERRATA_C1NANO_3516455``: This applies errata 3516455 workaround to 1423 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1424 in r0p1. 1425 1426- ``ERRATA_C1NANO_3616450``: This applies errata 3616450 workaround to 1427 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1428 in r0p1. 1429 1430- ``ERRATA_C1NANO_3630925``: This applies errata 3630925 workaround to 1431 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1432 in r0p1. 1433 1434- ``ERRATA_C1NANO_3754876``: This applies errata 3754876 workaround to 1435 C1-Nano CPU. This needs to be enabled for revisions r0p0 and r0p1, and 1436 is fixed in r0p2. 1437 1438DSU Errata Workarounds 1439---------------------- 1440 1441Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1442Shared Unit) errata. The DSU errata details can be found in the respective Arm 1443documentation: 1444 1445- `Arm DSU Software Developers Errata Notice`_. 1446 1447Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1448document. Thus, the build flags which enable/disable the errata workarounds 1449have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1450of DSU errata workarounds are similar to `CPU errata workarounds`_. 1451 1452For DSU errata, the following build flags are defined: 1453 1454- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1455 affected DSU configurations. This errata applies only for those DSUs that 1456 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1457 workaround results in increased DSU power consumption on idle. 1458 1459- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1460 affected DSU configurations. This errata applies only for those DSUs that 1461 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1462 r2p0 it is fixed). However, please note that this workaround results in 1463 increased DSU power consumption on idle. 1464 1465- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1466 affected DSU configurations. This errata applies for those DSUs with 1467 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1468 please note that this workaround results in increased DSU power consumption 1469 on idle. 1470 1471- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1472 affected DSU-120 configurations. This erratum applies to some r2p0 1473 implementations and is fixed in r2p1. The affected r2p0 implementations 1474 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1475 and making sure it's clear. 1476 1477CPU Specific optimizations 1478-------------------------- 1479 1480This section describes some of the optimizations allowed by the CPU micro 1481architecture that can be enabled by the platform as desired. 1482 1483- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1484 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1485 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1486 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1487 is a known safe deviation from the Cortex-A57 TRM defined power down 1488 sequence. Each Cortex-A57 based platform must make its own decision on 1489 whether to use the optimization. 1490 1491- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1492 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1493 in a way most programmers expect, and will most probably result in a 1494 significant speed degradation to any code that employs them. The Armv8-A 1495 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1496 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1497 flag enforces this behaviour. This needs to be enabled only for revisions 1498 <= r0p3 of the CPU and is enabled by default. 1499 1500- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1501 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1502 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1503 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1504 `Cortex-A57 Software Optimization Guide`_. 1505 1506- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1507 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1508 this bit only if their memory system meets the requirement that cache 1509 line fill requests from the Cortex-A57 processor are atomic. Each 1510 Cortex-A57 based platform must make its own decision on whether to use 1511 the optimization. This flag is disabled by default. 1512 1513- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1514 level cache(LLC) is present in the system, and that the DataSource field 1515 on the master CHI interface indicates when data is returned from the LLC. 1516 This is used to control how the LL_CACHE* PMU events count. 1517 Default value is 0 (Disabled). 1518 1519- ``NEOVERSE_Vx_EXTERNAL_LLC``: This flag has the same behaviour as 1520 ``NEOVERSE_Nx_EXTERNAL_LLC`` but for Neoverse-V2. This is disabled 1521 by default. Default value is 0 (Disabled). 1522 1523- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1524 on the Neoverse N2 core. This is used during performance analysis to get clean 1525 and repeatable measurements of the cache by preventing speculative data fetches 1526 from interfering with benchmark results. 1527 Default value is 0 (Disabled). 1528 1529GIC Errata Workarounds 1530---------------------- 1531- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1532 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1533 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1534 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1535 then this flag is enabled; otherwise, it is 0 (Disabled). 1536 1537-------------- 1538 1539*Copyright (c) 2014-2026, Arm Limited and Contributors. All rights reserved.* 1540 1541.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1542.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1543.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1544.. _CVE-2024-5660: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-5660 1545.. _CVE-2024-7881: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-7881 1546.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1547.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1548.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1549