1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 54 55The errata workarounds are implemented for a particular revision or a set of 56processor revisions. This is checked by the reset handler at runtime. Each 57errata workaround is identified by its ``ID`` as specified in the processor's 58errata notice document. The format of the define used to enable/disable the 59errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 60is for example ``A57`` for the ``Cortex_A57`` CPU. 61 62Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 63write errata workaround functions. 64 65All workarounds are disabled by default. The platform is responsible for 66enabling these workarounds according to its requirement by defining the 67errata workaround build flags in the platform specific makefile. In case 68these workarounds are enabled for the wrong CPU revision then the errata 69workaround is not applied. In the DEBUG build, this is indicated by 70printing a warning to the crash console. 71 72In the current implementation, a platform which has more than 1 variant 73with different revisions of a processor has no runtime mechanism available 74for it to specify which errata workarounds should be enabled or not. 75 76The value of the build flags is 0 by default, that is, disabled. A value of 1 77will enable it. 78 79For Cortex-A9, the following errata build flags are defined : 80 81- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 82 CPU. This needs to be enabled for all revisions of the CPU. 83 84For Cortex-A15, the following errata build flags are defined : 85 86- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 87 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 88 89- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92For Cortex-A17, the following errata build flags are defined : 93 94- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 95 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 96 97- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100For Cortex-A35, the following errata build flags are defined : 101 102- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 103 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 104 105For Cortex-A53, the following errata build flags are defined : 106 107- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 108 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 109 110- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 114 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 115 116- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 117 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 118 119- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 120 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 121 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 122 sections. 123 124- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 125 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 126 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 127 ``A53_DISABLE_NON_TEMPORAL_HINT``. 128 129- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 130 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 131 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 132 which are 4kB aligned. 133 134- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 135 CPUs. Though the erratum is present in every revision of the CPU, 136 this workaround is only applied to CPUs from r0p3 onwards, which feature 137 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 138 Earlier revisions of the CPU have other errata which require the same 139 workaround in software, so they should be covered anyway. 140 141- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 142 revisions of Cortex-A53 CPU. 143 144For Cortex-A55, the following errata build flags are defined : 145 146- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 157 158- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 163 164- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 165 revisions of Cortex-A55 CPU. 166 167For Cortex-A57, the following errata build flags are defined : 168 169- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 183 184- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 195 196- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 201 202- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 203 revisions of Cortex-A57 CPU. 204 205For Cortex-A65, the following errata build flags are defined : 206 207- ``ERRATA_A65_1179935``: This applies errata 1179935 workaround to Cortex-A65 208 CPU. This needs to be enabled only for revision r0p0 of the CPU, and is fixed 209 in r1p0. 210 211- ``ERRATA_A65_1227419``: This applies errata 1227419 workaround to Cortex-A65 212 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU and 213 is fixed in r1p1. 214 215- ``ERRATA_A65_1541130``: This applies errata 1541130 workaround to r0p0, r1p0, 216 r1p1, r1p2 revisions of the CPU and is still open. 217 218For Cortex-A72, the following errata build flags are defined : 219 220- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 221 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 222 223- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 224 revisions of Cortex-A72 CPU. 225 226For Cortex-A73, the following errata build flags are defined : 227 228- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 229 CPU. This needs to be enabled only for revision r0p0 of the CPU. 230 231- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 232 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 233 234For Cortex-A75, the following errata build flags are defined : 235 236- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 237 CPU. This needs to be enabled only for revision r0p0 of the CPU. 238 239- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 240 CPU. This needs to be enabled only for revision r0p0 of the CPU. 241 242For Cortex-A76, the following errata build flags are defined : 243 244- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 245 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 246 247- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 248 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 249 250- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 251 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 252 253- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 255 256- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 258 259- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 260 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 261 262- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 263 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 264 265- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 266 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 267 268- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 269 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 270 limitation of errata framework this errata is applied to all revisions 271 of Cortex-A76 CPU. 272 273- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 274 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 275 276- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 277 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 278 279- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 280 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 281 still open. 282 283For Cortex-A76AE, the following errata build flags are defined : 284 285- ``ERRATA_A76AE_1931427``: This applies errata 1931427 workaround to Cortex-A76AE 286 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 287 fixed in r1p1. 288 289- ``ERRATA_A76AE_1931435``: This applies errata 1931435 workaround to Cortex-A76AE 290 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 291 fixed in r1p1. 292 293- ``ERRATA_A76AE_1969401``: This applies errata 1969401 workaround to Cortex-A76AE 294 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 295 fixed in r1p1. 296 297- ``ERRATA_A76AE_2371140``: This applies errata 2371140 workaround to Cortex-A76AE 298 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 299 still open. 300 301- ``ERRATA_A76AE_2753838``: This applies errata 2753838 workaround to Cortex-A76AE 302 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 303 still open. 304 305For Cortex-A77, the following errata build flags are defined : 306 307- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 308 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 309 310- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 311 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 312 313- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 314 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 315 316- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 317 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 318 319- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 320 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 321 322 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 323 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 324 325 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 326 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 327 328For Cortex-A78, the following errata build flags are defined : 329 330- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 331 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 332 333- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 334 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 335 336- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 337 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 338 issue but there is no workaround for that revision. 339 340- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 341 CPU. This needs to be enabled for revisions r0p0 and r1p0. 342 343- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 344 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 345 346- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 347 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 348 is present in r0p0 but there is no workaround. It is still open. 349 350- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 351 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 352 it is still open. 353 354- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 355 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 356 it is still open. 357 358- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 359 CPU, this erratum affects system configurations that do not use an ARM 360 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 361 and r1p2 and it is still open. 362 363- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 364 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 365 it is still open. 366 367- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 368 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 369 it is still open. 370 371- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 372 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 373 it is still open. 374 375For Cortex-A78AE, the following errata build flags are defined : 376 377- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 378 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 379 This erratum is still open. 380 381- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 382 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 383 erratum is still open. 384 385- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 386 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 387 This erratum is still open. 388 389- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 390 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 391 erratum is still open. 392 393- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 394 Cortex-A78AE CPU. This erratum affects system configurations that do not use 395 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 396 r0p2. This erratum is still open. 397 398For Cortex-A78C, the following errata build flags are defined : 399 400- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 401 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 402 fixed in r0p1. 403 404- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 405 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 406 fixed in r0p1. 407 408- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 409 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 410 it is still open. 411 412- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 413 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 414 erratum is still open. 415 416- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 417 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 418 erratum is still open. 419 420- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 421 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 422 erratum is still open. 423 424- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 425 Cortex-A78C CPU, this erratum affects system configurations that do not use 426 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 427 and is still open. 428 429- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 430 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 431 This erratum is still open. 432 433- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 434 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 435 This erratum is still open. 436 437- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 438 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 439 This erratum is still open. 440 441For Cortex-X1 CPU, the following errata build flags are defined: 442 443- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 444 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 445 446- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 447 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 448 449- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 450 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 451 452For Neoverse N1, the following errata build flags are defined : 453 454- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 455 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 456 457- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 458 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 459 460- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 461 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 462 463- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 464 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 465 466- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 467 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 468 469- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 470 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 471 472- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 473 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 474 475- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 476 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 477 478- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 479 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 480 481- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 482 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 483 484- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 485 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 486 487- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 488 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 489 490- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 491 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 492 revisions r0p0, r1p0, and r2p0 there is no workaround. 493 494- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 495 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 496 still open. 497 498- ``ERRATA_N1_3324349``: This applies errata 3324349 workaround to Neoverse-N1 499 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 500 still open. 501 502For Neoverse V1, the following errata build flags are defined : 503 504- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 505 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 506 r1p0. 507 508- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 509 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 510 in r1p1. 511 512- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 513 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 514 in r1p1. 515 516- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 517 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 518 in r1p1. 519 520- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 521 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 522 523- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 524 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 525 CPU. 526 527- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 528 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 529 issue is present in r0p0 as well but there is no workaround for that 530 revision. It is still open. 531 532- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 533 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 534 CPU. It is still open. 535 536- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 537 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 538 issue is present in r0p0 as well but there is no workaround for that 539 revision. It is still open. 540 541- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 542 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 543 the CPU. 544 545- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 546 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 547 It has been fixed in r1p2. 548 549- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 550 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 551 It is still open. 552 553- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 554 CPU, this erratum affects system configurations that do not use an ARM 555 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 556 It has been fixed in r1p2. 557 558- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 559 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 560 CPU. It is still open. 561 562- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 563 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 564 CPU. It is still open. 565 566- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 567 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 568 CPU. It is still open. 569 570For Neoverse V2, the following errata build flags are defined : 571 572- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 573 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 574 r0p2. 575 576- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 577 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 578 r0p2. 579 580- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 581 CPU, this affects system configurations that do not use and ARM interconnect 582 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 583 in r0p2. 584 585- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 586 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 587 r0p2. 588 589- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 590 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 591 r0p2. 592 593- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 594 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 595 r0p2. 596 597- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 598 CPU, this affects all configurations. This needs to be enabled for revisions 599 r0p0 and r0p1. It has been fixed in r0p2. 600 601- ``ERRATA_V2_3442699``: This applies errata 3442699 workaround to Neoverse-V2 602 CPU. This needs to be enabled for revision r0p0 - r0p2 and is still open. 603 604- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 605 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 606 still open. 607 608- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 609 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 610 the CPU. It is fixed in r0p2. 611 612- ``ERRATA_V2_3888126``: This applies errata 3888126 workaround to Neoverse-V2 613 CPU. This needs to be enabled only for revisions r0p0, r0p1, r0p2 of 614 the CPU. It is still open. 615 616- ``ERRATA_V2_4302968``: This applies errata 4302968 workaround to Neoverse-V2 617 CPU. This needs to be enabled only for revisions r0p0, r0p1, r0p2 of 618 the CPU. It is still open. 619 620For Neoverse V3, the following errata build flags are defined : 621 622- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 623 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 624 625- ``ERRATA_V3_3312417``: This applies errata 3312417 workaround to Neoverse-V3 626 CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and is 627 fixed in r0p2. 628 629- ``ERRATA_V3_3696307``: This applies errata 3696307 workaround to Neoverse-V3 630 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 631 r0p2. 632 633- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 634 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 635 is still open. 636 637- ``ERRATA_V3_3734562``: This applies errata 3734562 workaround to Neoverse-V3 638 CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and 639 is fixed in r0p2. 640 641- ``ERRATA_V3_3782181``: This applies errata 3782181 workaround to Neoverse-V3 642 CPU. This needs to be enabled for revision r0p1 of the CPU and is fixed in 643 r0p2. 644 645- ``ERRATA_V3_3864536``: This applies errata 3864536 workaround to Neoverse-V3 646 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and 647 is still open. 648 649- ``ERRATA_V3_3878291``: This applies errata 3878291 workaround to Neoverse-V3 650 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and 651 is still open. 652 653For Cortex-A710, the following errata build flags are defined : 654 655- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 656 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 657 been fixed in r2p0. 658 659- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 660 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 661 It has been fixed in r2p0. 662 663- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 664 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 665 It has been fixed in r2p0. 666 667- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 668 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 669 It has been fixed in r2p0. 670 671- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 672 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 673 r2p0 of the CPU. It is still open. 674 675- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 676 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 677 r2p0 of the CPU. It is still open. 678 679- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 680 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 681 and is still open. 682 683- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 684 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 685 of the CPU and is still open. 686 687- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 688 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 689 is still open. 690 691- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 692 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 693 of the CPU and is fixed in r2p1. 694 695- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 696 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 697 of the CPU and is fixed in r2p1. 698 699- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 700 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 701 and is fixed in r2p1. 702 703- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 704 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 705 of the CPU and is fixed in r2p1. 706 707- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 708 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 709 r2p1 of the CPU and is still open. 710 711- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 712 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 713 of the CPU and is fixed in r2p1. 714 715- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 716 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 717 of the CPU and is fixed in r2p1. 718 719- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 720 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 721 of the CPU and is fixed in r2p1. 722 723- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 724 CPU, and applies to system configurations that do not use and ARM 725 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 726 is still open. 727 728- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 729 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 730 r2p1 of the CPU and is still open. 731 732- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 733 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 734 r2p1 of the CPU and is still open. 735 736- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 737 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 738 CPU and is still open. 739 740- ``ERRATA_A710_3324338``: This applies errata 3324338 workaround to 741 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 742 r2p1 of the CPU and is still open. 743 744- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 745 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 746 CPU and is still open. 747 748For Neoverse N2, the following errata build flags are defined : 749 750- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 751 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 752 753- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 754 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 755 756- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 757 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 758 759- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 760 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 761 762- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 763 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 764 765- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 766 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 767 768- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 769 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 770 771- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 772 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 773 774- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 775 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 776 777- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 778 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 779 780- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 781 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 782 r0p1. 783 784- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 785 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 786 r0p1. 787 788- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 789 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 790 it is fixed in r0p3. 791 792- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 793 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 794 795- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 796 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 797 r0p1. 798 799- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 800 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 801 in r0p3. 802 803- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 804 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 805 in r0p3. 806 807- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 808 CPU, this erratum affects system configurations that do not use and ARM 809 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 810 It is fixed in r0p3. 811 812- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 813 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 814 in r0p3. 815 816- ``ERRATA_N2_3324339``: This applies errata 3324339 workaround to Neoverse-N2 817 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 818 still open. 819 820- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 821 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 822 still open. 823 824For Neoverse N3, the following errata build flags are defined : 825 826- ``ERRATA_N3_3456111``: This applies errata 3456111 workaround to Neoverse-N3 827 CPU. This needs to be enabled for revisions r0p0 and r0p1 and is still open. 828 829- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 830 CPU. This needs to be enabled for revisions r0p0 and is still open. 831 832For Cortex-X2, the following errata build flags are defined : 833 834- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 835 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 836 837- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 838 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 839 is fixed in r2p0. 840 841- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 842 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 843 is fixed in r2p0. 844 845- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 846 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 847 is fixed in r2p0. 848 849- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 850 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 851 in r2p0. 852 853- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 854 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 855 CPU, it is fixed in r2p1. 856 857- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 858 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 859 CPU, it is fixed in r2p1. 860 861- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 862 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 863 CPU, it is fixed in r2p1. 864 865- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 866 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 867 in r2p1. 868 869- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 870 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 871 CPU, it is fixed in r2p1. 872 873- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 874 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 875 in r2p1. 876 877- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 878 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 879 CPU, it is fixed in r2p1. 880 881- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 882 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 883 CPU, it is fixed in r2p1. 884 885- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 886 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 887 CPU and is still open. 888 889- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 890 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 891 CPU, it is fixed in r2p1. 892 893- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 894 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 895 CPU, it is fixed in r2p1. 896 897- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 898 CPU and affects system configurations that do not use an Arm interconnect IP. 899 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 900 still open. 901 902- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 903 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 904 CPU and is still open. 905 906- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 907 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 908 CPU and is still open. 909 910- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 911 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 912 CPU and is still open. 913 914- ``ERRATA_X2_3324338``: This applies errata 3324338 workaround to Cortex-X2 915 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 916 CPU and is still open. 917 918- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 919 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 920 CPU and is still open. 921 922- ``ERRATA_X2_3888122``: This applies errata 3888122 workaround to Cortex-X2 923 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 924 CPU and is still open. 925 926- ``ERRATA_X2_4302969``: This applies errata 4302969 workaround to Cortex-X2 927 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 928 CPU and is still open. 929 930For Cortex-X3, the following errata build flags are defined : 931 932- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 933 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 934 is fixed in r1p1. 935 936- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 937 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 938 fixed in r1p2. 939 940- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 941 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 942 of the CPU, it is fixed in r1p1. 943 944- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 945 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 946 of the CPU, it is fixed in r1p1. 947 948- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 949 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 950 CPU, it is fixed in r1p2. 951 952- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 953 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 954 It is fixed in r1p1. 955 956- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 957 CPU and affects system configurations that do not use an ARM interconnect 958 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 959 in r1p2. 960 961- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 962 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 963 r1p1. It is fixed in r1p2. 964 965- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 966 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 967 fixed in r1p2. 968 969- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 970 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 971 CPU. It is fixed in r1p2. 972 973- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 974 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 975 of the CPU. It is still open. 976 977- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 978 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 979 of the CPU. It is still open. 980 981- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 982 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 983 of the CPU and it is still open. 984 985- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 986 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 987 the CPU. It is fixed in r1p2. 988 989- ``ERRATA_X3_3888125``: This applies errata 3888125 workaround to Cortex-X3 990 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 991 of the CPU. It is still open. 992 993- ``ERRATA_X3_4302966``: This applies errata 4302966 workaround to Cortex-X3 994 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 995 of the CPU. It is still open. 996 997For Cortex-X4, the following errata build flags are defined : 998 999- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 1000 CPU and affects system configurations that do not use an Arm interconnect IP. 1001 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 1002 The workaround for this erratum is not implemented in EL3, but the flag can 1003 be enabled/disabled at the platform level. The flag is used when the errata ABI 1004 feature is enabled and can assist the Kernel in the process of 1005 mitigation of the erratum. 1006 1007- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 1008 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 1009 r0p2. 1010 1011- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 1012 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 1013 in r0p2. 1014 1015- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 1016 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1017 1018- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 1019 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1020 1021- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 1022 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1023 1024- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 1025 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1026 1027- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 1028 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1029 1030- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 1031 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1032 1033- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 1034 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 1035 1036- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 1037 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 1038 It is still open. 1039 1040- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 1041 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 1042 It is still open. 1043 1044For Cortex-X925, the following errata build flags are defined : 1045 1046- ``ERRATA_X925_2921199``: This applies errata 2921199 workaround to Cortex-X925 1047 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1048 1049- ``ERRATA_X925_2922378``: This applies errata 2922378 workaround to Cortex-X925 1050 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1051 1052- ``ERRATA_X925_2933290``: This applies errata 2933290 workaround to Cortex-X925 1053 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1054 1055- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 1056 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1057 1058- ``ERRATA_X925_3324334``: This applies errata 3324334 workaround to Cortex-X925 1059 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1060 1061- ``ERRATA_X925_3692980``: This applies errata 3692980 workaround to Cortex-X925 1062 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1063 1064- ``ERRATA_X925_3730893``: This applies errata 3730893 workaround to Cortex-X925 1065 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1066 1067- ``ERRATA_X925_3865185``: This applies errata 3865185 workaround to Cortex-X925 1068 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1069 1070- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 1071 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 1072 1073For Cortex-A510, the following errata build flags are defined : 1074 1075- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 1076 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1077 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 1078 1079- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 1080 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1081 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1082 1083- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 1084 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 1085 r0p2, it is fixed in r0p3. 1086 1087- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 1088 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 1089 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 1090 workaround for those revisions. 1091 1092- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 1093 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 1094 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 1095 workaround for those revisions. 1096 1097- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 1098 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1099 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1100 1101- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 1102 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 1103 in r1p1. 1104 1105- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 1106 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1107 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 1108 ENABLE_MPMM=1. 1109 1110- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 1111 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1112 r0p3 and r1p0, it is fixed in r1p1. 1113 1114- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 1115 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1116 r0p3 and r1p0, it is fixed in r1p1. 1117 1118- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 1119 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1120 r0p3, r1p0 and r1p1. It is fixed in r1p2. 1121 1122- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 1123 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1124 r0p3, r1p0, r1p1, and is fixed in r1p2. 1125 1126- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1127 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1128 fixed in r1p2. 1129 1130- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1131 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1132 r0p3, r1p0, r1p1. It is fixed in r1p2. 1133 1134- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1135 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1136 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1137 1138- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1139 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1140 r1p0, r1p1, r1p2 and r1p3 and is still open. 1141 1142- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1143 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1144 r1p0, r1p1, r1p2 and r1p3 and is still open. 1145 1146- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1147 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1148 r1p0, r1p1, r1p2 and r1p3 and is still open. 1149 1150For Cortex-A520, the following errata build flags are defined : 1151 1152- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1153 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1154 CPU and is still open. 1155 1156- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1157 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1158 It is still open. 1159 1160- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1161 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1162 It is fixed in r0p2. 1163 1164For Cortex-A715, the following errata build flags are defined : 1165 1166- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1167 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1168 It is fixed in r1p1. 1169 1170- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1171 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1172 fixed in r1p1. 1173 1174- ``ERRATA_A715_2376701``: This applies errata 2376701 workaround to 1175 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1176 fixed in r1p1. 1177 1178- ``ERRATA_A715_2409570``: This applies errata 2409570 workaround to 1179 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1180 It is fixed in r1p1. This errata also applies to r0p0 but that revision has a 1181 different workaround, and since r0p0 is not used in production hardware it is 1182 not implemented. 1183 1184- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1185 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1186 when SPE(Statistical profiling extension)=True. The errata is fixed 1187 in r1p1. 1188 1189- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1190 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1191 It is fixed in r1p1. 1192 1193- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1194 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1195 workaround for revision r0p0. It is fixed in r1p1. 1196 1197- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1198 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1199 It is fixed in r1p1. 1200 1201- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1202 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1203 and r1p1. It is fixed in r1p2. 1204 1205- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1206 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1207 r1p1 and r1p2. It is fixed in r1p3. 1208 1209- ``ERRATA_A715_3456084``: This applies errata 3456084 workaround to 1210 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1211 r1p1, r1p2 and r1p3. It is still open. 1212 1213- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1214 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1215 r1p2 and r1p3. It is still open. 1216 1217- ``ERRATA_A715_3711916``: This applies errata 3711916 workaround to 1218 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1219 r1p1, r1p2 and r1p3. It is still open. 1220 1221For Cortex-A720, the following errata build flags are defined : 1222 1223- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1224 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1225 It is fixed in r0p2. 1226 1227- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1228 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1229 It is fixed in r0p2. 1230 1231- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1232 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1233 It is fixed in r0p2. 1234 1235- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1236 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1237 It is fixed in r0p2. 1238 1239- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1240 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1241 It is fixed in r0p2. 1242 1243- ``ERRATA_A720_3456091``: This applies errata 3456091 workaround to 1244 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1245 and r0p2. It is still open. 1246 1247- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1248 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1249 and r0p2. It is still open. 1250 1251- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1252 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1253 and r0p2. It is still open. 1254 1255For Cortex-A720_AE, the following errata build flags are defined : 1256 1257- ``ERRATA_A720_AE_3456103``: This applies errata 3456103 workaround to 1258 Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0 and r0p1. It 1259 is still open. 1260 1261- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1262 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1263 It is still open. 1264 1265For Cortex-A725, the following errata build flags are defined : 1266 1267- ``ERRATA_A725_2874943``: This applies errata 2874943 workaround to 1268 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 when 1269 FEAT_SPE is enabled. It is fixed in r0p1. 1270 1271- ``ERRATA_A725_2936490``: This applies errata 2936490 workaround to 1272 Cortex-A725 CPU. This needs to be enabled for revisions r0p0. 1273 It is fixed in r0p1. 1274 1275- ``ERRATA_A725_3456106``: This applies errata 3456106 workaround to 1276 Cortex-A725 CPU. This needs to be enabled for revisions r0p0, r0p1 1277 and r0p2. It is still open. 1278 1279- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1280 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1281 It is fixed in r0p2. 1282 1283- ``ERRATA_A725_3711914``: This applies errata 3711914 workaround to 1284 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1285 It is fixed in r0p2. 1286 1287For C1-Ultra, the following errata build flags are defined : 1288 1289- ``ERRATA_C1ULTRA_3324333``: This applies erratum 3324333 workaround to 1290 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is fixed 1291 in r1p0. 1292 1293- ``ERRATA_C1ULTRA_3502731``: This applies erratum 3502731 workaround to 1294 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1295 fixed in r1p0. 1296 1297- ``ERRATA_C1ULTRA_3651221``: This applies erratum 3651221 workaround to 1298 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1299 fixed in r1p0. 1300 1301- ``ERRATA_C1ULTRA_3658374``: This applies erratum 3658374 workaround to 1302 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1303 is still open. 1304 1305- ``ERRATA_C1ULTRA_3684152``: This applies erratum 3684152 workaround to 1306 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1307 fixed in r1p0. 1308 1309- ``ERRATA_C1ULTRA_3705939``: This applies erratum 3705939 workaround to 1310 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1311 is still open. 1312 1313- ``ERRATA_C1ULTRA_3815514``: This applies erratum 3815514 workaround to 1314 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1315 is still open. 1316 1317- ``ERRATA_C1ULTRA_3865171``: This applies erratum 3865171 workaround to 1318 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1319 is still open. 1320 1321- ``ERRATA_C1ULTRA_3926381``: This applies erratum 3926381 workaround to 1322 C1-Ultra CPU. This needs to be enabled for revision r1p0 and is still 1323 open. 1324 1325- ``ERRATA_C1ULTRA_4102704``: This applies erratum 4102704 workaround to 1326 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1327 is still open. 1328 1329For C1-Premium, the following errata build flags are defined : 1330 1331- ``ERRATA_C1PREMIUM_3324333``: This applies errata 3324333 workaround to 1332 C1-Premium CPU. This needs to be enabled for revision r0p0, and is 1333 fixed in r1p0. 1334 1335- ``ERRATA_C1PREMIUM_3502731``: This applies errata 3502731 workaround to 1336 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1337 in r1p0. 1338 1339- ``ERRATA_C1PREMIUM_3651221``: This applies errata 3651221 workaround to 1340 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1341 in r1p0. 1342 1343- ``ERRATA_C1PREMIUM_3684152``: This applies errata 3684152 workaround to 1344 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1345 in r1p0. 1346 1347- ``ERRATA_C1PREMIUM_3705939``: This applies errata 3705939 workaround to 1348 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1349 is still open. 1350 1351- ``ERRATA_C1PREMIUM_3815514``: This applies errata 3815514 workaround to 1352 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1353 is still open. 1354 1355- ``ERRATA_C1PREMIUM_3865171``: This applies errata 3865171 workaround to 1356 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1357 is still open. 1358 1359- ``ERRATA_C1PREMIUM_3926381``: This applies errata 3926381 workaround to 1360 C1-Premium CPU. This needs to be enabled for revision r1p0 and is 1361 still open. 1362 1363- ``ERRATA_C1PREMIUM_4102704``: This applies errata 4102704 workaround to 1364 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1365 is still open. 1366 1367For C1-Pro, the following errata build flags are defined : 1368 1369- ``ERRATA_C1PRO_3619847``: This applies errata 3619847 workaround to C1-Pro 1370 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1371 1372- ``ERRATA_C1PRO_3338470``: This applies errata 3338470 workaround to C1-Pro 1373 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1374 1375- ``ERRATA_C1PRO_3362007``: This applies errata 3362007 workaround to C1-Pro 1376 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1377 1378- ``ERRATA_C1PRO_3684268``: This applies errata 3684268 workaround to C1-Pro 1379 CPU. This needs to be enabled for revisions r0p0, r1p0 and is fixed in 1380 r1p1. 1381 1382- ``ERRATA_C1PRO_3686597``: This applies errata 3686597 workaround to C1-Pro 1383 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1384 is fixed in r1p1. 1385 1386- ``ERRATA_C1PRO_3694158``: This applies errata 3694158 workaround to C1-Pro 1387 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 and is 1388 fixed in r1p2. 1389 1390- ``ERRATA_C1PRO_3706576``: This applies errata 3706576 workaround to C1-Pro 1391 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1392 is fixed in r1p1. 1393 1394- ``ERRATA_C1PRO_3300099``: This applies errata 3300099 workaround to C1-Pro 1395 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1396 is fixed in r1p1. 1397 1398For C1-Nano, the following errata build flags are defined : 1399 1400- ``ERRATA_C1NANO_3392149``: This applies errata 3392149 workaround to 1401 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1402 in r0p1. 1403 1404- ``ERRATA_C1NANO_3419531``: This applies errata 3419531 workaround to 1405 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1406 in r0p1. 1407 1408- ``ERRATA_C1NANO_3437202``: This applies errata 3437202 workaround to 1409 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1410 in r0p1. 1411 1412- ``ERRATA_C1NANO_3516455``: This applies errata 3516455 workaround to 1413 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1414 in r0p1. 1415 1416- ``ERRATA_C1NANO_3616450``: This applies errata 3616450 workaround to 1417 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1418 in r0p1. 1419 1420- ``ERRATA_C1NANO_3630925``: This applies errata 3630925 workaround to 1421 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1422 in r0p1. 1423 1424- ``ERRATA_C1NANO_3754876``: This applies errata 3754876 workaround to 1425 C1-Nano CPU. This needs to be enabled for revisions r0p0 and r0p1, and 1426 is fixed in r0p2. 1427 1428DSU Errata Workarounds 1429---------------------- 1430 1431Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1432Shared Unit) errata. The DSU errata details can be found in the respective Arm 1433documentation: 1434 1435- `Arm DSU Software Developers Errata Notice`_. 1436 1437Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1438document. Thus, the build flags which enable/disable the errata workarounds 1439have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1440of DSU errata workarounds are similar to `CPU errata workarounds`_. 1441 1442For DSU errata, the following build flags are defined: 1443 1444- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1445 affected DSU configurations. This errata applies only for those DSUs that 1446 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1447 workaround results in increased DSU power consumption on idle. 1448 1449- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1450 affected DSU configurations. This errata applies only for those DSUs that 1451 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1452 r2p0 it is fixed). However, please note that this workaround results in 1453 increased DSU power consumption on idle. 1454 1455- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1456 affected DSU configurations. This errata applies for those DSUs with 1457 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1458 please note that this workaround results in increased DSU power consumption 1459 on idle. 1460 1461- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1462 affected DSU-120 configurations. This erratum applies to some r2p0 1463 implementations and is fixed in r2p1. The affected r2p0 implementations 1464 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1465 and making sure it's clear. 1466 1467CPU Specific optimizations 1468-------------------------- 1469 1470This section describes some of the optimizations allowed by the CPU micro 1471architecture that can be enabled by the platform as desired. 1472 1473- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1474 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1475 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1476 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1477 is a known safe deviation from the Cortex-A57 TRM defined power down 1478 sequence. Each Cortex-A57 based platform must make its own decision on 1479 whether to use the optimization. 1480 1481- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1482 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1483 in a way most programmers expect, and will most probably result in a 1484 significant speed degradation to any code that employs them. The Armv8-A 1485 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1486 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1487 flag enforces this behaviour. This needs to be enabled only for revisions 1488 <= r0p3 of the CPU and is enabled by default. 1489 1490- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1491 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1492 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1493 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1494 `Cortex-A57 Software Optimization Guide`_. 1495 1496- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1497 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1498 this bit only if their memory system meets the requirement that cache 1499 line fill requests from the Cortex-A57 processor are atomic. Each 1500 Cortex-A57 based platform must make its own decision on whether to use 1501 the optimization. This flag is disabled by default. 1502 1503- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1504 level cache(LLC) is present in the system, and that the DataSource field 1505 on the master CHI interface indicates when data is returned from the LLC. 1506 This is used to control how the LL_CACHE* PMU events count. 1507 Default value is 0 (Disabled). 1508 1509- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1510 on the Neoverse N2 core. This is used during performance analysis to get clean 1511 and repeatable measurements of the cache by preventing speculative data fetches 1512 from interfering with benchmark results. 1513 Default value is 0 (Disabled). 1514 1515GIC Errata Workarounds 1516---------------------- 1517- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1518 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1519 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1520 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1521 then this flag is enabled; otherwise, it is 0 (Disabled). 1522 1523-------------- 1524 1525*Copyright (c) 2014-2026, Arm Limited and Contributors. All rights reserved.* 1526 1527.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1528.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1529.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1530.. _CVE-2024-5660: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-5660 1531.. _CVE-2024-7881: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-7881 1532.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1533.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1534.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1535