1/* 2 * Copyright (c) 2020-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <dsu_macros.S> 11#include <neoverse_n2.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_neoverse_n2_3701773 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30cpu_reset_prologue neoverse_n2 31 32workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 33 /* Apply instruction patching sequence */ 34 ldr x0,=0x6 35 msr S3_6_c15_c8_0,x0 36 ldr x0,=0xF3A08002 37 msr S3_6_c15_c8_2,x0 38 ldr x0,=0xFFF0F7FE 39 msr S3_6_c15_c8_3,x0 40 ldr x0,=0x40000001003ff 41 msr S3_6_c15_c8_1,x0 42 ldr x0,=0x7 43 msr S3_6_c15_c8_0,x0 44 ldr x0,=0xBF200000 45 msr S3_6_c15_c8_2,x0 46 ldr x0,=0xFFEF0000 47 msr S3_6_c15_c8_3,x0 48 ldr x0,=0x40000001003f3 49 msr S3_6_c15_c8_1,x0 50workaround_reset_end neoverse_n2, ERRATUM(2002655) 51 52check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 53 54workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 55 /* Stash ERRSELR_EL1 in x2 */ 56 mrs x2, ERRSELR_EL1 57 58 /* Select error record 0 and clear ED bit */ 59 msr ERRSELR_EL1, xzr 60 mrs x1, ERXCTLR_EL1 61 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 62 msr ERXCTLR_EL1, x1 63 64 /* Restore ERRSELR_EL1 from x2 */ 65 msr ERRSELR_EL1, x2 66workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 67 68check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 69 70workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 71 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 72workaround_reset_end neoverse_n2, ERRATUM(2025414) 73 74check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 75 76workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 77 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 78workaround_reset_end neoverse_n2, ERRATUM(2067956) 79 80check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 81 82workaround_runtime_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 83 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, BIT(29) 84workaround_runtime_end neoverse_n2, ERRATUM(2138953) 85 86check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 87 88workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 89 /* Apply instruction patching sequence */ 90 ldr x0,=0x3 91 msr S3_6_c15_c8_0,x0 92 ldr x0,=0xF3A08002 93 msr S3_6_c15_c8_2,x0 94 ldr x0,=0xFFF0F7FE 95 msr S3_6_c15_c8_3,x0 96 ldr x0,=0x10002001003FF 97 msr S3_6_c15_c8_1,x0 98 ldr x0,=0x4 99 msr S3_6_c15_c8_0,x0 100 ldr x0,=0xBF200000 101 msr S3_6_c15_c8_2,x0 102 ldr x0,=0xFFEF0000 103 msr S3_6_c15_c8_3,x0 104 ldr x0,=0x10002001003F3 105 msr S3_6_c15_c8_1,x0 106workaround_reset_end neoverse_n2, ERRATUM(2138956) 107 108check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 109 110workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 111 /* Apply instruction patching sequence */ 112 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 113workaround_reset_end neoverse_n2, ERRATUM(2138958) 114 115check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 116 117workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 118 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 119workaround_reset_end neoverse_n2, ERRATUM(2189731) 120 121check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 122 123workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 124 /* Apply instruction patching sequence */ 125 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 126 ldr x0, =0x2 127 msr S3_6_c15_c8_0, x0 128 ldr x0, =0x10F600E000 129 msr S3_6_c15_c8_2, x0 130 ldr x0, =0x10FF80E000 131 msr S3_6_c15_c8_3, x0 132 ldr x0, =0x80000000003FF 133 msr S3_6_c15_c8_1, x0 134workaround_reset_end neoverse_n2, ERRATUM(2242400) 135 136check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 137 138workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 139 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 140workaround_reset_end neoverse_n2, ERRATUM(2242415) 141 142check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 143 144workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 145 /* Apply instruction patching sequence */ 146 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 147workaround_reset_end neoverse_n2, ERRATUM(2280757) 148 149check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 150 151workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 152 errata_dsu_2313941_wa_impl 153workaround_reset_end neoverse_n2, ERRATUM(2313941) 154 155check_erratum_custom_start neoverse_n2, ERRATUM(2313941) 156 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 157 check_errata_dsu_2313941_impl 158 2: 159 ret 160check_erratum_custom_end neoverse_n2, ERRATUM(2313941) 161 162.global erratum_neoverse_n2_2326639_wa 163workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 164 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 165 * the workaround. Second call clears it to undo it. */ 166 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 167workaround_runtime_end neoverse_n2, ERRATUM(2326639) 168 169check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 170 171workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 172 /* Set bit 61 in CPUACTLR5_EL1 */ 173 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 174workaround_reset_end neoverse_n2, ERRATUM(2340933) 175 176check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 177 178workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 179 /* Set TXREQ to STATIC and full L2 TQ size */ 180 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 181 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 182 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 183 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 184workaround_reset_end neoverse_n2, ERRATUM(2346952) 185 186check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 187 188workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 189 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 190 * ST to behave like PLD/PFRM LD and not cause 191 * invalidations to other PE caches. 192 */ 193 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 194workaround_reset_end neoverse_n2, ERRATUM(2376738) 195 196check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 197 198workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 199 /*Set bit 40 in ACTLR2_EL1 */ 200 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 201workaround_reset_end neoverse_n2, ERRATUM(2388450) 202 203check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 204 205workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 206 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 207 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 208 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 209workaround_reset_end neoverse_n2, ERRATUM(2743014) 210 211check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 212 213workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 214 /* dsb before isb of power down sequence */ 215 dsb sy 216workaround_runtime_end neoverse_n2, ERRATUM(2743089) 217 218check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 219 220workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 221 /* Set bit 47 in ACTLR3_EL1 */ 222 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 223workaround_reset_end neoverse_n2, ERRATUM(2779511) 224 225check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 226 227workaround_runtime_start neoverse_n2, ERRATUM(3324339), ERRATA_N2_3324339 228 speculation_barrier 229workaround_runtime_end neoverse_n2, ERRATUM(3324339) 230 231check_erratum_ls neoverse_n2, ERRATUM(3324339), CPU_REV(0, 3) 232 233add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773 234 235check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 236 237workaround_reset_start neoverse_n2, ERRATUM(3888123), ERRATA_N2_3888123 238 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, BIT(22) 239workaround_reset_end neoverse_n2, ERRATUM(3888123) 240 241check_erratum_ls neoverse_n2, ERRATUM(3888123), CPU_REV(0, 3) 242 243workaround_reset_start neoverse_n2, ERRATUM(4302970), ERRATA_N2_4302970 244 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(50) 245workaround_reset_end neoverse_n2, ERRATUM(4302970) 246 247check_erratum_ls neoverse_n2, ERRATUM(4302970), CPU_REV(0, 3) 248 249workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 250#if IMAGE_BL31 251 /* 252 * The Neoverse-N2 generic vectors are overridden to apply errata 253 * mitigation on exception entry from lower ELs. 254 */ 255 override_vector_table wa_cve_vbar_neoverse_n2 256#endif /* IMAGE_BL31 */ 257workaround_reset_end neoverse_n2, CVE(2022,23960) 258 259check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 260 261/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 262workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 263 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 264workaround_reset_end neoverse_n2, CVE(2024, 5660) 265 266check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 267 268 /* ------------------------------------------- 269 * The CPU Ops reset function for Neoverse N2. 270 * ------------------------------------------- 271 */ 272cpu_reset_func_start neoverse_n2 273 274 /* Check if the PE implements SSBS */ 275 mrs x0, id_aa64pfr1_el1 276 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 277 b.eq 1f 278 279 /* Disable speculative loads */ 280 msr SSBS, xzr 281 apply_erratum neoverse_n2, ERRATUM(3324339), ERRATA_N2_3324339 282 2831: 284 /* Force all cacheable atomic instructions to be near */ 285 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 286 287#if ENABLE_FEAT_AMU 288 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 289 sysreg_bit_clear cptr_el3, TAM_BIT 290 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 291 sysreg_bit_clear cptr_el2, TAM_BIT 292 /* No need to enable the counters as this would be done at el3 exit */ 293#endif 294 295#if NEOVERSE_Nx_EXTERNAL_LLC 296 /* Some systems may have External LLC, core needs to be made aware */ 297 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 298#endif 299#if NEOVERSE_N2_PREFETCHER_DISABLE 300 /* Disable region prefetcher for L2 cache perf measurement */ 301 apply_erratum neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 302 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFDIS_BIT 303#endif 304cpu_reset_func_end neoverse_n2 305 306func neoverse_n2_core_pwr_dwn 307 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 308 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 309 310 /* --------------------------------------------------- 311 * Enable CPU power down bit in power control register 312 * No need to do cache maintenance here. 313 * --------------------------------------------------- 314 */ 315 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 316 317 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 318 319 isb 320 ret 321endfunc neoverse_n2_core_pwr_dwn 322 323 /* --------------------------------------------- 324 * This function provides Neoverse N2 specific 325 * register information for crash reporting. 326 * It needs to return with x6 pointing to 327 * a list of register names in ASCII and 328 * x8 - x15 having values of registers to be 329 * reported. 330 * --------------------------------------------- 331 */ 332.section .rodata.neoverse_n2_regs, "aS" 333neoverse_n2_regs: /* The ASCII list of register names to be reported */ 334 .asciz "cpupwrctlr_el1", "" 335 336func neoverse_n2_cpu_reg_dump 337 adr x6, neoverse_n2_regs 338 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 339 ret 340endfunc neoverse_n2_cpu_reg_dump 341 342declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 343 neoverse_n2_reset_func, \ 344 neoverse_n2_core_pwr_dwn 345