1/* 2 * Copyright (c) 2023-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_ultra.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12#include <wa_cve_2025_0647_cpprctx.h> 13 14#include <plat_macros.S> 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Arm C1-Ultra must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Arm C1-Ultra supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26#if ERRATA_SME_POWER_DOWN == 0 27#error "Arm C1-Ultra needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 28#endif 29 30cpu_reset_prologue c1_ultra 31 32workaround_runtime_start c1_ultra, ERRATUM(3324333), ERRATA_C1ULTRA_3324333 33 speculation_barrier 34workaround_runtime_end c1_ultra, ERRATUM(3324333) 35 36check_erratum_ls c1_ultra, ERRATUM(3324333), CPU_REV(0, 0) 37 38workaround_reset_start c1_ultra, ERRATUM(3502731), ERRATA_C1ULTRA_3502731 39 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 40workaround_reset_end c1_ultra, ERRATUM(3502731) 41 42check_erratum_ls c1_ultra, ERRATUM(3502731), CPU_REV(0, 0) 43 44.global check_erratum_c1_ultra_3658374 45add_erratum_entry c1_ultra, ERRATUM(3658374), ERRATA_C1ULTRA_3658374 46check_erratum_ls c1_ultra, ERRATUM(3658374), CPU_REV(1, 0) 47 48workaround_reset_start c1_ultra, ERRATUM(3684152), ERRATA_C1ULTRA_3684152 49 sysreg_bitfield_insert C1_ULTRA_IMP_CPUACTLR_EL1, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_BIT, \ 50 C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_WIDTH 51workaround_reset_end c1_ultra, ERRATUM(3684152) 52 53check_erratum_ls c1_ultra, ERRATUM(3684152), CPU_REV(0, 0) 54 55workaround_reset_start c1_ultra, ERRATUM(3705939), ERRATA_C1ULTRA_3705939 56 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR_EL1, BIT(48) 57workaround_reset_end c1_ultra, ERRATUM(3705939) 58 59check_erratum_ls c1_ultra, ERRATUM(3705939), CPU_REV(1, 0) 60 61workaround_reset_start c1_ultra, ERRATUM(3815514), ERRATA_C1ULTRA_3815514 62 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR5_EL1, BIT(13) 63workaround_reset_end c1_ultra, ERRATUM(3815514) 64 65check_erratum_ls c1_ultra, ERRATUM(3815514), CPU_REV(1, 0) 66 67workaround_reset_start c1_ultra, ERRATUM(3865171), ERRATA_C1ULTRA_3865171 68 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR2_EL1, BIT(22) 69workaround_reset_end c1_ultra, ERRATUM(3865171) 70 71check_erratum_ls c1_ultra, ERRATUM(3865171), CPU_REV(1, 0) 72 73workaround_reset_start c1_ultra, ERRATUM(3926381), ERRATA_C1ULTRA_3926381 74 /* Convert WFx to NOP */ 75 ldr x0,=0x0 76 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0 77 ldr x0,=0xD503205f 78 msr C1_ULTRA_IMP_CPUPOR_EL3, x0 79 ldr x0,=0xFFFFFFDF 80 msr C1_ULTRA_IMP_CPUPMR_EL3, x0 81 ldr x0,=0x1000002043ff 82 msr C1_ULTRA_IMP_CPUPCR_EL3, x0 83 /* Convert WFxT to NOP */ 84 ldr x0,=0x1 85 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0 86 ldr x0,=0xD5031000 87 msr C1_ULTRA_IMP_CPUPOR_EL3, x0 88 ldr x0,=0xFFFFFFC0 89 msr C1_ULTRA_IMP_CPUPMR_EL3, x0 90 ldr x0,=0x1000002043ff 91 msr C1_ULTRA_IMP_CPUPCR_EL3, x0 92 isb 93workaround_reset_end c1_ultra, ERRATUM(3926381) 94 95check_erratum_range c1_ultra, ERRATUM(3926381), CPU_REV(1, 0), CPU_REV(1, 0) 96 97workaround_reset_start c1_ultra, ERRATUM(4102704), ERRATA_C1ULTRA_4102704 98 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 99workaround_reset_end c1_ultra, ERRATUM(4102704) 100 101check_erratum_ls c1_ultra, ERRATUM(4102704), CPU_REV(1, 0) 102 103 /* ------------------------------------------------------------- 104 * CVE-2024-7881 is mitigated for C1-Ultra using erratum 3651221 105 * workaround by disabling the affected prefetcher setting 106 * CPUACTLR6_EL1[41]. 107 * ------------------------------------------------------------- 108 */ 109workaround_reset_start c1_ultra, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 110 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 111workaround_reset_end c1_ultra, CVE(2024, 7881) 112 113check_erratum_ls c1_ultra, CVE(2024, 7881), CPU_REV(0, 0) 114 115 /* 116 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 117 * Enables mitigation for CVE-2025-0647. 118 */ 119workaround_reset_start c1_ultra, CVE(2025, 647), WORKAROUND_CVE_2025_0647 120 mov x0, #WA_PATCH_SLOT(3) 121 bl wa_cve_2025_0647_instruction_patch 122workaround_reset_end c1_ultra, CVE(2025, 647) 123 124check_erratum_chosen c1_ultra, CVE(2025, 647), WORKAROUND_CVE_2025_0647 125 126#if WORKAROUND_CVE_2025_0647 127func c1_ultra_impl_defined_el3_handler 128 mov x0, #WA_LS_RCG_EN 129 130 /* See if this call came from trap handler. */ 131 cmp x1, #EC_IMP_DEF_EL3 132 bne wa_cve_2025_0647_do_cpp_wa 133 orr x0, x0, #WA_IS_TRAP_HANDLER 134 b wa_cve_2025_0647_do_cpp_wa 135endfunc c1_ultra_impl_defined_el3_handler 136#endif 137 138cpu_reset_func_start c1_ultra 139 /* ---------------------------------------------------- 140 * Disable speculative loads 141 * ---------------------------------------------------- 142 */ 143 msr SSBS, xzr 144 apply_erratum c1_ultra, ERRATUM(3324333), ERRATA_C1ULTRA_3324333 145 /* model bug: not cleared on reset */ 146 sysreg_bit_clear C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 147 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 148 enable_mpmm 149cpu_reset_func_end c1_ultra 150 151func c1_ultra_core_pwr_dwn 152 /* --------------------------------------------------- 153 * Flip CPU power down bit in power control register. 154 * It will be set on powerdown and cleared on wakeup 155 * --------------------------------------------------- 156 */ 157 sysreg_bit_toggle C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 158 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 159 isb 160 signal_pabandon_handled 161 ret 162endfunc c1_ultra_core_pwr_dwn 163 164.section .rodata.c1_ultra_regs, "aS" 165c1_ultra_regs: /* The ASCII list of register names to be reported */ 166 .asciz "cpuectlr_el1", "" 167 168func c1_ultra_cpu_reg_dump 169 adr x6, c1_ultra_regs 170 mrs x8, C1_ULTRA_IMP_CPUECTLR_EL1 171 ret 172endfunc c1_ultra_cpu_reg_dump 173 174#if WORKAROUND_CVE_2025_0647 175declare_cpu_ops_eh c1_ultra, C1_ULTRA_MIDR, \ 176 c1_ultra_reset_func, \ 177 c1_ultra_impl_defined_el3_handler, \ 178 c1_ultra_core_pwr_dwn 179#else 180declare_cpu_ops c1_ultra, C1_ULTRA_MIDR, \ 181 c1_ultra_reset_func, \ 182 c1_ultra_core_pwr_dwn 183#endif 184