1/* 2 * Copyright (c) 2019-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a65ae.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14#include <dsu_macros.S> 15 16/* Hardware handled coherency */ 17#if !HW_ASSISTED_COHERENCY 18#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS 23#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a65ae 27 28/* Due to the nature of the errata it is applied unconditionally when chosen */ 29check_erratum_chosen cortex_a65ae, ERRATUM(1638571), ERRATA_A65AE_1638571 30/* erratum workaround is interleaved with generic code */ 31add_erratum_entry cortex_a65ae, ERRATUM(1638571), ERRATA_A65AE_1638571 32 33workaround_reset_start cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184 34 errata_dsu_936184_wa_impl 35workaround_reset_end cortex_a65ae, ERRATUM(936184) 36 37check_erratum_custom_start cortex_a65ae, ERRATUM(936184) 38 check_errata_dsu_936184_impl 39 ret 40check_erratum_custom_end cortex_a65ae, ERRATUM(936184) 41 42cpu_reset_func_start cortex_a65ae 43cpu_reset_func_end cortex_a65ae 44 45func cortex_a65ae_cpu_pwr_dwn 46 sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 47 isb 48 ret 49endfunc cortex_a65ae_cpu_pwr_dwn 50 51.section .rodata.cortex_a65ae_regs, "aS" 52cortex_a65ae_regs: /* The ascii list of register names to be reported */ 53 .asciz "cpuectlr_el1", "" 54 55func cortex_a65ae_cpu_reg_dump 56 adr x6, cortex_a65ae_regs 57 mrs x8, CORTEX_A65AE_ECTLR_EL1 58 ret 59endfunc cortex_a65ae_cpu_reg_dump 60 61declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \ 62 cortex_a65ae_reset_func, \ 63 cortex_a65ae_cpu_pwr_dwn 64