1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <drivers/arm/sp804_delay_timer.h> 12 #include <fvp_pas_def.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #if TRANSFER_LIST 16 #include <transfer_list.h> 17 #endif 18 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 #include <platform_def.h> 22 23 #include "fvp_private.h" 24 25 #if ENABLE_RME 26 /* 27 * The GPT library might modify the gpt regions structure to optimize 28 * the layout, so the array cannot be constant. 29 */ 30 static pas_region_t pas_regions[] = { 31 ARM_PAS_KERNEL, 32 ARM_PAS_SECURE, 33 ARM_PAS_REALM, 34 ARM_PAS_EL3_DRAM, 35 #ifdef ARM_PAS_GPTS 36 ARM_PAS_GPTS, 37 #endif 38 ARM_PAS_KERNEL_1, 39 ARM_PAS_PCI_MEM_1, 40 ARM_PAS_PCI_MEM_2 41 }; 42 43 static const arm_gpt_info_t arm_gpt_info = { 44 .pas_region_base = pas_regions, 45 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions), 46 .l0_base = ARM_L0_GPT_BASE, 47 .l1_base = ARM_L1_GPT_BASE, 48 .l0_size = ARM_L0_GPT_SIZE, 49 .l1_size = ARM_L1_GPT_SIZE, 50 .pps = GPCCR_PPS_1TB, 51 .pgs = GPCCR_PGS_4K 52 }; 53 #endif /* ENABLE_RME */ 54 55 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 56 { 57 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); 58 59 /* Initialize the platform config for future decision making */ 60 fvp_config_setup(); 61 62 #if RESET_TO_BL2 63 /* 64 * Initialize Interconnect for this cluster during cold boot. 65 * No need for locks as no other CPU is active. 66 */ 67 fvp_interconnect_init(); 68 69 /* Enable coherency in Interconnect for the primary CPU's cluster. */ 70 fvp_interconnect_enable(); 71 #endif 72 } 73 74 void bl2_platform_setup(void) 75 { 76 arm_bl2_platform_setup(); 77 78 /* Initialize System level generic or SP804 timer */ 79 fvp_timer_init(); 80 } 81 82 #if ENABLE_RME 83 const arm_gpt_info_t *plat_arm_get_gpt_info(void) 84 { 85 return &arm_gpt_info; 86 } 87 #endif /* ENABLE_RME */ 88 89 /******************************************************************************* 90 * This function returns the list of executable images 91 ******************************************************************************/ 92 struct bl_params *plat_get_next_bl_params(void) 93 { 94 struct bl_params *arm_bl_params; 95 bl_mem_params_node_t *param_node __unused; 96 const struct dyn_cfg_dtb_info_t *fw_config_info __unused; 97 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 98 entry_point_info_t *ep __unused; 99 uint32_t next_exe_img_id __unused; 100 uintptr_t fw_config_base __unused; 101 102 arm_bl_params = arm_get_next_bl_params(); 103 104 #if __aarch64__ 105 /* Get BL31 image node */ 106 param_node = get_bl_mem_params_node(BL31_IMAGE_ID); 107 #else /* aarch32 */ 108 /* Get SP_MIN image node */ 109 param_node = get_bl_mem_params_node(BL32_IMAGE_ID); 110 #endif /* __aarch64__ */ 111 assert(param_node != NULL); 112 113 #if TRANSFER_LIST 114 arm_bl_params->head = ¶m_node->params_node_mem; 115 arm_bl_params->head->ep_info = ¶m_node->ep_info; 116 arm_bl_params->head->image_id = param_node->image_id; 117 118 arm_bl2_setup_next_ep_info(param_node); 119 #elif (!RESET_TO_BL2 || ARM_FW_CONFIG_LOAD_ENABLE) && !EL3_PAYLOAD_BASE 120 fw_config_base = 0UL; 121 122 /* Update the next image's ep info with the FW config address */ 123 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); 124 assert(fw_config_info != NULL); 125 126 fw_config_base = fw_config_info->config_addr; 127 assert(fw_config_base != 0UL); 128 129 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; 130 #endif /* TRANSFER_LIST */ 131 132 return arm_bl_params; 133 } 134 135 int bl2_plat_handle_post_image_load(unsigned int image_id) 136 { 137 #if ((!RESET_TO_BL2 || ARM_FW_CONFIG_LOAD_ENABLE) && !EL3_PAYLOAD_BASE && \ 138 !TRANSFER_LIST) 139 if (image_id == HW_CONFIG_ID) { 140 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 141 struct transfer_list_entry *te __unused; 142 bl_mem_params_node_t *param_node __unused; 143 144 param_node = get_bl_mem_params_node(image_id); 145 assert(param_node != NULL); 146 147 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 148 assert(hw_config_info != NULL); 149 150 memcpy((void *)hw_config_info->secondary_config_addr, 151 (void *)hw_config_info->config_addr, 152 (size_t)param_node->image_info.image_size); 153 154 /* 155 * Ensure HW-config device tree is committed to memory, as the HW-Config 156 * might be used without cache and MMU enabled at BL33. 157 */ 158 flush_dcache_range(hw_config_info->secondary_config_addr, 159 param_node->image_info.image_size); 160 } 161 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/ 162 163 return arm_bl2_plat_handle_post_image_load(image_id); 164 } 165 166 uintptr_t plat_get_hw_dt_base(void) 167 { 168 const struct dyn_cfg_dtb_info_t *hw_config_info; 169 170 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 171 if (hw_config_info == NULL) { 172 return 0U; 173 } 174 175 return hw_config_info->secondary_config_addr; 176 } 177