1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a76ae.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a76ae 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 31 32workaround_reset_start cortex_a76ae, ERRATUM(1931427), ERRATA_A76AE_1931427 33 sysreg_bit_set CORTEX_A76AE_CPUACTLR2_EL1, BIT(2) 34workaround_reset_end cortex_a76ae, ERRATUM(1931427) 35 36check_erratum_ls cortex_a76ae, ERRATUM(1931427), CPU_REV(1, 0) 37 38workaround_reset_start cortex_a76ae, ERRATUM(1931435), ERRATA_A76AE_1931435 39 sysreg_bit_set CORTEX_A76AE_CPUACTLR_EL1, BIT(13) 40workaround_reset_end cortex_a76ae, ERRATUM(1931435) 41 42check_erratum_ls cortex_a76ae, ERRATUM(1931435), CPU_REV(1, 0) 43 44workaround_reset_start cortex_a76ae, ERRATUM(1969401), ERRATA_A76AE_1969401 45 ldr x0,=0x3 46 msr CORTEX_A76AE_CPUPSELR_EL3,x0 47 ldr x0,=0x10E3900002 48 msr CORTEX_A76AE_CPUPOR_EL3,x0 49 ldr x0,=0x10FFF00083 50 msr CORTEX_A76AE_CPUPMR_EL3,x0 51 ldr x0,=0x2001003FF 52 msr CORTEX_A76AE_CPUPCR_EL3,x0 53 54 ldr x0,=0x4 55 msr CORTEX_A76AE_CPUPSELR_EL3,x0 56 ldr x0,=0x10E3800082 57 msr CORTEX_A76AE_CPUPOR_EL3,x0 58 ldr x0,= 0x10FFF00083 59 msr CORTEX_A76AE_CPUPMR_EL3,x0 60 ldr x0,=0x2001003FF 61 msr CORTEX_A76AE_CPUPCR_EL3,x0 62 63 ldr x0,=0x5 64 msr CORTEX_A76AE_CPUPSELR_EL3,x0 65 ldr x0,=0x10E3800200 66 msr CORTEX_A76AE_CPUPOR_EL3,x0 67 ldr x0,=0x10FFF003E0 68 msr CORTEX_A76AE_CPUPMR_EL3,x0 69 ldr x0,=0x2001003FF 70 msr CORTEX_A76AE_CPUPCR_EL3,x0 71workaround_reset_end cortex_a76ae, ERRATUM(1969401) 72 73check_erratum_ls cortex_a76ae, ERRATUM(1969401), CPU_REV(1, 0) 74 75workaround_reset_start cortex_a76ae, ERRATUM(2371140), ERRATA_A76AE_2371140 76 sysreg_bit_set CORTEX_A76AE_CPUACTLR2_EL1, BIT(0) 77workaround_reset_end cortex_a76ae, ERRATUM(2371140) 78 79check_erratum_ls cortex_a76ae, ERRATUM(2371140), CPU_REV(1, 1) 80 81workaround_runtime_start cortex_a76ae, ERRATUM(2753838), ERRATA_A76AE_2753838 82 dsb sy 83workaround_runtime_end cortex_a76ae, ERRATUM(2753838) 84 85check_erratum_ls cortex_a76ae, ERRATUM(2753838), CPU_REV(1, 1) 86 87workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 88#if IMAGE_BL31 89 /* 90 * The Cortex-A76ae generic vectors are overridden to apply errata 91 * mitigation on exception entry from lower ELs. 92 */ 93 override_vector_table wa_cve_vbar_cortex_a76ae 94 isb 95#endif /* IMAGE_BL31 */ 96workaround_reset_end cortex_a76ae, CVE(2022, 23960) 97 98cpu_reset_func_start cortex_a76ae 99cpu_reset_func_end cortex_a76ae 100 101 /* ---------------------------------------------------- 102 * HW will do the cache maintenance while powering down 103 * ---------------------------------------------------- 104 */ 105func cortex_a76ae_core_pwr_dwn 106 sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK 107 apply_erratum cortex_a76ae, ERRATUM(2753838), ERRATA_A76AE_2753838 108 isb 109 ret 110endfunc cortex_a76ae_core_pwr_dwn 111 112 /* --------------------------------------------- 113 * This function provides cortex_a76ae specific 114 * register information for crash reporting. 115 * It needs to return with x6 pointing to 116 * a list of register names in ascii and 117 * x8 - x15 having values of registers to be 118 * reported. 119 * --------------------------------------------- 120 */ 121.section .rodata.cortex_a76ae_regs, "aS" 122cortex_a76ae_regs: /* The ASCII list of register names to be reported */ 123 .asciz "cpuectlr_el1", "" 124 125func cortex_a76ae_cpu_reg_dump 126 adr x6, cortex_a76ae_regs 127 mrs x8, CORTEX_A76AE_CPUECTLR_EL1 128 ret 129endfunc cortex_a76ae_cpu_reg_dump 130 131declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ 132 cortex_a76ae_core_pwr_dwn 133