1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53For example: `Cortex-A72 MPCore Software Developers Errata Notice`_ 54 55The errata workarounds are implemented for a particular revision or a set of 56processor revisions. This is checked by the reset handler at runtime. Each 57errata workaround is identified by its ``ID`` as specified in the processor's 58errata notice document. The format of the define used to enable/disable the 59errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 60is for example ``A57`` for the ``Cortex_A57`` CPU. 61 62Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 63write errata workaround functions. 64 65All workarounds are disabled by default. The platform is responsible for 66enabling these workarounds according to its requirement by defining the 67errata workaround build flags in the platform specific makefile. In case 68these workarounds are enabled for the wrong CPU revision then the errata 69workaround is not applied. In the DEBUG build, this is indicated by 70printing a warning to the crash console. 71 72In the current implementation, a platform which has more than 1 variant 73with different revisions of a processor has no runtime mechanism available 74for it to specify which errata workarounds should be enabled or not. 75 76The value of the build flags is 0 by default, that is, disabled. A value of 1 77will enable it. 78 79For Cortex-A9, the following errata build flags are defined : 80 81- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 82 CPU. This needs to be enabled for all revisions of the CPU. 83 84For Cortex-A15, the following errata build flags are defined : 85 86- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 87 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 88 89- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92For Cortex-A17, the following errata build flags are defined : 93 94- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 95 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 96 97- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100For Cortex-A35, the following errata build flags are defined : 101 102- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 103 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 104 105For Cortex-A53, the following errata build flags are defined : 106 107- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 108 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 109 110- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 114 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 115 116- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 117 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 118 119- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 120 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 121 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 122 sections. 123 124- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 125 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 126 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 127 ``A53_DISABLE_NON_TEMPORAL_HINT``. 128 129- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 130 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 131 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 132 which are 4kB aligned. 133 134- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 135 CPUs. Though the erratum is present in every revision of the CPU, 136 this workaround is only applied to CPUs from r0p3 onwards, which feature 137 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 138 Earlier revisions of the CPU have other errata which require the same 139 workaround in software, so they should be covered anyway. 140 141- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 142 revisions of Cortex-A53 CPU. 143 144For Cortex-A55, the following errata build flags are defined : 145 146- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 147 CPU. This needs to be enabled only for revision r0p0 of the CPU. 148 149- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 157 158- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 163 164- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 165 revisions of Cortex-A55 CPU. 166 167For Cortex-A57, the following errata build flags are defined : 168 169- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 170 CPU. This needs to be enabled only for revision r0p0 of the CPU. 171 172- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 183 184- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 186 187- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 195 196- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 201 202- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 203 revisions of Cortex-A57 CPU. 204 205For Cortex-A65, the following errata build flags are defined : 206 207- ``ERRATA_A65_1179935``: This applies errata 1179935 workaround to Cortex-A65 208 CPU. This needs to be enabled only for revision r0p0 of the CPU, and is fixed 209 in r1p0. 210 211- ``ERRATA_A65_1227419``: This applies errata 1227419 workaround to Cortex-A65 212 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU and 213 is fixed in r1p1. 214 215- ``ERRATA_A65_1541130``: This applies errata 1541130 workaround to r0p0, r1p0, 216 r1p1, r1p2 revisions of the CPU and is still open. 217 218For Cortex-A72, the following errata build flags are defined : 219 220- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 221 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 222 223- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 224 revisions of Cortex-A72 CPU. 225 226For Cortex-A73, the following errata build flags are defined : 227 228- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 229 CPU. This needs to be enabled only for revision r0p0 of the CPU. 230 231- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 232 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 233 234For Cortex-A75, the following errata build flags are defined : 235 236- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 237 CPU. This needs to be enabled only for revision r0p0 of the CPU. 238 239- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 240 CPU. This needs to be enabled only for revision r0p0 of the CPU. 241 242For Cortex-A76, the following errata build flags are defined : 243 244- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 245 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 246 247- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 248 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 249 250- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 251 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 252 253- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 255 256- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 258 259- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 260 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 261 262- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 263 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 264 265- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 266 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 267 268- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 269 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 270 limitation of errata framework this errata is applied to all revisions 271 of Cortex-A76 CPU. 272 273- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 274 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 275 276- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 277 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 278 279- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 280 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 281 still open. 282 283For Cortex-A76AE, the following errata build flags are defined : 284 285- ``ERRATA_A76AE_1931427``: This applies errata 1931427 workaround to Cortex-A76AE 286 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 287 fixed in r1p1. 288 289- ``ERRATA_A76AE_1931435``: This applies errata 1931435 workaround to Cortex-A76AE 290 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 291 fixed in r1p1. 292 293- ``ERRATA_A76AE_1969401``: This applies errata 1969401 workaround to Cortex-A76AE 294 CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is 295 fixed in r1p1. 296 297- ``ERRATA_A76AE_2371140``: This applies errata 2371140 workaround to Cortex-A76AE 298 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 299 still open. 300 301- ``ERRATA_A76AE_2753838``: This applies errata 2753838 workaround to Cortex-A76AE 302 CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is 303 still open. 304 305For Cortex-A77, the following errata build flags are defined : 306 307- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 308 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 309 310- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 311 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 312 313- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 314 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 315 316- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 317 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 318 319- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 320 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 321 322 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 323 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 324 325 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 326 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 327 328For Cortex-A78, the following errata build flags are defined : 329 330- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 331 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 332 333- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 334 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 335 336- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 337 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 338 issue but there is no workaround for that revision. 339 340- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 341 CPU. This needs to be enabled for revisions r0p0 and r1p0. 342 343- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 344 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 345 346- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 347 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 348 is present in r0p0 but there is no workaround. It is still open. 349 350- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 351 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 352 it is still open. 353 354- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 355 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 356 it is still open. 357 358- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 359 CPU, this erratum affects system configurations that do not use an ARM 360 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 361 and r1p2 and it is still open. 362 363- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 364 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 365 it is still open. 366 367- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 368 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 369 it is still open. 370 371- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 372 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 373 it is still open. 374 375For Cortex-A78AE, the following errata build flags are defined : 376 377- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 378 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 379 This erratum is still open. 380 381- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 382 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 383 erratum is still open. 384 385- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 386 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 387 This erratum is still open. 388 389- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 390 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 391 erratum is still open. 392 393- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 394 Cortex-A78AE CPU. This erratum affects system configurations that do not use 395 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 396 r0p2. This erratum is still open. 397 398For Cortex-A78C, the following errata build flags are defined : 399 400- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 401 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 402 fixed in r0p1. 403 404- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 405 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 406 fixed in r0p1. 407 408- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 409 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 410 it is still open. 411 412- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 413 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 414 erratum is still open. 415 416- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 417 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 418 erratum is still open. 419 420- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 421 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 422 erratum is still open. 423 424- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 425 Cortex-A78C CPU, this erratum affects system configurations that do not use 426 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 427 and is still open. 428 429- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 430 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 431 This erratum is still open. 432 433- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 434 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 435 This erratum is still open. 436 437- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 438 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 439 This erratum is still open. 440 441For Cortex-X1 CPU, the following errata build flags are defined: 442 443- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 444 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 445 446- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 447 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 448 449- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 450 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 451 452For Neoverse N1, the following errata build flags are defined : 453 454- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 455 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 456 457- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 458 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 459 460- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 461 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 462 463- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 464 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 465 466- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 467 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 468 469- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 470 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 471 472- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 473 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 474 475- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 476 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 477 478- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 479 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 480 481- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 482 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 483 484- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 485 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 486 487- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 488 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 489 490- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 491 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 492 revisions r0p0, r1p0, and r2p0 there is no workaround. 493 494- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 495 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 496 still open. 497 498- ``ERRATA_N1_3324349``: This applies errata 3324349 workaround to Neoverse-N1 499 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 500 still open. 501 502For Neoverse V1, the following errata build flags are defined : 503 504- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 505 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 506 r1p0. 507 508- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 509 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 510 in r1p1. 511 512- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 513 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 514 in r1p1. 515 516- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 517 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 518 in r1p1. 519 520- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 521 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 522 523- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 524 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 525 CPU. 526 527- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 528 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 529 issue is present in r0p0 as well but there is no workaround for that 530 revision. It is still open. 531 532- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 533 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 534 CPU. It is still open. 535 536- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 537 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 538 issue is present in r0p0 as well but there is no workaround for that 539 revision. It is still open. 540 541- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 542 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 543 the CPU. 544 545- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 546 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 547 It has been fixed in r1p2. 548 549- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 550 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 551 It is still open. 552 553- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 554 CPU, this erratum affects system configurations that do not use an ARM 555 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 556 It has been fixed in r1p2. 557 558- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 559 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 560 CPU. It is still open. 561 562- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 563 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 564 CPU. It is still open. 565 566- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 567 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 568 CPU. It is still open. 569 570For Neoverse V2, the following errata build flags are defined : 571 572- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 573 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 574 r0p2. 575 576- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 577 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 578 r0p2. 579 580- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 581 CPU, this affects system configurations that do not use and ARM interconnect 582 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 583 in r0p2. 584 585- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 586 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 587 r0p2. 588 589- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 590 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 591 r0p2. 592 593- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 594 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 595 r0p2. 596 597- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 598 CPU, this affects all configurations. This needs to be enabled for revisions 599 r0p0 and r0p1. It has been fixed in r0p2. 600 601- ``ERRATA_V2_3442699``: This applies errata 3442699 workaround to Neoverse-V2 602 CPU. This needs to be enabled for revision r0p0 - r0p2 and is still open. 603 604- ``ERRATA_V2_3701771``: This applies errata 3701771 workaround to Neoverse-V2 605 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is 606 still open. 607 608- ``ERRATA_V2_3841324``: This applies errata 3841324 workaround to Neoverse-V2 609 CPU. This needs to be enabled only for revisions r0p0 and r0p1 of 610 the CPU. It is fixed in r0p2. 611 612For Neoverse V3, the following errata build flags are defined : 613 614- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 615 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 616 617- ``ERRATA_V3_3312417``: This applies errata 3312417 workaround to Neoverse-V3 618 CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and is 619 fixed in r0p2. 620 621- ``ERRATA_V3_3696307``: This applies errata 3696307 workaround to Neoverse-V3 622 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 623 r0p2. 624 625- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 626 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 627 is still open. 628 629- ``ERRATA_V3_3734562``: This applies errata 3734562 workaround to Neoverse-V3 630 CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and 631 is fixed in r0p2. 632 633- ``ERRATA_V3_3782181``: This applies errata 3782181 workaround to Neoverse-V3 634 CPU. This needs to be enabled for revision r0p1 of the CPU and is fixed in 635 r0p2. 636 637- ``ERRATA_V3_3864536``: This applies errata 3864536 workaround to Neoverse-V3 638 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and 639 is still open. 640 641- ``ERRATA_V3_3878291``: This applies errata 3878291 workaround to Neoverse-V3 642 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and 643 is still open. 644 645For Cortex-A710, the following errata build flags are defined : 646 647- ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to 648 Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has 649 been fixed in r2p0. 650 651- ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to 652 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 653 It has been fixed in r2p0. 654 655- ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to 656 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 657 It has been fixed in r2p0. 658 659- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to 660 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0. 661 It has been fixed in r2p0. 662 663- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 664 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 665 r2p0 of the CPU. It is still open. 666 667- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 668 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 669 r2p0 of the CPU. It is still open. 670 671- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 672 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 673 and is still open. 674 675- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 676 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 677 of the CPU and is still open. 678 679- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 680 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 681 is still open. 682 683- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 684 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 685 of the CPU and is fixed in r2p1. 686 687- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 688 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 689 of the CPU and is fixed in r2p1. 690 691- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 692 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 693 and is fixed in r2p1. 694 695- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 696 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 697 of the CPU and is fixed in r2p1. 698 699- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 700 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 701 r2p1 of the CPU and is still open. 702 703- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 704 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 705 of the CPU and is fixed in r2p1. 706 707- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 708 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 709 of the CPU and is fixed in r2p1. 710 711- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 712 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 713 of the CPU and is fixed in r2p1. 714 715- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 716 CPU, and applies to system configurations that do not use and ARM 717 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 718 is still open. 719 720- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 721 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 722 r2p1 of the CPU and is still open. 723 724- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 725 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 726 r2p1 of the CPU and is still open. 727 728- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 729 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 730 CPU and is still open. 731 732- ``ERRATA_A710_3324338``: This applies errata 3324338 workaround to 733 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 734 r2p1 of the CPU and is still open. 735 736- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 737 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 738 CPU and is still open. 739 740For Neoverse N2, the following errata build flags are defined : 741 742- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 743 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 744 745- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 746 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 747 748- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 749 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 750 751- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 752 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 753 754- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 755 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 756 757- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 758 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 759 760- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 761 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 762 763- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 764 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 765 766- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 767 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 768 769- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 770 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 771 772- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 773 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 774 r0p1. 775 776- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 777 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 778 r0p1. 779 780- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 781 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 782 it is fixed in r0p3. 783 784- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 785 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 786 787- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 788 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 789 r0p1. 790 791- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 792 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 793 in r0p3. 794 795- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 796 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 797 in r0p3. 798 799- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 800 CPU, this erratum affects system configurations that do not use and ARM 801 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 802 It is fixed in r0p3. 803 804- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 805 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 806 in r0p3. 807 808- ``ERRATA_N2_3324339``: This applies errata 3324339 workaround to Neoverse-N2 809 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 810 still open. 811 812- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 813 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 814 still open. 815 816For Neoverse N3, the following errata build flags are defined : 817 818- ``ERRATA_N3_3456111``: This applies errata 3456111 workaround to Neoverse-N3 819 CPU. This needs to be enabled for revisions r0p0 and r0p1 and is still open. 820 821- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 822 CPU. This needs to be enabled for revisions r0p0 and is still open. 823 824For Cortex-X2, the following errata build flags are defined : 825 826- ``ERRATA_X2_1901946``: This applies errata 1901946 workaround to Cortex-X2 827 CPU. This needs to be enabled only for r1p0, it is fixed in r2p0. 828 829- ``ERRATA_X2_1916945``: This applies errata 1916945 workaround to Cortex-X2 830 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 831 is fixed in r2p0. 832 833- ``ERRATA_X2_1917258``: This applies errata 1917258 workaround to Cortex-X2 834 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 835 is fixed in r2p0. 836 837- ``ERRATA_X2_1927200``: This applies errata 1927200 workaround to Cortex-X2 838 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 839 is fixed in r2p0. 840 841- ``ERRATA_X2_1934260``: This applies errata 1934260 workaround to Cortex-X2 842 CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed 843 in r2p0. 844 845- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 846 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 847 CPU, it is fixed in r2p1. 848 849- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 850 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 851 CPU, it is fixed in r2p1. 852 853- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 854 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 855 CPU, it is fixed in r2p1. 856 857- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 858 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 859 in r2p1. 860 861- ``ERRATA_X2_2136059``: This applies errata 2136059 workaround to Cortex-X2 862 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 863 CPU, it is fixed in r2p1. 864 865- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 866 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 867 in r2p1. 868 869- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 870 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 871 CPU, it is fixed in r2p1. 872 873- ``ERRATA_X2_2267065``: This applies errata 2267065 workaround to Cortex-X2 874 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 875 CPU, it is fixed in r2p1. 876 877- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 878 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 879 CPU and is still open. 880 881- ``ERRATA_X2_2291219``: This applies errata 2291219 workaround to Cortex-X2 882 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 883 CPU, it is fixed in r2p1. 884 885- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 886 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 887 CPU, it is fixed in r2p1. 888 889- ``ERRATA_X2_2701952``: This applies errata 2701952 workaround to Cortex-X2 890 CPU and affects system configurations that do not use an Arm interconnect IP. 891 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 892 still open. 893 894- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 895 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 896 CPU and is still open. 897 898- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 899 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 900 CPU and is still open. 901 902- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 903 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 904 CPU and is still open. 905 906- ``ERRATA_X2_3324338``: This applies errata 3324338 workaround to Cortex-X2 907 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 908 CPU and is still open. 909 910- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 911 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 912 CPU and is still open. 913 914For Cortex-X3, the following errata build flags are defined : 915 916- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 917 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 918 is fixed in r1p1. 919 920- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 921 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 922 fixed in r1p2. 923 924- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 925 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 926 of the CPU, it is fixed in r1p1. 927 928- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 929 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 930 of the CPU, it is fixed in r1p1. 931 932- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 933 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 934 CPU, it is fixed in r1p2. 935 936- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 937 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 938 It is fixed in r1p1. 939 940- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 941 CPU and affects system configurations that do not use an ARM interconnect 942 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 943 in r1p2. 944 945- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 946 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 947 r1p1. It is fixed in r1p2. 948 949- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 950 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 951 fixed in r1p2. 952 953- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 954 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 955 CPU. It is fixed in r1p2. 956 957- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3 958 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 959 of the CPU. It is still open. 960 961- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3 962 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 963 of the CPU. It is still open. 964 965- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 966 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 967 of the CPU and it is still open. 968 969- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3 970 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of 971 the CPU. It is fixed in r1p2. 972 973For Cortex-X4, the following errata build flags are defined : 974 975- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 976 CPU and affects system configurations that do not use an Arm interconnect IP. 977 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 978 The workaround for this erratum is not implemented in EL3, but the flag can 979 be enabled/disabled at the platform level. The flag is used when the errata ABI 980 feature is enabled and can assist the Kernel in the process of 981 mitigation of the erratum. 982 983- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 984 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 985 r0p2. 986 987- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 988 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 989 in r0p2. 990 991- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 992 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 993 994- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 995 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 996 997- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 998 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 999 1000- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 1001 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1002 1003- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 1004 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1005 1006- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 1007 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1008 1009- ``ERRATA_X4_3133195``: This applies errata 3133195 workaround to Cortex-X4 1010 CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3. 1011 1012- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 1013 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 1014 It is still open. 1015 1016- ``ERRATA_X4_3887999``: This applies errata 3887999 workaround to Cortex-X4 1017 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3. 1018 It is still open. 1019 1020For Cortex-X925, the following errata build flags are defined : 1021 1022- ``ERRATA_X925_2921199``: This applies errata 2921199 workaround to Cortex-X925 1023 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1024 1025- ``ERRATA_X925_2922378``: This applies errata 2922378 workaround to Cortex-X925 1026 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1027 1028- ``ERRATA_X925_2933290``: This applies errata 2933290 workaround to Cortex-X925 1029 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1030 1031- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 1032 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 1033 1034- ``ERRATA_X925_3324334``: This applies errata 3324334 workaround to Cortex-X925 1035 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1036 1037- ``ERRATA_X925_3692980``: This applies errata 3692980 workaround to Cortex-X925 1038 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1039 1040- ``ERRATA_X925_3730893``: This applies errata 3730893 workaround to Cortex-X925 1041 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1042 1043- ``ERRATA_X925_3865185``: This applies errata 3865185 workaround to Cortex-X925 1044 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 1045 1046- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 1047 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 1048 1049For Cortex-A510, the following errata build flags are defined : 1050 1051- ``ERRATA_A510_2008766``: This applies errata 2008766 workaround to 1052 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1053 r0p3, r1p0, r1p1, r1p2 and r1p3. It is still open. 1054 1055- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 1056 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1057 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1058 1059- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 1060 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 1061 r0p2, it is fixed in r0p3. 1062 1063- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 1064 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 1065 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 1066 workaround for those revisions. 1067 1068- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 1069 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 1070 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 1071 workaround for those revisions. 1072 1073- ``ERRATA_A510_2169012``: This applies errata 2169012 workaround to 1074 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 1075 r0p2, r0p3 and r1p0, it is fixed in r1p1. 1076 1077- ``ERRATA_A510_2218134``: This applies errata 2218134 workaround to 1078 Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed 1079 in r1p1. 1080 1081- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 1082 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1083 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 1084 ENABLE_MPMM=1. 1085 1086- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 1087 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1088 r0p3 and r1p0, it is fixed in r1p1. 1089 1090- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 1091 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1092 r0p3 and r1p0, it is fixed in r1p1. 1093 1094- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 1095 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 1096 r0p3, r1p0 and r1p1. It is fixed in r1p2. 1097 1098- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 1099 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1100 r0p3, r1p0, r1p1, and is fixed in r1p2. 1101 1102- ``ERRATA_A510_2420992``: This applies errata 2420992 workaround to 1103 Cortex-A510 CPU. This needs to applied for revisions r1p0 and r1p1, and is 1104 fixed in r1p2. 1105 1106- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 1107 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 1108 r0p3, r1p0, r1p1. It is fixed in r1p2. 1109 1110- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 1111 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 1112 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 1113 1114- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 1115 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1116 r1p0, r1p1, r1p2 and r1p3 and is still open. 1117 1118- ``ERRATA_A510_3672349``: This applies erratum 3672349 workaround to 1119 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1120 r1p0, r1p1, r1p2 and r1p3 and is still open. 1121 1122- ``ERRATA_A510_3704847``: This applies erratum 3704847 workaround to 1123 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 1124 r1p0, r1p1, r1p2 and r1p3 and is still open. 1125 1126For Cortex-A520, the following errata build flags are defined : 1127 1128- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 1129 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 1130 CPU and is still open. 1131 1132- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 1133 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1134 It is still open. 1135 1136- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 1137 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1138 It is fixed in r0p2. 1139 1140For Cortex-A715, the following errata build flags are defined : 1141 1142- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 1143 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 1144 It is fixed in r1p1. 1145 1146- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 1147 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1148 fixed in r1p1. 1149 1150- ``ERRATA_A715_2376701``: This applies errata 2376701 workaround to 1151 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 1152 fixed in r1p1. 1153 1154- ``ERRATA_A715_2409570``: This applies errata 2409570 workaround to 1155 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1156 It is fixed in r1p1. This errata also applies to r0p0 but that revision has a 1157 different workaround, and since r0p0 is not used in production hardware it is 1158 not implemented. 1159 1160- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 1161 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 1162 when SPE(Statistical profiling extension)=True. The errata is fixed 1163 in r1p1. 1164 1165- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 1166 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1167 It is fixed in r1p1. 1168 1169- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 1170 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 1171 workaround for revision r0p0. It is fixed in r1p1. 1172 1173- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1174 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1175 It is fixed in r1p1. 1176 1177- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1178 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1179 and r1p1. It is fixed in r1p2. 1180 1181- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1182 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1183 r1p1 and r1p2. It is fixed in r1p3. 1184 1185- ``ERRATA_A715_3456084``: This applies errata 3456084 workaround to 1186 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1187 r1p1, r1p2 and r1p3. It is still open. 1188 1189- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1190 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1191 r1p2 and r1p3. It is still open. 1192 1193- ``ERRATA_A715_3711916``: This applies errata 3711916 workaround to 1194 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1195 r1p1, r1p2 and r1p3. It is still open. 1196 1197For Cortex-A720, the following errata build flags are defined : 1198 1199- ``ERRATA_A720_2729604``: This applies errata 2729604 workaround to 1200 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1201 It is fixed in r0p2. 1202 1203- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1204 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1205 It is fixed in r0p2. 1206 1207- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1208 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1209 It is fixed in r0p2. 1210 1211- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1212 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1213 It is fixed in r0p2. 1214 1215- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1216 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1217 It is fixed in r0p2. 1218 1219- ``ERRATA_A720_3456091``: This applies errata 3456091 workaround to 1220 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1221 and r0p2. It is still open. 1222 1223- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1224 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1225 and r0p2. It is still open. 1226 1227- ``ERRATA_A720_3711910``: This applies errata 3711910 workaround to 1228 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1229 and r0p2. It is still open. 1230 1231For Cortex-A720_AE, the following errata build flags are defined : 1232 1233- ``ERRATA_A720_AE_3456103``: This applies errata 3456103 workaround to 1234 Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0 and r0p1. It 1235 is still open. 1236 1237- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1238 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1239 It is still open. 1240 1241For Cortex-A725, the following errata build flags are defined : 1242 1243- ``ERRATA_A725_2874943``: This applies errata 2874943 workaround to 1244 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 when 1245 FEAT_SPE is enabled. It is fixed in r0p1. 1246 1247- ``ERRATA_A725_2936490``: This applies errata 2936490 workaround to 1248 Cortex-A725 CPU. This needs to be enabled for revisions r0p0. 1249 It is fixed in r0p1. 1250 1251- ``ERRATA_A725_3456106``: This applies errata 3456106 workaround to 1252 Cortex-A725 CPU. This needs to be enabled for revisions r0p0, r0p1 1253 and r0p2. It is still open. 1254 1255- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1256 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1257 It is fixed in r0p2. 1258 1259- ``ERRATA_A725_3711914``: This applies errata 3711914 workaround to 1260 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1261 It is fixed in r0p2. 1262 1263For C1-Ultra, the following errata build flags are defined : 1264 1265- ``ERRATA_C1ULTRA_3324333``: This applies erratum 3324333 workaround to 1266 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is fixed 1267 in r1p0. 1268 1269- ``ERRATA_C1ULTRA_3502731``: This applies erratum 3502731 workaround to 1270 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1271 fixed in r1p0. 1272 1273- ``ERRATA_C1ULTRA_3651221``: This applies erratum 3651221 workaround to 1274 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1275 fixed in r1p0. 1276 1277- ``ERRATA_C1ULTRA_3658374``: This applies erratum 3658374 workaround to 1278 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1279 is still open. 1280 1281- ``ERRATA_C1ULTRA_3684152``: This applies erratum 3684152 workaround to 1282 C1-Ultra CPU. This needs to be enabled for revision r0p0 and is 1283 fixed in r1p0. 1284 1285- ``ERRATA_C1ULTRA_3705939``: This applies erratum 3705939 workaround to 1286 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1287 is still open. 1288 1289- ``ERRATA_C1ULTRA_3815514``: This applies erratum 3815514 workaround to 1290 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1291 is still open. 1292 1293- ``ERRATA_C1ULTRA_3865171``: This applies erratum 3865171 workaround to 1294 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1295 is still open. 1296 1297- ``ERRATA_C1ULTRA_3926381``: This applies erratum 3926381 workaround to 1298 C1-Ultra CPU. This needs to be enabled for revision r1p0 and is still 1299 open. 1300 1301- ``ERRATA_C1ULTRA_4102704``: This applies erratum 4102704 workaround to 1302 C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and 1303 is still open. 1304 1305For C1-Premium, the following errata build flags are defined : 1306 1307- ``ERRATA_C1PREMIUM_3324333``: This applies errata 3324333 workaround to 1308 C1-Premium CPU. This needs to be enabled for revision r0p0, and is 1309 fixed in r1p0. 1310 1311- ``ERRATA_C1PREMIUM_3502731``: This applies errata 3502731 workaround to 1312 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1313 in r1p0. 1314 1315- ``ERRATA_C1PREMIUM_3651221``: This applies errata 3651221 workaround to 1316 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1317 in r1p0. 1318 1319- ``ERRATA_C1PREMIUM_3684152``: This applies errata 3684152 workaround to 1320 C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed 1321 in r1p0. 1322 1323- ``ERRATA_C1PREMIUM_3705939``: This applies errata 3705939 workaround to 1324 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1325 is still open. 1326 1327- ``ERRATA_C1PREMIUM_3815514``: This applies errata 3815514 workaround to 1328 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1329 is still open. 1330 1331- ``ERRATA_C1PREMIUM_3865171``: This applies errata 3865171 workaround to 1332 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1333 is still open. 1334 1335- ``ERRATA_C1PREMIUM_3926381``: This applies errata 3926381 workaround to 1336 C1-Premium CPU. This needs to be enabled for revision r1p0 and is 1337 still open. 1338 1339- ``ERRATA_C1PREMIUM_4102704``: This applies errata 4102704 workaround to 1340 C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and 1341 is still open. 1342 1343For C1-Pro, the following errata build flags are defined : 1344 1345- ``ERRATA_C1PRO_3619847``: This applies errata 3619847 workaround to C1-Pro 1346 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1347 1348- ``ERRATA_C1PRO_3338470``: This applies errata 3338470 workaround to C1-Pro 1349 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1350 1351- ``ERRATA_C1PRO_3362007``: This applies errata 3362007 workaround to C1-Pro 1352 CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0. 1353 1354- ``ERRATA_C1PRO_3684268``: This applies errata 3684268 workaround to C1-Pro 1355 CPU. This needs to be enabled for revisions r0p0, r1p0 and is fixed in 1356 r1p1. 1357 1358- ``ERRATA_C1PRO_3686597``: This applies errata 3686597 workaround to C1-Pro 1359 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1360 is fixed in r1p1. 1361 1362- ``ERRATA_C1PRO_3694158``: This applies errata 3694158 workaround to C1-Pro 1363 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 and is 1364 fixed in r1p2. 1365 1366- ``ERRATA_C1PRO_3706576``: This applies errata 3706576 workaround to C1-Pro 1367 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1368 is fixed in r1p1. 1369 1370- ``ERRATA_C1PRO_3300099``: This applies errata 3300099 workaround to C1-Pro 1371 CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it 1372 is fixed in r1p1. 1373 1374For C1-Nano, the following errata build flags are defined : 1375 1376- ``ERRATA_C1NANO_3392149``: This applies errata 3392149 workaround to 1377 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1378 in r0p1. 1379 1380- ``ERRATA_C1NANO_3419531``: This applies errata 3419531 workaround to 1381 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1382 in r0p1. 1383 1384- ``ERRATA_C1NANO_3437202``: This applies errata 3437202 workaround to 1385 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1386 in r0p1. 1387 1388- ``ERRATA_C1NANO_3516455``: This applies errata 3516455 workaround to 1389 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1390 in r0p1. 1391 1392- ``ERRATA_C1NANO_3616450``: This applies errata 3616450 workaround to 1393 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1394 in r0p1. 1395 1396- ``ERRATA_C1NANO_3630925``: This applies errata 3630925 workaround to 1397 C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed 1398 in r0p1. 1399 1400- ``ERRATA_C1NANO_3754876``: This applies errata 3754876 workaround to 1401 C1-Nano CPU. This needs to be enabled for revisions r0p0 and r0p1, and 1402 is fixed in r0p2. 1403 1404DSU Errata Workarounds 1405---------------------- 1406 1407Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1408Shared Unit) errata. The DSU errata details can be found in the respective Arm 1409documentation: 1410 1411- `Arm DSU Software Developers Errata Notice`_. 1412 1413Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1414document. Thus, the build flags which enable/disable the errata workarounds 1415have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1416of DSU errata workarounds are similar to `CPU errata workarounds`_. 1417 1418For DSU errata, the following build flags are defined: 1419 1420- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1421 affected DSU configurations. This errata applies only for those DSUs that 1422 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1423 workaround results in increased DSU power consumption on idle. 1424 1425- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1426 affected DSU configurations. This errata applies only for those DSUs that 1427 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1428 r2p0 it is fixed). However, please note that this workaround results in 1429 increased DSU power consumption on idle. 1430 1431- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1432 affected DSU configurations. This errata applies for those DSUs with 1433 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1434 please note that this workaround results in increased DSU power consumption 1435 on idle. 1436 1437- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the 1438 affected DSU-120 configurations. This erratum applies to some r2p0 1439 implementations and is fixed in r2p1. The affected r2p0 implementations 1440 are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit 1441 and making sure it's clear. 1442 1443CPU Specific optimizations 1444-------------------------- 1445 1446This section describes some of the optimizations allowed by the CPU micro 1447architecture that can be enabled by the platform as desired. 1448 1449- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1450 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1451 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1452 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1453 is a known safe deviation from the Cortex-A57 TRM defined power down 1454 sequence. Each Cortex-A57 based platform must make its own decision on 1455 whether to use the optimization. 1456 1457- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1458 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1459 in a way most programmers expect, and will most probably result in a 1460 significant speed degradation to any code that employs them. The Armv8-A 1461 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1462 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1463 flag enforces this behaviour. This needs to be enabled only for revisions 1464 <= r0p3 of the CPU and is enabled by default. 1465 1466- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1467 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1468 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1469 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1470 `Cortex-A57 Software Optimization Guide`_. 1471 1472- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1473 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1474 this bit only if their memory system meets the requirement that cache 1475 line fill requests from the Cortex-A57 processor are atomic. Each 1476 Cortex-A57 based platform must make its own decision on whether to use 1477 the optimization. This flag is disabled by default. 1478 1479- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1480 level cache(LLC) is present in the system, and that the DataSource field 1481 on the master CHI interface indicates when data is returned from the LLC. 1482 This is used to control how the LL_CACHE* PMU events count. 1483 Default value is 0 (Disabled). 1484 1485- ``NEOVERSE_N2_PREFETCHER_DISABLE``: This flag disables the region prefetcher 1486 on the Neoverse N2 core. This is used during performance analysis to get clean 1487 and repeatable measurements of the cache by preventing speculative data fetches 1488 from interfering with benchmark results. 1489 Default value is 0 (Disabled). 1490 1491GIC Errata Workarounds 1492---------------------- 1493- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1494 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1495 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1496 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1497 then this flag is enabled; otherwise, it is 0 (Disabled). 1498 1499-------------- 1500 1501*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1502 1503.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1504.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1505.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1506.. _CVE-2024-5660: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-5660 1507.. _CVE-2024-7881: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-7881 1508.. _Cortex-A72 MPCore Software Developers Errata Notice: https://developer.arm.com/documentation/epm012079/latest 1509.. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015 1510.. _Arm DSU Software Developers Errata Notice: https://developer.arm.com/documentation/SDEN854652 1511