xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_private.h (revision a4defaefe65379554f464e9cf2b4f4d9818740aa)
1 /*
2  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3  * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SOCFPGA_PRIVATE_H
9 #define SOCFPGA_PRIVATE_H
10 
11 #include <errno.h>
12 
13 #define EMMC_DESC_SIZE		(1<<20)
14 
15 #define EMMC_INIT_PARAMS(base, clk)			\
16 	{	.bus_width = MMC_BUS_WIDTH_4,		\
17 		.clk_rate = (clk),			\
18 		.desc_base = (base),			\
19 		.desc_size = EMMC_DESC_SIZE,		\
20 		.flags = 0,				\
21 		.reg_base = SOCFPGA_MMC_REG_BASE	\
22 	}
23 
24 #undef memcpy_s
25 #define memcpy_s socfpga_memcpy_s
26 
27 typedef enum {
28 	BOOT_SOURCE_FPGA = 0,
29 	BOOT_SOURCE_SDMMC,
30 	BOOT_SOURCE_NAND,
31 	BOOT_SOURCE_QSPI,
32 	BOOT_SOURCE_RSVD
33 } boot_source_type;
34 
35 /*******************************************************************************
36  * Function and variable prototypes
37  ******************************************************************************/
38 
39 void enable_nonsecure_access(void);
40 
41 void socfpga_io_setup(int boot_source, unsigned long offset);
42 
43 void socfgpa_configure_mmu_el3(unsigned long total_base,
44 			unsigned long total_size,
45 			unsigned long ro_start,
46 			unsigned long ro_limit,
47 			unsigned long coh_start,
48 			unsigned long coh_limit);
49 
50 
51 void socfpga_configure_mmu_el1(unsigned long total_base,
52 			unsigned long total_size,
53 			unsigned long ro_start,
54 			unsigned long ro_limit,
55 			unsigned long coh_start,
56 			unsigned long coh_limit);
57 
58 void socfpga_delay_timer_init(void);
59 
60 void socfpga_gic_driver_init(void);
61 
62 void socfpga_delay_timer_init_args(void);
63 
64 uint32_t socfpga_get_spsr_for_bl32_entry(void);
65 
66 uint32_t socfpga_get_spsr_for_bl33_entry(void);
67 
68 unsigned long socfpga_get_ns_image_entrypoint(void);
69 
70 void plat_secondary_cpus_bl31_entry(void);
71 
72 void setup_clusterectlr_el1(void);
73 
74 int socfpga_memcpy_s(void *dst, size_t dsize, void *src, size_t ssize);
75 
76 /******************************************************************************
77  * Macro for generic poling function
78  *****************************************************************************/
79 
80 #define SOCFPGA_POLL(cond, max_count, delay, delay_fn, status)	\
81 	do {							\
82 		int __count = (max_count);			\
83 		(status) = -ETIMEDOUT;				\
84 		while ((!(cond)) && (__count-- > 0)) {		\
85 			delay_fn(delay);			\
86 		}						\
87 								\
88 		if ((cond)) {					\
89 			(status) = 0;				\
90 		}						\
91 	} while (0)
92 
93 #endif /* SOCFPGA_PRIVATE_H */
94