1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39# Enable CRC instructions via extension for ARMv8-A CPUs. 40# For ARMv8.1-A, and onwards CRC instructions are default enabled. 41ifeq (${ARM_ARCH_MAJOR},8) 42ifeq (${ARM_ARCH_MINOR},0) 43 ARM_ARCH_FEATURE := crc 44endif 45endif 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52 53ifeq (${ARCH}, aarch64) 54 55ifeq (${SPM_MM}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58 ENABLE_SME2_FOR_NS := 2 59else 60 ENABLE_SVE_FOR_NS := 0 61 ENABLE_SME_FOR_NS := 0 62 ENABLE_SME2_FOR_NS := 0 63endif 64endif 65 66 ENABLE_BRBE_FOR_NS := 2 67 ENABLE_TRBE_FOR_NS := 2 68 ENABLE_FEAT_D128 := 2 69 ENABLE_FEAT_FPMR := 2 70 ENABLE_FEAT_MOPS := 2 71 ENABLE_FEAT_FGWTE3 := 2 72 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 73 ENABLE_FEAT_CPA2 := 2 74 ENABLE_FEAT_UINJ := 2 75endif 76 77ENABLE_SYS_REG_TRACE_FOR_NS := 2 78ENABLE_FEAT_CSV2_2 := 2 79ENABLE_FEAT_CSV2_3 := 2 80ENABLE_FEAT_CLRBHB := 2 81ENABLE_FEAT_DEBUGV8P9 := 2 82ENABLE_FEAT_DIT := 2 83ENABLE_FEAT_PAN := 2 84ENABLE_FEAT_VHE := 2 85CTX_INCLUDE_NEVE_REGS := 2 86ENABLE_FEAT_SEL2 := 2 87ENABLE_TRF_FOR_NS := 2 88ENABLE_FEAT_ECV := 2 89ENABLE_FEAT_FGT := 2 90ENABLE_FEAT_FGT2 := 2 91ENABLE_FEAT_THE := 2 92ENABLE_FEAT_TCR2 := 2 93ENABLE_FEAT_S2PIE := 2 94ENABLE_FEAT_S1PIE := 2 95ENABLE_FEAT_S2POE := 2 96ENABLE_FEAT_S1POE := 2 97ENABLE_FEAT_SCTLR2 := 2 98ENABLE_FEAT_MTE2 := 2 99ENABLE_FEAT_LS64_ACCDATA := 2 100ENABLE_FEAT_AIE := 2 101ENABLE_FEAT_PFAR := 2 102ENABLE_FEAT_EBEP := 2 103 104ifeq (${ENABLE_RME},1) 105 ENABLE_FEAT_MEC := 2 106 RMMD_ENABLE_IDE_KEY_PROG := 1 107endif 108 109# The FVP platform depends on this macro to build with correct GIC driver. 110$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 111 112# Pass FVP_CLUSTER_COUNT to the build system. 113$(eval $(call add_define,FVP_CLUSTER_COUNT)) 114 115# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 116$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 117 118# Pass FVP_MAX_PE_PER_CPU to the build system. 119$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 120 121# Pass FVP_GICR_REGION_PROTECTION to the build system. 122$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 123 124# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 125$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 126 127ifeq (${DRTM_SUPPORT},1) 128MBOOT_EL_HASH_ALG := sha256 129endif 130 131# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 132# choose the CCI driver , else the CCN driver 133ifeq ($(FVP_CLUSTER_COUNT), 0) 134$(error "Incorrect cluster count specified for FVP port") 135else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 136FVP_INTERCONNECT_DRIVER := FVP_CCI 137else 138FVP_INTERCONNECT_DRIVER := FVP_CCN 139endif 140 141$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 142 143# Choose the GIC sources depending upon the how the FVP will be invoked 144ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 145USE_GIC_DRIVER := 3 146 147# The GIC model (GIC-600 or GIC-500) will be detected at runtime 148GICV3_SUPPORT_GIC600 := 1 149GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 150 151FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 152ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 153BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 154endif 155 156ifeq (${HW_ASSISTED_COHERENCY}, 0) 157FVP_DT_PREFIX := fvp-base-gicv3-psci 158else 159FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 160endif 161else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 162USE_GIC_DRIVER := 5 163ENABLE_FEAT_GCIE := 1 164BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 165FVP_DT_PREFIX := fvp-base-gicv5-psci 166ifneq ($(SPD),none) 167 $(error Error: GICv5 is not compatible with SPDs) 168endif 169ifeq ($(ENABLE_RME),1) 170 $(error Error: GICv5 is not compatible with RME) 171endif 172else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 173USE_GIC_DRIVER := 2 174 175# No GICv4 extension 176GIC_ENABLE_V4_EXTN := 0 177$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 178 179FVP_DT_PREFIX := fvp-base-gicv2-psci 180else 181$(error "Incorrect GIC driver chosen on FVP port") 182endif 183 184ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 185FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 186else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 187FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 188 plat/arm/common/arm_ccn.c 189else 190$(error "Incorrect CCN driver chosen on FVP port") 191endif 192 193FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 194 plat/arm/board/fvp/fvp_security.c \ 195 plat/arm/common/arm_tzc400.c 196 197 198PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 199 -Iinclude/lib/psa 200 201 202PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 203 204FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 205 206ifeq (${ARCH}, aarch64) 207 208# select a different set of CPU files, depending on whether we compile for 209# hardware assisted coherency cores or not 210ifeq (${HW_ASSISTED_COHERENCY}, 0) 211# Cores used without DSU 212 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 213 lib/cpus/aarch64/cortex_a53.S \ 214 lib/cpus/aarch64/cortex_a57.S \ 215 lib/cpus/aarch64/cortex_a72.S \ 216 lib/cpus/aarch64/cortex_a73.S 217else 218# Cores used with DSU only 219 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 220 # AArch64-only cores 221 # TODO: add all cores to the appropriate lists 222 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 223 lib/cpus/aarch64/cortex_a65ae.S \ 224 lib/cpus/aarch64/cortex_a76.S \ 225 lib/cpus/aarch64/cortex_a76ae.S \ 226 lib/cpus/aarch64/cortex_a77.S \ 227 lib/cpus/aarch64/cortex_a78.S \ 228 lib/cpus/aarch64/cortex_a78_ae.S \ 229 lib/cpus/aarch64/cortex_a78c.S \ 230 lib/cpus/aarch64/cortex_a710.S \ 231 lib/cpus/aarch64/cortex_a715.S \ 232 lib/cpus/aarch64/cortex_a720.S \ 233 lib/cpus/aarch64/cortex_a720_ae.S \ 234 lib/cpus/aarch64/neoverse_n1.S \ 235 lib/cpus/aarch64/neoverse_n2.S \ 236 lib/cpus/aarch64/neoverse_v1.S \ 237 lib/cpus/aarch64/neoverse_e1.S \ 238 lib/cpus/aarch64/cortex_x2.S \ 239 lib/cpus/aarch64/cortex_x4.S 240 endif 241 # AArch64/AArch32 cores 242 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 243 lib/cpus/aarch64/cortex_a75.S 244endif 245 246#Include all CPUs to build to support all-errata build. 247ifeq (${ENABLE_ERRATA_ALL},1) 248 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 249 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 250 lib/cpus/aarch64/cortex_a510.S \ 251 lib/cpus/aarch64/cortex_a520.S \ 252 lib/cpus/aarch64/cortex_a725.S \ 253 lib/cpus/aarch64/cortex_x1.S \ 254 lib/cpus/aarch64/cortex_x3.S \ 255 lib/cpus/aarch64/cortex_x925.S \ 256 lib/cpus/aarch64/neoverse_n3.S \ 257 lib/cpus/aarch64/neoverse_v2.S \ 258 lib/cpus/aarch64/neoverse_v3.S 259endif 260 261#Build AArch64-only CPUs with no FVP model yet. 262ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 263 ERRATA_SME_POWER_DOWN := 1 264 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 265 lib/cpus/aarch64/c1_nano.S \ 266 lib/cpus/aarch64/c1_ultra.S \ 267 lib/cpus/aarch64/c1_premium.S \ 268 lib/cpus/aarch64/canyon.S \ 269 lib/cpus/aarch64/caddo.S \ 270 lib/cpus/aarch64/veymont.S \ 271 lib/cpus/aarch64/dionysus.S \ 272 lib/cpus/aarch64/venom.S \ 273 lib/cpus/aarch64/lsc25_p_core.S \ 274 lib/cpus/aarch64/lsc25_e_core.S 275endif 276 277else 278FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 279 lib/cpus/aarch32/cortex_a57.S \ 280 lib/cpus/aarch32/cortex_a53.S 281endif 282 283BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 284 drivers/arm/sp805/sp805.c \ 285 drivers/delay_timer/delay_timer.c \ 286 drivers/io/io_semihosting.c \ 287 lib/semihosting/semihosting.c \ 288 lib/semihosting/${ARCH}/semihosting_call.S \ 289 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 290 plat/arm/board/fvp/fvp_bl1_setup.c \ 291 plat/arm/board/fvp/fvp_cpu_pwr.c \ 292 plat/arm/board/fvp/fvp_err.c \ 293 plat/arm/board/fvp/fvp_io_storage.c \ 294 plat/arm/board/fvp/fvp_topology.c \ 295 ${FVP_CPU_LIBS} \ 296 ${FVP_INTERCONNECT_SOURCES} 297 298ifeq (${USE_SP804_TIMER},1) 299BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 300else 301BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 302endif 303 304 305BL2_SOURCES += drivers/arm/sp805/sp805.c \ 306 drivers/io/io_semihosting.c \ 307 lib/utils/mem_region.c \ 308 lib/semihosting/semihosting.c \ 309 lib/semihosting/${ARCH}/semihosting_call.S \ 310 plat/arm/board/fvp/fvp_bl2_setup.c \ 311 plat/arm/board/fvp/fvp_err.c \ 312 plat/arm/board/fvp/fvp_io_storage.c \ 313 plat/arm/common/arm_nor_psci_mem_protect.c \ 314 ${FVP_SECURITY_SOURCES} 315 316 317ifeq (${COT_DESC_IN_DTB},1) 318BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 319endif 320 321ifeq (${ENABLE_RME},1) 322BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 323 plat/arm/board/fvp/fvp_cpu_pwr.c 324 325BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 326 plat/arm/board/fvp/fvp_realm_attest_key.c \ 327 plat/arm/board/fvp/fvp_el3_token_sign.c \ 328 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 329 plat/arm/common/plat_rmm_mem_carveout.c 330endif 331 332ifneq (${ENABLE_FEAT_RNG_TRAP},0) 333BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 334endif 335 336ifeq (${RESET_TO_BL2},1) 337BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 338 plat/arm/board/fvp/fvp_cpu_pwr.c \ 339 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 340 ${FVP_CPU_LIBS} \ 341 ${FVP_INTERCONNECT_SOURCES} 342endif 343 344ifeq (${USE_SP804_TIMER},1) 345BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 346endif 347 348BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 349 ${FVP_SECURITY_SOURCES} 350 351ifeq (${USE_SP804_TIMER},1) 352BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 353endif 354 355BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 356 drivers/arm/smmu/smmu_v3.c \ 357 drivers/delay_timer/delay_timer.c \ 358 drivers/cfi/v2m/v2m_flash.c \ 359 lib/utils/mem_region.c \ 360 plat/arm/board/fvp/fvp_bl31_setup.c \ 361 plat/arm/board/fvp/fvp_console.c \ 362 plat/arm/board/fvp/fvp_pm.c \ 363 plat/arm/board/fvp/fvp_topology.c \ 364 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 365 plat/arm/board/fvp/fvp_cpu_pwr.c \ 366 plat/arm/common/arm_nor_psci_mem_protect.c \ 367 ${FVP_CPU_LIBS} \ 368 ${FVP_INTERCONNECT_SOURCES} \ 369 ${FVP_SECURITY_SOURCES} 370 371# Support for fconf in BL31 372# Added separately from the above list for better readability 373ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 374BL31_SOURCES += lib/fconf/fconf.c \ 375 lib/fconf/fconf_dyn_cfg_getter.c \ 376 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 377 378BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 379 380ifeq (${SEC_INT_DESC_IN_FCONF},1) 381BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 382endif 383 384endif 385 386ifeq (${USE_SP804_TIMER},1) 387BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 388else 389BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 390endif 391 392# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 393FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 394 395FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 396$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 397HW_CONFIG := ${FVP_HW_CONFIG} 398 399HW_CONFIG_BASE ?= 0x82000000 400 401# Set default initrd base 128MiB offset of the default kernel address in FVP 402INITRD_BASE ?= 0x90000000 403 404# Kernel base address supports Linux kernels before v5.7 405# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 406ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 407 PRELOADED_BL33_BASE ?= 0x80080000 408 ifeq (${RESET_TO_BL31},1) 409 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 410 endif 411endif 412 413ifeq (${TRANSFER_LIST}, 0) 414FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 415 ${PLAT}_fw_config.dts \ 416 ${PLAT}_tb_fw_config.dts \ 417 ${PLAT}_soc_fw_config.dts \ 418 ${PLAT}_nt_fw_config.dts \ 419 ) 420 421FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 422FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 423FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 424FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 425 426ifeq (${SPD},tspd) 427FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 428FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 429 430# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 431$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 432endif 433 434# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 435$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 436# Add the NT_FW_CONFIG to FIP and specify the same to certtool 437$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 438endif 439 440ifeq (${SPD},spmd) 441 442ifeq ($(ARM_SPMC_MANIFEST_DTS),) 443ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 444endif 445 446FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 447FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 448 449# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 450$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 451endif 452 453# Add the HW_CONFIG to FIP and specify the same to certtool 454$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 455 456ifeq (${TRANSFER_LIST}, 1) 457 458ifeq ($(RESET_TO_BL31), 1) 459FW_HANDOFF_SIZE := 20000 460 461TRANSFER_LIST_DTB_OFFSET := 0x20 462$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 463endif 464 465# 466# To load SP_PKGs with TRANSFER_LIST, FVP_TB_FW_CONFIG is required. 467# 468ifeq (${BL2_ENABLE_SP_LOAD}, 1) 469 FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 470 ${PLAT}_tb_fw_config.dts \ 471 ) 472 473 FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 474 475 # Add the TB_FW_CONFIG to FIP and specify the same to certtool 476 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 477endif 478 479endif 480 481ifeq (${HOB_LIST}, 1) 482include lib/hob/hob.mk 483endif 484 485# Enable dynamic mitigation support by default 486DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 487 488ifneq (${ENABLE_FEAT_AMU},0) 489BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 490 lib/cpus/aarch64/cpuamu_helpers.S 491 492ifeq (${HW_ASSISTED_COHERENCY}, 1) 493BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 494 lib/cpus/aarch64/neoverse_n1_pubsub.c 495endif 496endif 497 498ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 499 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 500 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 501 endif 502 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 503 plat/arm/board/fvp/aarch64/fvp_ea.c 504endif 505 506ifneq (${ENABLE_STACK_PROTECTOR},0) 507PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 508endif 509 510# Enable the dynamic translation tables library. 511ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 512 ifeq (${ARCH},aarch32) 513 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 514 else # AArch64 515 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 516 endif 517endif 518 519ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 520 ifeq (${ARCH},aarch32) 521 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 522 else # AArch64 523 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 524 ifeq (${SPD},tspd) 525 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 526 endif 527 endif 528endif 529 530ifeq (${USE_DEBUGFS},1) 531 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 532endif 533 534# Add support for platform supplied linker script for BL31 build 535PLAT_EXTRA_LD_SCRIPT := 1 536 537ifneq (${RESET_TO_BL2}, 0) 538 override BL1_SOURCES = 539endif 540 541include plat/arm/board/common/board_common.mk 542include plat/arm/common/arm_common.mk 543 544ifeq (${MEASURED_BOOT},1) 545BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 546 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 547 lib/psa/measured_boot.c \ 548 common/measured_boot_helpers.c 549 550BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 551 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 552 lib/psa/measured_boot.c \ 553 common/measured_boot_helpers.c 554endif 555 556ifeq (${DRTM_SUPPORT}, 1) 557BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 558 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 559 plat/arm/board/fvp/fvp_drtm_err.c \ 560 plat/arm/board/fvp/fvp_drtm_measurement.c \ 561 plat/arm/board/fvp/fvp_drtm_stub.c \ 562 plat/arm/common/arm_dyn_cfg.c \ 563 plat/arm/board/fvp/fvp_err.c 564endif 565 566ifeq (${TRUSTED_BOARD_BOOT}, 1) 567BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 568BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 569 570# FVP being a development platform, enable capability to disable Authentication 571# dynamically if TRUSTED_BOARD_BOOT is set. 572DYN_DISABLE_AUTH := 1 573endif 574 575ifeq (${SPMC_AT_EL3}, 1) 576PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 577endif 578 579PSCI_OS_INIT_MODE := 1 580 581ifeq (${SPD},spmd) 582BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 583endif 584 585# Test specific macros, keep them at bottom of this file 586$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 587ifeq (${PLATFORM_TEST_EA_FFH}, 1) 588 ifeq (${FFH_SUPPORT}, 0) 589 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 590 endif 591 592endif 593 594PLATFORM_TEST_RAS_FFH ?= 0 595$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 596ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 597 ifeq (${ENABLE_FEAT_RAS}, 0) 598 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 599 endif 600 ifeq (${SDEI_SUPPORT}, 0) 601 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 602 endif 603 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 604 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 605 endif 606endif 607 608$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 609ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 610 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 611 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 612 endif 613 ifeq (${ENABLE_SPMD_LP}, 0) 614 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 615 endif 616 ifeq (${ENABLE_FEAT_RAS}, 0) 617 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 618 endif 619 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 620 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 621 endif 622endif 623 624ifeq (${ERRATA_ABI_SUPPORT}, 1) 625include plat/arm/board/fvp/fvp_cpu_errata.mk 626endif 627 628# Build macro necessary for running SPM tests on FVP platform 629$(eval $(call add_define,PLAT_TEST_SPM)) 630 631ifeq (${LFA_SUPPORT},1) 632BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 633endif 634 635# This is set to 1 by default when the firmware update 636# support is enabled. Since the BL2 image is not updatable 637ifeq ($(PSA_FWU_SUPPORT),1) 638 SEPARATE_BL2_FIP := 1 639endif 640 641ifeq (${TRANSFER_LIST}, 0) 642ifeq (${SEPARATE_BL2_FIP},1) 643$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 644$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 645else 646$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 647$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 648endif 649endif 650