1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31workaround_runtime_start c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 32 speculation_barrier 33workaround_runtime_end c1_pro, ERRATUM(3338470) 34 35check_erratum_ls c1_pro, ERRATUM(3338470), CPU_REV(0, 0) 36 37workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 38 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 39workaround_reset_end c1_pro, ERRATUM(3362007) 40 41check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 42 43workaround_reset_start c1_pro, ERRATUM(3619847), ERRATA_C1PRO_3619847 44 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(42) 45workaround_reset_end c1_pro, ERRATUM(3619847) 46 47check_erratum_ls c1_pro, ERRATUM(3619847), CPU_REV(0, 0) 48 49workaround_runtime_start c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 50#if ENABLE_SME_FOR_NS 51#if ENABLE_SME_FOR_NS == 2 52 is_feat_sme_present_asm x1 53 beq 1f 54#endif 55 56 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(57) 57 dsb sy 58 591: 60#endif 61workaround_runtime_end c1_pro, ERRATUM(3686597) 62 63check_erratum_ls c1_pro, ERRATUM(3686597), CPU_REV(1, 0) 64 65workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 66 mov x0, #5 67 msr C1_PRO_IMP_CPUPSELR_EL3, x0 68 isb 69 ldr x0, =0xd503329f 70 msr C1_PRO_IMP_CPUPOR_EL3, x0 71 ldr x0, =0xfffff3ff 72 msr C1_PRO_IMP_CPUPMR_EL3, x0 73 mov x1, #0 74 orr x1, x1, #1<<0 75 orr x1, x1, #3<<4 76 orr x1, x1, #0xf<<6 77 orr x1, x1, #1<<22 78 orr x1, x1, #1<<32 79 msr C1_PRO_IMP_CPUPCR_EL3, x1 80workaround_reset_end c1_pro, ERRATUM(3694158) 81 82check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 83 84workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 85 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 86workaround_reset_end c1_pro, ERRATUM(3706576) 87 88check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 89 90add_erratum_entry c1_pro, ERRATUM(3300099), ERRATA_C1PRO_3300099 91.global check_erratum_c1_pro_3300099 92check_erratum_ls c1_pro, ERRATUM(3300099), CPU_REV(1, 0) 93 94 /* ----------------------------------------------------------- 95 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 96 * workaround by disabling the affected prefetcher 97 * via IMP_CPUECTLR_EL1[49]. 98 * ----------------------------------------------------------- 99 */ 100workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 101 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 102 dsb sy 103workaround_reset_end c1_pro, CVE(2024, 7881) 104 105check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 106 107cpu_reset_func_start c1_pro 108 /* ---------------------------------------------------- 109 * Disable speculative loads 110 * ---------------------------------------------------- 111 */ 112 msr SSBS, xzr 113 apply_erratum c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 114 /* model bug: not cleared on reset */ 115 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 116 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 117 enable_mpmm 118cpu_reset_func_end c1_pro 119 120 /* ---------------------------------------------------- 121 * HW will do the cache maintenance while powering down 122 * ---------------------------------------------------- 123 */ 124func c1_pro_core_pwr_dwn 125 /* --------------------------------------------------- 126 * Flip CPU power down bit in power control register. 127 * It will be set on powerdown and cleared on wakeup 128 * --------------------------------------------------- 129 */ 130 apply_erratum c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 131 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 132 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 133 isb 134 signal_pabandon_handled 135 ret 136endfunc c1_pro_core_pwr_dwn 137 138 /* --------------------------------------------- 139 * This function provides Arm C1-Pro specific 140 * register information for crash reporting. 141 * It needs to return with x6 pointing to 142 * a list of register names in ascii and 143 * x8 - x15 having values of registers to be 144 * reported. 145 * --------------------------------------------- 146 */ 147.section .rodata.c1_pro_regs, "aS" 148c1_pro_regs: /* The ASCII list of register names to be reported */ 149 .asciz "imp_cpuectlr_el1", "" 150 151func c1_pro_cpu_reg_dump 152 adr x6, c1_pro_regs 153 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 154 ret 155endfunc c1_pro_cpu_reg_dump 156 157declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 158 c1_pro_reset_func, \ 159 c1_pro_core_pwr_dwn 160