1# 2# Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Making sure the corstone1000 platform type is specified 8ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) 9 $(error TARGET_PLATFORM must be fpga or fvp) 10endif 11 12ifeq ($(CORSTONE1000_CORTEX_A320), 1) 13CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a320.S 14$(eval $(call add_define,CORSTONE1000_CORTEX_A320)) 15GIC_ENABLE_V4_EXTN := 1 16GICV3_SUPPORT_GIC600 := 1 17else 18CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S 19endif 20 21# FEAT_CRC32 is impelemented in the armv8.0 core 22ARM_ARCH_FEATURE := crc 23 24PLAT_INCLUDES := -Iplat/arm/board/corstone1000/common/include \ 25 -Iplat/arm/board/corstone1000/include \ 26 -Iinclude/plat/arm/common \ 27 -Iinclude/plat/arm/css/common/aarch64 28 29override ARM_PLAT_PROVIDES_BL2_MEM_PARAMS := 1 30 31CORSTONE1000_FW_NVCTR_VAL := 255 32TFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} 33NTFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} 34 35override NEED_BL1 := no 36 37override NEED_BL2 := yes 38FIP_BL2_ARGS := tb-fw 39 40override NEED_BL2U := no 41override NEED_BL31 := yes 42NEED_BL32 ?= yes 43override NEED_BL33 := yes 44 45# Add CORSTONE1000_WITH_BL32 as a preprocessor define (-D option) 46ifeq (${NEED_BL32},yes) 47$(eval $(call add_define,CORSTONE1000_WITH_BL32)) 48endif 49 50ENABLE_MULTICORE := 0 51ifneq ($(filter ${TARGET_PLATFORM}, fvp),) 52ifeq (${ENABLE_MULTICORE},1) 53$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE)) 54endif 55endif 56 57ifeq ($(CORSTONE1000_CORTEX_A320), 1) 58USE_GIC_DRIVER := 3 59else 60USE_GIC_DRIVER := 2 61endif 62 63BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \ 64 plat/arm/board/corstone1000/common/corstone1000_err.c \ 65 plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \ 66 lib/utils/mem_region.c \ 67 lib/cpus/aarch64/cpu_helpers.S \ 68 plat/arm/board/corstone1000/common/corstone1000_helpers.S \ 69 plat/arm/board/corstone1000/common/corstone1000_plat.c \ 70 plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \ 71 ${CORSTONE1000_CPU_LIBS} \ 72 73 74BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 75 lib/utils/mem_region.c \ 76 plat/arm/board/corstone1000/common/corstone1000_helpers.S \ 77 plat/arm/board/corstone1000/common/corstone1000_topology.c \ 78 plat/arm/board/corstone1000/common/corstone1000_security.c \ 79 plat/arm/board/corstone1000/common/corstone1000_plat.c \ 80 plat/arm/board/corstone1000/common/corstone1000_pm.c \ 81 plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c \ 82 ${CORSTONE1000_CPU_LIBS} 83 84ifneq (${ENABLE_STACK_PROTECTOR},0) 85 ifneq (${ENABLE_STACK_PROTECTOR},none) 86 CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c 87 BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} 88 BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} 89 endif 90endif 91 92FDT_SOURCES += plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts 93CORSTONE1000_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb 94 95# Add the SPMC manifest to FIP and specify the same to certtool 96$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG})) 97 98# Adding TARGET_PLATFORM as a GCC define (-D option) 99$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) 100 101# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option) 102$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL)) 103 104include plat/arm/common/arm_common.mk 105include plat/arm/board/common/board_common.mk 106