1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_neoverse_v2_3701771 26 27cpu_reset_prologue neoverse_v2 28 29workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 30 /* Disable retention control for WFI and WFE. */ 31 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 32 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 33 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 34 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 35 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 36 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 37workaround_reset_end neoverse_v2, ERRATUM(2618597) 38 39/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 40add_erratum_entry neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 41 42check_erratum_ls neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), CPU_REV(0, 0) 43 44check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 45 46workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 47 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 48 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 49workaround_reset_end neoverse_v2, ERRATUM(2662553) 50 51check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 52 53workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 54 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 55workaround_reset_end neoverse_v2, ERRATUM(2719105) 56 57check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 58 59workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 60 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 61 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 62workaround_reset_end neoverse_v2, ERRATUM(2743011) 63 64check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 65 66workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 67 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 68workaround_reset_end neoverse_v2, ERRATUM(2779510) 69 70check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 71 72workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 73 /* dsb before isb of power down sequence */ 74 dsb sy 75workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 76 77check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 78 79workaround_reset_start neoverse_v2, ERRATUM(3442699), ERRATA_V2_3442699 80 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, NEOVERSE_V2_CPUACTLR_EL1_BIT_36 81workaround_reset_end neoverse_v2, ERRATUM(3442699) 82 83check_erratum_ls neoverse_v2, ERRATUM(3442699), CPU_REV(0, 2) 84 85add_erratum_entry neoverse_v2, ERRATUM(3701771), ERRATA_V2_3701771 86 87check_erratum_ls neoverse_v2, ERRATUM(3701771), CPU_REV(0, 2) 88 89workaround_reset_start neoverse_v2, ERRATUM(3841324), ERRATA_V2_3841324 90 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 91workaround_reset_end neoverse_v2, ERRATUM(3841324) 92 93check_erratum_ls neoverse_v2, ERRATUM(3841324), CPU_REV(0, 1) 94 95workaround_reset_start neoverse_v2, ERRATUM(3888126), ERRATA_V2_3888126 96 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, BIT(22) 97workaround_reset_end neoverse_v2, ERRATUM(3888126) 98 99check_erratum_ls neoverse_v2, ERRATUM(3888126), CPU_REV(0, 2) 100 101workaround_reset_start neoverse_v2, ERRATUM(4302968), ERRATA_V2_4302968 102 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, BIT(50) 103workaround_reset_end neoverse_v2, ERRATUM(4302968) 104 105check_erratum_ls neoverse_v2, ERRATUM(4302968), CPU_REV(0, 2) 106 107workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 108#if IMAGE_BL31 109 /* 110 * The Neoverse-V2 generic vectors are overridden to apply errata 111 * mitigation on exception entry from lower ELs. 112 */ 113 override_vector_table wa_cve_vbar_neoverse_v2 114#endif /* IMAGE_BL31 */ 115workaround_reset_end neoverse_v2, CVE(2022,23960) 116 117check_erratum_ls neoverse_v2, CVE(2022, 23960), CPU_REV(0, 0) 118 119/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 120workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 121 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 122workaround_reset_end neoverse_v2, CVE(2024, 5660) 123 124check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 125 126#if WORKAROUND_CVE_2022_23960 127 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 128#endif /* WORKAROUND_CVE_2022_23960 */ 129 130 /* ---------------------------------------------------------------- 131 * CVE-2024-7881 is mitigated for Neoverse-V2 using erratum 3696445 132 * workaround by disabling the affected prefetcher setting 133 * CPUACTLR6_EL1[41]. 134 * ---------------------------------------------------------------- 135 */ 136workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 137 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 138workaround_reset_end neoverse_v2, CVE(2024, 7881) 139 140check_erratum_ls neoverse_v2, CVE(2024, 7881), CPU_REV(0, 2) 141 142 /* ---------------------------------------------------- 143 * HW will do the cache maintenance while powering down 144 * ---------------------------------------------------- 145 */ 146func neoverse_v2_core_pwr_dwn 147 /* --------------------------------------------------- 148 * Enable CPU power down bit in power control register 149 * --------------------------------------------------- 150 */ 151 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 152 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 153 154 isb 155 ret 156endfunc neoverse_v2_core_pwr_dwn 157 158cpu_reset_func_start neoverse_v2 159 /* Disable speculative loads */ 160 msr SSBS, xzr 161 162#if NEOVERSE_Vx_EXTERNAL_LLC 163 /* Some systems may have External LLC, core needs to be made aware */ 164 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 165#endif 166cpu_reset_func_end neoverse_v2 167 168 /* --------------------------------------------- 169 * This function provides Neoverse V2- 170 * specific register information for crash 171 * reporting. It needs to return with x6 172 * pointing to a list of register names in ascii 173 * and x8 - x15 having values of registers to be 174 * reported. 175 * --------------------------------------------- 176 */ 177.section .rodata.neoverse_v2_regs, "aS" 178neoverse_v2_regs: /* The ascii list of register names to be reported */ 179 .asciz "cpuectlr_el1", "" 180 181func neoverse_v2_cpu_reg_dump 182 adr x6, neoverse_v2_regs 183 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 184 ret 185endfunc neoverse_v2_cpu_reg_dump 186 187declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 188 neoverse_v2_reset_func, \ 189 neoverse_v2_core_pwr_dwn 190