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Searched refs:HAL_DMD_RIU_WriteByte (Results 1 – 25 of 146) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_ATSC.c286 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
287 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
288 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
289 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
293 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
294 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
295 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x10, u8Data); in _MBX_WriteReg()
296 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x01); in _MBX_WriteReg()
299 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
300 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
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H A DhalDMD_INTERN_DTMB.c237 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
238 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
239 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
240 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
242 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
243 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
267 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
268 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
269 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
271 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_ReadReg()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_ATSC.c259 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
260 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
261 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
262 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
266 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
267 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
268 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x10, u8Data); in _MBX_WriteReg()
269 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x01); in _MBX_WriteReg()
272 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
273 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
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H A DhalDMD_INTERN_DTMB.c200 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
201 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
202 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
203 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
205 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
206 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
230 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
231 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
232 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
234 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_ReadReg()
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H A DhalDMD_INTERN_DVBC.c438 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
461 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
469 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBC_Cmd_Packet_Send()
471 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
495 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
532 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBC_SoftStop()
534 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
535 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
550 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBC_SoftStop()
572 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBC_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_ATSC.c259 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
260 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
261 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
262 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
266 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
267 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
268 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x10, u8Data); in _MBX_WriteReg()
269 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x01); in _MBX_WriteReg()
272 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
273 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
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H A DhalDMD_INTERN_DTMB.c197 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
198 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
199 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
200 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
202 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
203 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
227 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
228 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
229 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
231 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_ReadReg()
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H A DhalDMD_INTERN_DVBC.c427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
450 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
458 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBC_Cmd_Packet_Send()
460 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
484 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
521 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBC_SoftStop()
523 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
524 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
539 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBC_SoftStop()
562 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBC_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_ATSC.c259 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
260 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
261 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
262 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
266 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
267 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
268 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x10, u8Data); in _MBX_WriteReg()
269 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x01); in _MBX_WriteReg()
272 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
273 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
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H A DhalDMD_INTERN_DTMB.c240 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
241 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
242 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
243 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
245 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
246 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
270 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
271 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
272 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
274 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_ReadReg()
[all …]
H A DhalDMD_INTERN_ISDBT.c186 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_WriteReg()
187 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_WriteReg()
188 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data); in _MBX_WriteReg()
189 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01); in _MBX_WriteReg()
191 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_WriteReg()
192 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-a… in _MBX_WriteReg()
216 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff)); in _MBX_ReadReg()
217 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8)); in _MBX_ReadReg()
218 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02); in _MBX_ReadReg()
220 …HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // asse… in _MBX_ReadReg()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT2.c372 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT2_SoftStop()
374 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT2_SoftStop()
375 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT2_SoftStop()
387 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT2_SoftStop()
401 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN in INTERN_DVBT2_SoftReset()
501 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT2_Reset()
503 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL in INTERN_DVBT2_Reset()
505 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); in INTERN_DVBT2_Reset()
509 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); in INTERN_DVBT2_Reset()
715 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU in INTERN_DVBT2_LoadDSPCode()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBC.c426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
457 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBC_Cmd_Packet_Send()
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
520 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBC_SoftStop()
522 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
523 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
538 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBC_SoftStop()
561 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBC_Reset()
[all …]
H A DhalDMD_INTERN_DVBT2.c383 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT2_SoftStop()
385 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT2_SoftStop()
386 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT2_SoftStop()
398 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT2_SoftStop()
412 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN in INTERN_DVBT2_SoftReset()
512 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT2_Reset()
514 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL in INTERN_DVBT2_Reset()
516 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); in INTERN_DVBT2_Reset()
520 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); in INTERN_DVBT2_Reset()
726 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU in INTERN_DVBT2_LoadDSPCode()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c454 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
456 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
457 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
472 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
494 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset in INTERN_DVBT_Reset()
495 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset DMD_MCU in INTERN_DVBT_Reset()
498 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL in INTERN_DVBT_Reset()
500 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); in INTERN_DVBT_Reset()
504 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); in INTERN_DVBT_Reset()
564 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset in INTERN_DVBT_LoadDSPCode()
[all …]
H A DhalDMD_INTERN_DVBT2.c397 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT2_SoftStop()
399 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT2_SoftStop()
400 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT2_SoftStop()
412 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT2_SoftStop()
426 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN in INTERN_DVBT2_SoftReset()
526 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x02); // reset RIU remapping reset in INTERN_DVBT2_Reset()
527 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x03); // reset DMD_MCU in INTERN_DVBT2_Reset()
529 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL in INTERN_DVBT2_Reset()
531 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); in INTERN_DVBT2_Reset()
535 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); in INTERN_DVBT2_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBC.c566 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBC_Cmd_Packet_Send()
589 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBC_Cmd_Packet_Send()
597 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBC_Cmd_Packet_Send()
599 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBC_Cmd_Packet_Send()
623 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBC_Cmd_Packet_Send()
660 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBC_SoftStop()
662 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
663 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBC_SoftStop()
678 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBC_SoftStop()
757 HAL_DMD_RIU_WriteByte(0x101e39,0x00); in INTERN_DVBC_Exit()
[all …]
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT.c458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val); in INTERN_DVBT_Cmd_Packet_Send()
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00); in INTERN_DVBT_Cmd_Packet_Send()
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]); in INTERN_DVBT_Cmd_Packet_Send()
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ); in INTERN_DVBT_Cmd_Packet_Send()
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END); in INTERN_DVBT_Cmd_Packet_Send()
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode in INTERN_DVBT_SoftStop()
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
555 … HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51 in INTERN_DVBT_SoftStop()
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear in INTERN_DVBT_SoftStop()
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU in INTERN_DVBT_Reset()
[all …]

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