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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107
108 #include "MsCommon.h"
109 #include "MsIRQ.h"
110 #include "MsOS.h"
111 //#include "apiPWS.h"
112
113 #include "MsTypes.h"
114 #include "drvBDMA.h"
115 //#include "drvIIC.h"
116 //#include "msAPI_Tuner.h"
117 //#include "msAPI_MIU.h"
118 //#include "BinInfo.h"
119 //#include "halVif.h"
120 #include "drvDMD_INTERN_DVBC.h"
121 #include "halDMD_INTERN_DVBC.h"
122 #include "halDMD_INTERN_common.h"
123 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
124 #include "InfoBlock.h"
125 #endif
126 #include "drvMMIO.h"
127 //#include "TDAG4D01A_SSI_DVBT.c"
128 #include "drvDMD_VD_MBX.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
133
134 #define TDE_REG_BASE 0x2400UL
135 #define INNC_REG_BASE 0x2600UL
136 #define EQE_REG_BASE 0x2c00UL
137 #define EQE2_REG_BASE 0x2d00UL
138
139 #ifdef MS_DEBUG
140 #define DBG_INTERN_DVBC(x) x
141 #define DBG_GET_SIGNAL_DVBC(x) x
142 #define DBG_INTERN_DVBC_TIME(x) x
143 #define DBG_INTERN_DVBC_LOCK(x) x
144 #define INTERN_DVBC_INTERNAL_DEBUG 0
145 #else
146 #define DBG_INTERN_DVBC(x) //x
147 #define DBG_GET_SIGNAL_DVBC(x) //x
148 #define DBG_INTERN_DVBC_TIME(x) //x
149 #define DBG_INTERN_DVBC_LOCK(x) //x
150 #define INTERN_DVBC_INTERNAL_DEBUG 0
151 #endif
152 #define DBG_DUMP_LOAD_DSP_TIME 0
153
154
155 //#define SIGNAL_LEVEL_OFFSET 0.00f
156 //#define TAKEOVERPOINT -60.0f
157 //#define TAKEOVERRANGE 0.5f
158 //#define LOG10_OFFSET -0.21f
159 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
160 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
161
162 #define TUNER_IF 36167
163
164 #define TS_SER_C 0x00 //0: parallel 1:serial
165
166 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
167 #define TS_INV_C 0x01
168 #else
169 #define TS_INV_C 0x00
170 #endif
171
172 #define DVBC_FS 45474 //24000
173 #define CFG_ZIF 0x00 //For ZIF ,FC=0
174 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
175 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
176 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
177 #define FS_L_C (DVBC_FS&0xFF)
178 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
179 #define IQ_SWAP_C 0x00
180 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
181 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
182 // Symbol Rate: 6875 = 0x1ADB
183 // Symbol Rate: 6900 = 0x1AF4
184 // Symbol Rate: 7000 = 0x1B58
185 // Symbol Rate: 4000 = 0x0FA0
186 // Symbol Rate: 6125 = 0x17ED
187 #define SR0_H 0x1A
188 #define SR0_L 0xF4 //6900
189 #define SR1_H 0x1B
190 #define SR1_L 0x58 //7000
191 #define SR2_H 0x17
192 #define SR2_L 0xED //6125
193 #define SR3_H 0x0F
194 #define SR3_L 0xA0 //4000
195 #define SR4_H 0x1B
196 #define SR4_L 0x26 //6950
197 #define SR5_H 0x1A //0xDB
198 #define SR5_L 0xDB //0x1A //6875
199 #define SR6_H 0x1C
200 #define SR6_L 0x20 //7200
201 #define SR7_H 0x1C
202 #define SR7_L 0x52 //7250
203 #define SR8_H 0x0B
204 #define SR8_L 0xB8 //3000
205 #define SR9_H 0x03
206 #define SR9_L 0xE8 //1000
207 #define SR10_H 0x07
208 #define SR10_L 0xD0 //2000
209 #define SR11_H 0x00
210 #define SR11_L 0x00 //0000
211
212
213 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
214
215 // SAR dependent
216 #define NO_SIGNAL_TH_A 0xA3
217 // Tuner dependent
218 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
219 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
220 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
221 #define NO_SIGNAL_TH_C_H 0xff //0x00
222 #define DAGC1_REF 0x70
223 #define DAGC2_REF 0x30
224 #define AGC_REF_L 0x00
225 #define AGC_REF_H 0x06
226
227 #define INTERN_AUTO_SR_C 1
228 #define INTERN_AUTO_QAM_C 1
229
230 #define ATV_DET_EN 1
231
232 #if 0
233 MS_U8 INTERN_DVBC_DSPREG[] =
234 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
235 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
236 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
237 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
238 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
239 };
240 #else
241 MS_U8 INTERN_DVBC_DSPREG[] =
242 {
243 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
244 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
245 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
246 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
247 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
248 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
249 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
250 };
251 #endif
252 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
253
254 //-----------------------------------------------------------------------
255 /****************************************************************
256 *Local Variables *
257 ****************************************************************/
258
259 //static MS_BOOL TPSLock = 0;
260 static MS_U32 u32ChkScanTimeStartDVBC = 0;
261 static MS_U8 g_dvbc_lock = 0;
262
263 //Global Variables
264 S_CMDPKTREG gsCmdPacketDVBC;
265 //MS_U8 gCalIdacCh0, gCalIdacCh1;
266 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
267 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
268 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
269 MS_U8 INTERN_DVBC_table[] = {
270 #include "fwDMD_INTERN_DVBC.dat"
271 };
272
273 #endif
274
275 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
276 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
277 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
278 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
279 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW);
280 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
281 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
282 //MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
283
284 #if (INTERN_DVBC_INTERNAL_DEBUG)
285 void INTERN_DVBC_info(void);
286 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
287 #endif
288
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)289 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
290 {
291 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
292 MS_U8 status = TRUE;
293 MS_U16 u16DspAddr = 0;
294
295 DBG_INTERN_DVBC(printf("INTERN_DVBC_DSPReg_Init\n"));
296
297 #if 0//def MS_DEBUG
298 {
299 MS_U8 u8buffer[256];
300 printf("INTERN_DVBC_DSPReg_Init Reset\n");
301 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
302 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
303
304 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
305 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
306 printf("INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
307 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
308 printf("%x ", u8buffer[idx]);
309 printf("\n");
310
311 printf("INTERN_DVBC_DSPReg_Init Value\n");
312 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
313 printf("%x ", INTERN_DVBC_DSPREG[idx]);
314 printf("\n");
315 }
316 #endif
317
318 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
319 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
320
321 // readback to confirm.
322 #ifdef MS_DEBUG
323 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
324 {
325 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
326 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
327 {
328 printf("[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
329 }
330 }
331 #endif
332
333 if (u8DVBC_DSPReg != NULL)
334 {
335 if (1 == u8DVBC_DSPReg[0])
336 {
337 u8DVBC_DSPReg+=2;
338 for (idx = 0; idx<u8Size; idx++)
339 {
340 u16DspAddr = *u8DVBC_DSPReg;
341 u8DVBC_DSPReg++;
342 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
343 u8DVBC_DSPReg++;
344 u8Mask = *u8DVBC_DSPReg;
345 u8DVBC_DSPReg++;
346 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
347 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
348 u8DVBC_DSPReg++;
349 DBG_INTERN_DVBC(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
350 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
351 }
352 }
353 else
354 {
355 printf("FATAL: parameter version incorrect\n");
356 }
357 }
358
359 #if 0//def MS_DEBUG
360 {
361 MS_U8 u8buffer[256];
362 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
363 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
364 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
365 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
366 printf("%x ", u8buffer[idx]);
367 printf("\n");
368 }
369 #endif
370
371 #if 0//def MS_DEBUG
372 {
373 MS_U8 u8buffer[256];
374 for (idx = 0; idx<128; idx++)
375 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
376 printf("INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
377 for (idx = 0; idx<128; idx++)
378 {
379 printf("%x ", u8buffer[idx]);
380 if ((idx & 0xF) == 0xF) printf("\n");
381 }
382 printf("\n");
383 }
384 #endif
385 return status;
386 }
387
388 /***********************************************************************************
389 Subject: Command Packet Interface
390 Function: INTERN_DVBC_Cmd_Packet_Send
391 Parmeter:
392 Return: MS_BOOL
393 Remark:
394 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)395 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
396 {
397 MS_U8 status = true, indx;
398 MS_U8 reg_val, timeout = 0;
399 return TRUE;
400 // ==== Command Phase ===================
401 DBG_INTERN_DVBC(printf("--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
402 pCmdPacket->param[0],pCmdPacket->param[1],
403 pCmdPacket->param[2],pCmdPacket->param[3],
404 pCmdPacket->param[4],pCmdPacket->param[5] ));
405
406 // wait _BIT_END clear
407 do
408 {
409 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
410 if((reg_val & _BIT_END) != _BIT_END)
411 {
412 break;
413 }
414 MsOS_DelayTask(5);
415 if (timeout > 200)
416 {
417 printf("---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
418 return false;
419 }
420 timeout++;
421 } while (1);
422
423 // set cmd_3:0 and _BIT_START
424 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
425 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
426 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
427
428
429 //DBG_INTERN_DVBT(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
430 // wait _BIT_START clear
431 do
432 {
433 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
434 if((reg_val & _BIT_START) != _BIT_START)
435 {
436 break;
437 }
438 MsOS_DelayTask(10);
439 if (timeout > 200)
440 {
441 printf("---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
442 return false;
443 }
444 timeout++;
445 } while (1);
446
447 // ==== Data Phase ======================
448
449 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
450
451 for (indx = 0; indx < param_cnt; indx++)
452 {
453 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
454 //DBG_INTERN_DVBT(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
455
456 // set param[indx] and _BIT_DRQ
457 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
458 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
459 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
460
461 // wait _BIT_DRQ clear
462 do
463 {
464 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
465 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
466 {
467 break;
468 }
469 MsOS_DelayTask(5);
470 if (timeout > 200)
471 {
472 printf("---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
473 return false;
474 }
475 timeout++;
476 } while (1);
477 }
478
479 // ==== End Phase =======================
480
481 // set _BIT_END to finish command
482 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
483 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
484 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
485 return status;
486 }
487
488
489 /***********************************************************************************
490 Subject: Command Packet Interface
491 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
492 Parmeter:
493 Return: MS_BOOL
494 Remark:
495 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)496 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
497 {
498 return TRUE;
499 }
500
501 /***********************************************************************************
502 Subject: SoftStop
503 Function: INTERN_DVBC_SoftStop
504 Parmeter:
505 Return: MS_BOOL
506 Remark:
507 ************************************************************************************/
508
INTERN_DVBC_SoftStop(void)509 MS_BOOL INTERN_DVBC_SoftStop ( void )
510 {
511 #if 1
512 MS_U16 u8WaitCnt=0;
513
514 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
515 {
516 printf(">> MB Busy!\n");
517 return FALSE;
518 }
519
520 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
521
522 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
523 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
524
525 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
526 {
527 #if TEST_EMBEDED_DEMOD
528 MsOS_DelayTask(1); // << Ken 20090629
529 #endif
530 if (u8WaitCnt++ >= 0xFF)
531 {
532 printf(">> DVBT SoftStop Fail!\n");
533 return FALSE;
534 }
535 }
536
537 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
538 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
539 #endif
540 return TRUE;
541 }
542
543
544 /***********************************************************************************
545 Subject: Reset
546 Function: INTERN_DVBC_Reset
547 Parmeter:
548 Return: MS_BOOL
549 Remark:
550 ************************************************************************************/
551 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)552 MS_BOOL INTERN_DVBC_Reset ( void )
553 {
554 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_reset\n"));
555
556 //DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
557
558 INTERN_DVBC_SoftStop();
559
560
561 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
562 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
563 MsOS_DelayTask(5);
564 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
565 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
566 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
567 MsOS_DelayTask(5);
568
569 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
571
572 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
573 g_dvbc_lock = 0;
574
575 return TRUE;
576 }
577
578 /***********************************************************************************
579 Subject: Exit
580 Function: INTERN_DVBC_Exit
581 Parmeter:
582 Return: MS_BOOL
583 Remark:
584 ************************************************************************************/
INTERN_DVBC_Exit(void)585 MS_BOOL INTERN_DVBC_Exit ( void )
586 {
587
588 INTERN_DVBC_SoftStop();
589
590
591 //diable clk gen
592 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
593 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
594
595 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
596 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
597
598 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
599 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
600
601 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
602 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
603
604 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
605 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
606
607 HAL_DMD_RIU_WriteByte(0x103312, 0x05); // dvbt_t:0x0000, dvb_c: 0x0004
608 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
609
610 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
611 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
612
613 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
614 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
615
616 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
617 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
618
619 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
620 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
621
622 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
623
624 return TRUE;
625 }
626
627 /***********************************************************************************
628 Subject: Load DSP code to chip
629 Function: INTERN_DVBC_LoadDSPCode
630 Parmeter:
631 Return: MS_BOOL
632 Remark:
633 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)634 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
635 {
636 MS_U8 udata = 0x00;
637 MS_U16 i;
638 MS_U16 fail_cnt=0;
639
640 #if (DBG_DUMP_LOAD_DSP_TIME==1)
641 MS_U32 u32Time;
642 #endif
643
644
645 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
646 BININFO BinInfo;
647 MS_BOOL bResult;
648 MS_U32 u32GEAddr;
649 MS_U8 Data;
650 MS_S8 op;
651 MS_U32 srcaddr;
652 MS_U32 len;
653 MS_U32 SizeBy4K;
654 MS_U16 u16Counter=0;
655 MS_U8 *pU8Data;
656 #endif
657
658 #if 0
659 if(HAL_DMD_RIU_ReadByte(0x101E3E))
660 {
661 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
662 return FALSE;
663 }
664 #endif
665
666 // MDrv_Sys_DisableWatchDog();
667
668
669 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
670 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
671 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
672 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
673 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
674 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
675
676 //// Load code thru VDMCU_IF ////
677 DBG_INTERN_DVBC(printf(">Load Code.....\n"));
678 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
679 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
680 {
681 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
682 }
683 #else
684 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
685 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
686 if ( bResult != PASS )
687 {
688 return FALSE;
689 }
690 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
691
692 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
693 InfoBlock_Flash_2_Checking_Start(&BinInfo);
694 #endif
695
696 #if OBA2
697 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
698 #else
699 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
700 #endif
701
702 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
703 InfoBlock_Flash_2_Checking_End(&BinInfo);
704 #endif
705
706 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
707 SizeBy4K=BinInfo.B_Len/0x1000;
708 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
709
710 #if (DBG_DUMP_LOAD_DSP_TIME==1)
711 u32Time = msAPI_Timer_GetTime0();
712 #endif
713
714 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
715
716 for (i=0;i<=SizeBy4K;i++)
717 {
718 if(i==SizeBy4K)
719 len=BinInfo.B_Len%0x1000;
720 else
721 len=0x1000;
722
723 srcaddr = u32GEAddr+(0x1000*i);
724 //printf("\t i = %08X\n", i);
725 //printf("\t len = %08X\n", len);
726 op = 1;
727 u16Counter = 0 ;
728 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
729 while(len--)
730 {
731 u16Counter ++ ;
732 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
733 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
734 #if OBA2
735 pU8Data = (MS_U8 *)(srcaddr);
736 #else
737 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
738 #endif
739 Data = *pU8Data;
740
741 #if 0
742 if(u16Counter < 0x100)
743 printf("0x%bx,", Data);
744 #endif
745 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
746
747 srcaddr += op;
748 }
749 // printf("\n\n\n");
750 }
751
752 #if (DBG_DUMP_LOAD_DSP_TIME==1)
753 printf("------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
754 #endif
755
756 #endif
757
758 //// Content verification ////
759 DBG_INTERN_DVBC(printf(">Verify Code...\n"));
760
761 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
762 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
763
764 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
765 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
766 {
767 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
768 if (udata != INTERN_DVBC_table[i])
769 {
770 printf(">fail add = 0x%x\n", i);
771 printf(">code = 0x%x\n", INTERN_DVBC_table[i]);
772 printf(">data = 0x%x\n", udata);
773
774 if (fail_cnt > 10)
775 {
776 printf(">DVB-C DSP Loadcode fail!");
777 return false;
778 }
779 fail_cnt++;
780 }
781 }
782 #else
783 for (i=0;i<=SizeBy4K;i++)
784 {
785 if(i==SizeBy4K)
786 len=BinInfo.B_Len%0x1000;
787 else
788 len=0x1000;
789
790 srcaddr = u32GEAddr+(0x1000*i);
791 //printf("\t i = %08LX\n", i);
792 //printf("\t len = %08LX\n", len);
793 op = 1;
794 u16Counter = 0 ;
795 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
796 while(len--)
797 {
798 u16Counter ++ ;
799 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
800 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
801 #if OBA2
802 pU8Data = (MS_U8 *)(srcaddr);
803 #else
804 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
805 #endif
806 Data = *pU8Data;
807
808 #if 0
809 if(u16Counter < 0x100)
810 printf("0x%bx,", Data);
811 #endif
812 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
813 if (udata != Data)
814 {
815 printf(">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
816 printf(">code = 0x%x\n", Data);
817 printf(">data = 0x%x\n", udata);
818
819 if (fail_cnt++ > 10)
820 {
821 printf(">DVB-C DSP Loadcode fail!");
822 return false;
823 }
824 }
825
826 srcaddr += op;
827 }
828 // printf("\n\n\n");
829 }
830 #endif
831
832 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
833 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
834 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
835 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
836
837 DBG_INTERN_DVBC(printf(">DSP Loadcode done."));
838 //while(load_data_variable);
839 #if 0
840 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
841 INTERN_DVBC_Active(ENABLE);
842 while(1);
843 #endif
844 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
845
846 return TRUE;
847 }
848
849 /***********************************************************************************
850 Subject: DVB-T CLKGEN initialized function
851 Function: INTERN_DVBC_Power_On_Initialization
852 Parmeter:
853 Return: MS_BOOL
854 Remark:
855 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)856 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
857 {
858 MS_U8 temp_val;
859 //move to drvSYS MS_U8 tmp;
860 //MS_U8 udatatemp = 0x00;
861 /************************************************************************
862 * T10 U01
863 * This bit0 is mux for DMD muc and HK,
864 * bit0: 0:HK can rw bank 0x1120, 1: DMD mcu can rw bank 0x1120;
865 ************************************************************************/
866 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
867 // HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
868
869 // Release vivaldi2mi_bridge reset
870 // [0] reg_vivaldi2mi_bridge_rst
871 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
872 // `RIU_W( (`RIUBASE_DMD_TOP>>1)+7'h47, 2'b01, 16'h0000);
873 // HAL_DMD_RIU_WriteByte(0x11208E, (HAL_DMD_RIU_ReadByte(0x11208E)&(~(BIT(0)))));
874
875 // CLK_DMDMCU clock setting
876 // [0] disable clock
877 // [1] invert clock
878 // [4:2]
879 // 000:170 MHz(MPLL_DIV_BUf)
880 // 001:160MHz
881 // 010:144MHz
882 // 011:123MHz
883 // 100:108MHz
884 // 101:mem_clcok
885 // 110:mem_clock div 2
886 // 111:select XTAL
887 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
888 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
889
890 // set parallet ts clock
891 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
892 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
893 // wriu 0x103301 0x06
894 // wriu 0x103300 0x19
895
896
897 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
898 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
899 temp_val|=0x07;
900 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
901
902 HAL_DMD_RIU_WriteByte(0x103300,0x13);
903
904 // enable atsc, DVBTC ts clock
905 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
906 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
907 // wriu 0x103309 0x00
908 // wriu 0x103308 0x00
909
910 HAL_DMD_RIU_WriteByte(0x103309,0x00);
911 HAL_DMD_RIU_WriteByte(0x103308,0x00);
912
913 // enable dvbc adc clock
914 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
915 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
916 // wriu 0x103315 0x00
917 // wriu 0x103314 0x00
918
919 HAL_DMD_RIU_WriteByte(0x103315,0x00);
920 HAL_DMD_RIU_WriteByte(0x103314,0x00);
921
922 // Reset TS divider
923 HAL_DMD_RIU_WriteByte(0x103302,0x01);
924 HAL_DMD_RIU_WriteByte(0x103302,0x00);
925
926
927 // Select MPLLDIV17
928 // [0] : reg_atsc_adc_sel_mplldiv2
929 // [1] : reg_atsc_eq_sel_mplldiv2
930 // [2] : reg_eq25_sel_mplldiv3
931 // [3] : reg_p4_cfo_sel_eq25
932 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0007);
933 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b01, 16'h0007);
934 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
935 HAL_DMD_RIU_WriteByte(0x111f28,0x04);
936
937 // enable vif DAC clock
938 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
939 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
940 // wriu 0x10331b 0x00
941 // wriu 0x10331a 0x00
942
943 // HAL_DMD_RIU_WriteByte(0x10331b,0x00);
944 // HAL_DMD_RIU_WriteByte(0x10331a,0x00);
945
946 // *** Set register at CLKGEN_DMD
947 // enable atsc clock
948 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
949 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
950 // wriu 0x111f03 0x04
951 // wriu 0x111f02 0x04
952
953 HAL_DMD_RIU_WriteByte(0x111f03,0x04);
954 HAL_DMD_RIU_WriteByte(0x111f02,0x04);
955 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
956 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
957 // wriu 0x111f05 0x00
958 // wriu 0x111f04 0x00
959 // HAL_DMD_RIU_WriteByte(0x111f05,0x00);
960 // HAL_DMD_RIU_WriteByte(0x111f04,0x00);
961
962 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
963 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
964 // wriu 0x111f07 0x04
965 // wriu 0x111f06 0x04
966
967 HAL_DMD_RIU_WriteByte(0x111f07,0x04);
968 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
969
970 // enable clk_atsc_adcd_sync
971 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
972 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
973 // wriu 0x111f0b 0x00
974 // wriu 0x111f0a 0x00
975
976 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
977 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
978
979 // enable dvbt inner clock
980 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
981 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
982 // wriu 0x111f0d 0x00
983 // wriu 0x111f0c 0x00
984
985 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
986 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
987
988 // enable dvbt inner clock
989 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
990 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
991 // wriu 0x111f0f 0x00
992 // wriu 0x111f0e 0x00
993
994 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
995 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
996
997 // enable dvbt inner clock
998 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
999 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
1000 // wriu 0x111f11 0x00
1001 // wriu 0x111f10 0x00
1002
1003 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1005
1006 // enable dvbc outer clock
1007 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
1008 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
1009 // wriu 0x111f13 0x00
1010 // wriu 0x111f12 0x00
1011
1012 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1013 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1014
1015 // enable dvbc inner-c clock
1016 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1017 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1018 // wriu 0x111f15 0x00
1019 // wriu 0x111f14 0x00
1020
1021 // HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1022 // HAL_DMD_RIU_WriteByte(0x111f14,0x00);
1023
1024 // enable dvbc eq clock
1025 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1026 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1027 // wriu 0x111f17 0x00
1028 // wriu 0x111f16 0x00
1029
1030 // HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1031 // HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1032
1033 // enable sram clock
1034 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1035 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1036 // wriu 0x111f19 0x00
1037 // wriu 0x111f18 0x00
1038
1039 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1040 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1041
1042 // enable isdbt clock
1043 // [2:0] : reg_ckg_isdbt_inner1x
1044 // [0] : disable clock
1045 // [1] : invert clock
1046 // [3:2]: Select clock source
1047 // 00: clk_dmplldiv10_div4(21.6MHz, ISDBT only)
1048 // 01: reserved
1049 // 10: reserved
1050 // 11: DFT_CLK
1051 // [6:4]: reg_ckg_isdbt_inner2x
1052 // [0] : disable clock
1053 // [1] : invert clock
1054 // [2]: Select clock source
1055 // 00: clk_dmplldiv10_div2(43.2MHz,ISDBT only)
1056 // 01: reserved
1057 // 10: reserved
1058 // 11: DFT_CLK
1059 // [10:8] : reg_ckg_isdbt_inner4x
1060 // [0] : disable clock
1061 // [1] : invert clock
1062 // [3:2]: Select clock source
1063 // 00: clk_dmplldiv10(86.4 MHz, DVBT only)
1064 // 01: reserved
1065 // 10: reserved
1066 // 11: DFT_CLK
1067 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1068 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h21, 2'b11, 16'h0000);
1069 // HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1070 // HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1071
1072 // enable isdbt outer clock
1073 // [3:0] : reg_ckg_isdbt_outer1x
1074 // [0] : disable clock
1075 // [1] : invert clock
1076 // [3:2]: Select clock source
1077 // 00: isdbt_clk6_lat (6 MHz)
1078 // 01: isdbt_clk8_lat (8 MHz)
1079 // 10: reserved
1080 // 11: DFT_CLK
1081 // [6:4]: reg_ckg_isdbt_outer4x
1082 // [0] : disable clock
1083 // [1] : invert clock
1084 // [3:2]: Select clock source
1085 // 00: isdbt_clk24_lat(24 MHz)
1086 // 01: isdbt_clk32_lat(32 MHz)
1087 // 10: reserved
1088 // 11: DFT_CLK
1089 // [10:8]: reg_ckg_isdbt_outer6x
1090 // [0] : disable clock
1091 // [1] : invert clock
1092 // [2] : Select clock source
1093 // 00: isdbt_clk36_lat(36 MHz)
1094 // 01: isdbt_clk48_lat(48 MHz)
1095 // 10: reserved
1096 // 11: DFT_CLK
1097 // [14:12]: reg_ckg_isdbt_outer12x
1098 // [0] : disable clock
1099 // [1] : invert clock
1100 // [2] : Select clock source
1101 // 00: isdbt_clk72_lat(72 MHz)
1102 // 01: isdbt_clk96_lat(96 MHz)
1103 // 10: reserved
1104 // 11: DFT_CLK
1105 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1106 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0000);
1107 // HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1108 // HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1109
1110 // Enable ISDBT clk_outer_div
1111 // reg_clk_isdbt_outer_div_en[0]
1112 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1113 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h23, 2'b01, 16'h0001);// enable isdbt outer div clock
1114 // HAL_DMD_RIU_WriteByte(0x111f46,0x01);
1115
1116 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1117 // [1:0] : reg_ckg_dvbtc_sram4_isdbt_inner4x
1118 // [0]: disable clock
1119 // [1]: invert clock
1120 // [5:4] : reg_ckg_dvbtc_sram4_isdbt_outer6x
1121 // [0]: disable clock
1122 // [1]: invert clock
1123 // [9:8] : reg_ckg_adc1x_eq1x
1124 // [0]: disable clock
1125 // [1]: invert clock
1126 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1127 // [0]: disable clock
1128 // [1]: invert clock
1129 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1130 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b11, 16'h0000);
1131 HAL_DMD_RIU_WriteByte(0x111f49,0x00);
1132 HAL_DMD_RIU_WriteByte(0x111f48,0x00);
1133
1134 // [1:0] : reg_ckg_isdbt_outer6x_dvbt_inner1x
1135 // [0]: disable clock
1136 // [1]: invert clock
1137 // [5:4] : reg_ckg_isdbt_outer6x_dvbt_inner2x
1138 // [0]: disable clock
1139 // [1]: invert clock
1140 // [9:8] : reg_ckg_isdbt_outer6x_dvbt_outer2x
1141 // [0]: disable clock
1142 // [1]: invert clock
1143 // [13:12]: reg_ckg_isdbt_outer6x_dvbt_outer2x_c
1144 // [0]: disable clock
1145 // [1]: invert clock
1146 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1147 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h25, 2'b11, 16'h0000);
1148 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1149 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1150
1151 // enable isdbt outer clock_rs
1152 // [7:4] : reg_ckg_isdbt_outer_rs
1153 // [0] : disable clock
1154 // [1] : invert clock
1155 // [3:2]: Select clock source
1156 // 00: isdbt_clk36_lat (36 MHz)
1157 // 01: isdbt_clk48_lat (48 MHz)
1158 // 10: clk_dmplldiv3_div4(72 MHz)
1159 // 11: isdbt_clk96_buf (96 MHz)
1160 // enable share isdbt &dvbt logic clock
1161 // [1:0] : reg_ckg_isdbt_inner2x_dvbt_inner2x
1162 // [0]: disable clock
1163 // [1]: invert clock
1164 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1165 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h26, 2'b01, 16'h0000);
1166 // HAL_DMD_RIU_WriteByte(0x111f4c,0x00);
1167 HAL_DMD_RIU_WriteByte(0x111f4c,0x11);
1168
1169 // enable vif clock
1170 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1171 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1172 // wriu 0x111f1d 0x00
1173 // wriu 0x111f1c 0x00
1174
1175 // HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1176 // HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1177
1178 // enable DEMODE-DMA clock
1179 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1180 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1181 // wriu 0x111f21 0x00
1182 // wriu 0x111f20 0x00
1183
1184 // HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1185 // HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1186 // select clock
1187 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1188 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1189 // wriu 0x111f23 0x04
1190 // wriu 0x111f22 0x44
1191 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1192 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1193
1194 // Enable SAWLESS clock
1195 // reg_ckg_adcd_d2 @0x12[3:0]
1196 // reg_ckg_adcd_d4 @0x12[7:4]
1197 // reg_ckg_adcd_d6 @0x12[11:8]
1198 // reg_ckg_adcd_d12@0x12[15:12]
1199 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1200 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0000);
1201 // wriu 0x111f25 0x00
1202 // wriu 0x111f24 0x00
1203 // HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1204 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1205
1206 // [15:12]: reg_ckg_dtmb_sram_dump
1207 // [0] : disable clock
1208 // [1] : invert clock
1209 // [3:2]: Select clock source
1210 // 00: dtmb_clk18_buf(16 MHz)
1211 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1212 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1213 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1214 HAL_DMD_RIU_WriteByte(0x111f71,0x14);
1215 HAL_DMD_RIU_WriteByte(0x111f70,0x41);
1216
1217 // ----------------------------------------------
1218 // start demod CLKGEN setting
1219 // ----------------------------------------------
1220 // select DMD MCU
1221 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1222 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1223 // [0] 0:TOP HK; 1:DMDMCU
1224 // [1] 0:DMDANAQ HK; 1:DMDMCU
1225 // begin BY temp patch
1226 // HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1227 // HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1228 // end
1229 // HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1230 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1231 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1232
1233
1234
1235 HAL_DMD_RIU_WriteByte(0x111f4f,0x00);
1236
1237 // wriu 0x111f81 0x00
1238 // wriu 0x111f80 0x00
1239 // wriu 0x111f83 0x00
1240 // wriu 0x111f82 0x00
1241 // wriu 0x111f85 0x00
1242 // wriu 0x111f84 0x00
1243 // wriu 0x111f87 0x00
1244 // wriu 0x111f86 0x00
1245
1246 HAL_DMD_RIU_WriteByte(0x111f81,0x00);
1247 HAL_DMD_RIU_WriteByte(0x111f80,0x00);
1248
1249 HAL_DMD_RIU_WriteByte(0x111f83,0x00);
1250 HAL_DMD_RIU_WriteByte(0x111f82,0x00);
1251
1252 HAL_DMD_RIU_WriteByte(0x111f85,0x00);
1253 HAL_DMD_RIU_WriteByte(0x111f84,0x00);
1254
1255 HAL_DMD_RIU_WriteByte(0x111f87,0x00);
1256 HAL_DMD_RIU_WriteByte(0x111f86,0x00);
1257
1258
1259
1260 // ----------------------------------------------
1261 // Turn TSP
1262 // ----------------------------------------------
1263 // set the ts0_clk from demod
1264 // [3:0]: CLK_TS0 clock setting
1265 // [0] : disable
1266 // [1] : invert clock
1267 // [3:2]: Select clock source
1268 // 00: select TS0_CLK
1269 // 01: select TS1_CLK
1270 // 10: reserved
1271 // 11: clk_demod_ts_p
1272 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28 , 2'b11, 16'h000c);
1273
1274 // PWDN_REF_eco => reg_reserve0[10] = 0
1275 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1276 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1277 // swch 3
1278 // wriu 0x000e13 0x01
1279
1280 // HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1281 // swch 4
1282 // Switch Demod Bank
1283 //HAL_DMD_RIU_WriteByte(0x000e13,0x01);
1284 // udatatemp = HAL_DMD_RIU_ReadByte(0x000e13);
1285 // HAL_DMD_RIU_WriteByte(0x000e13, udatatemp&0xFB);//Set 0e12,Bit10=0,
1286 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
1287 }
1288
1289
1290 /***********************************************************************************
1291 Subject: Power on initialized function
1292 Function: INTERN_DVBC_Power_On_Initialization
1293 Parmeter:
1294 Return: MS_BOOL
1295 Remark:
1296 ************************************************************************************/
1297
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)1298 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
1299 {
1300 MS_U8 status = true;
1301 DBG_INTERN_DVBC(printf("INTERN_DVBC_Power_On_Initialization\n"));
1302
1303 #if defined(PWS_ENABLE)
1304 Mapi_PWS_Stop_VDMCU();
1305 #endif
1306
1307 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1308 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1309 //// Firmware download //////////
1310 DBG_INTERN_DVBC(printf("INTERN_DVBC Load DSP...\n"));
1311 //MsOS_DelayTask(100);
1312
1313 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
1314 {
1315 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1316 {
1317 printf("DVB-C Load DSP Code Fail\n");
1318 return FALSE;
1319 }
1320 else
1321 {
1322 DBG_INTERN_DVBC(printf("DVB-C Load DSP Code OK\n"));
1323 }
1324 }
1325
1326 status &= INTERN_DVBC_Reset();
1327
1328 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1329
1330 return status;
1331 }
1332 /************************************************************************************************
1333 Subject: Driving control
1334 Function: INTERN_DVBC_Driving_Control
1335 Parmeter: bInversionEnable : TRUE For High
1336 Return: void
1337 Remark:
1338 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1339 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1340 {
1341 MS_U8 u8Temp;
1342
1343 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1344
1345 if (bEnable)
1346 {
1347 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1348 }
1349 else
1350 {
1351 u8Temp = u8Temp & (~0x01);
1352 }
1353
1354 DBG_INTERN_DVBC(printf("---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1355 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1356 }
1357 /************************************************************************************************
1358 Subject: Clk Inversion control
1359 Function: INTERN_DVBC_Clk_Inversion_Control
1360 Parmeter: bInversionEnable : TRUE For Inversion Action
1361 Return: void
1362 Remark:
1363 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1364 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1365 {
1366 MS_U8 u8Temp;
1367
1368 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1369
1370 if (bInversionEnable)
1371 {
1372 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1373 }
1374 else
1375 {
1376 u8Temp = u8Temp & (~0x02);
1377 }
1378
1379 DBG_INTERN_DVBC(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1380 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1381 }
1382 /************************************************************************************************
1383 Subject: Transport stream serial/parallel control
1384 Function: INTERN_DVBC_Serial_Control
1385 Parmeter: bEnable : TRUE For serial
1386 Return: MS_BOOL :
1387 Remark:
1388 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1389 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1390 {
1391 MS_U8 status = true;
1392 MS_U8 temp_val;
1393 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_ts... u8TSClk=%d\n", u8TSClk));
1394
1395 if (u8TSClk == 0xFF) u8TSClk=0x13;
1396 if (bEnable) //Serial mode for TS pad
1397 {
1398 // serial
1399 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1400 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1401
1402 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1403 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1404 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1405 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1406 temp_val|=0x04;
1407 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1408 #else
1409 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1410 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1411 temp_val|=0x07;
1412 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1413 #endif
1414 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1415 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1416
1417 //// INTERN_DVBC TS Control: Serial //////////
1418
1419 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_SERIAL);
1420
1421 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1422 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1423 #else
1424 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1425 #endif
1426 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1427
1428 gsCmdPacketDVBC.param[0] = TS_SERIAL;
1429 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1430 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1431 #else
1432 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1433 #endif
1434 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1435 }
1436 else
1437 {
1438 //parallel
1439 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1440 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1441
1442 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1443 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1444 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1445 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1446 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1447 temp_val|=0x05;
1448 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1449 #else
1450 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1451 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1452 temp_val|=0x07;
1453 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1454 #endif
1455
1456 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1457 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1458
1459 //// INTERN_DVBC TS Control: Parallel //////////
1460
1461 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_PARALLEL);
1462
1463 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1464 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1465 #else
1466 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1467 #endif
1468 //// INTERN_DVBC TS Control: Parallel //////////
1469 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1470
1471 gsCmdPacketDVBC.param[0] = TS_PARALLEL;
1472 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1473 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1474 #else
1475 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1476 #endif
1477 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1478 }
1479
1480 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1481 DBG_INTERN_DVBC(printf("---> Inversion(Bit5) = %d \n",0 ));
1482 #else
1483 DBG_INTERN_DVBC(printf("---> Inversion(Bit5) = %d \n",1 ));
1484 #endif
1485
1486 INTERN_DVBC_Driving_Control(INTERN_DVBC_DTV_DRIVING_LEVEL);
1487 return status;
1488 }
1489
1490 /************************************************************************************************
1491 Subject: TS1 output control
1492 Function: INTERN_DVBC_PAD_TS1_Enable
1493 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1494 Return: void
1495 Remark:
1496 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1497 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1498 {
1499 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_TS1_Enable... \n"));
1500
1501 if(flag) // PAD_TS1 Enable TS CLK PAD
1502 {
1503 //printf("=== TS1_Enable ===\n");
1504 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1505 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1506 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1507 }
1508 else // PAD_TS1 Disable TS CLK PAD
1509 {
1510 //printf("=== TS1_Disable ===\n");
1511 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1512 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1513 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1514 }
1515 }
1516
1517 /************************************************************************************************
1518 Subject: channel change config
1519 Function: INTERN_DVBC_Config
1520 Parmeter: BW: bandwidth
1521 Return: MS_BOOL :
1522 Remark:
1523 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1524 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1525 {
1526
1527 MS_U8 status = true;
1528 MS_U8 reg_symrate_l, reg_symrate_h;
1529 //MS_U16 u16Fc = 0;
1530 MS_U8 temp_val;
1531 // force
1532 // u16SymbolRate = 0;
1533 // eQamMode = DMD_DVBC_QAMAUTO;
1534
1535 pu16_symbol_rate_list = pu16_symbol_rate_list;
1536 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1537
1538 //DBG_INTERN_DVBC(printf(" @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
1539 //DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
1540
1541 if (u8TSClk == 0xFF) u8TSClk=0x13;
1542
1543 /*
1544 switch(u32IFFreq)
1545 {
1546 case 36125:
1547 case 36167:
1548 case 36000:
1549 case 6000:
1550 case 4560:
1551 //u16Fc = DVBC_FS - u32IFFreq;
1552 DBG_INTERN_DVBC(printf("Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1553 break;
1554 case 44000:
1555 default:
1556 printf("IF frequency not supported\n");
1557 status = false;
1558 break;
1559 }
1560 */
1561
1562 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1563 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1564
1565 status &= INTERN_DVBC_Reset();
1566
1567 if (eQamMode == DMD_DVBC_QAMAUTO)
1568 {
1569 DBG_INTERN_DVBC(printf("DMD_DVBC_QAMAUTO\n"));
1570 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1571 // give default value.
1572 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1573 }
1574 else
1575 {
1576 DBG_INTERN_DVBC(printf("DMD_DVBC_QAM %d\n", eQamMode));
1577 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1578 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1579 }
1580 // auto symbol rate enable/disable
1581 if (u16SymbolRate == 0)
1582 {
1583 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1584 }
1585 else
1586 {
1587 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1588 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1589 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1590 }
1591 // TS mode
1592 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1593
1594 // IQ Swap
1595 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1596
1597 // Fc
1598 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1599 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1600 // Lif
1601 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1602 // Fif
1603 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1604 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1605
1606 //// INTERN_DVBC system init: DVB-C //////////
1607 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1608
1609 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1610 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1611
1612 if (bSerialTS)
1613 {
1614 // serial
1615 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1616 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1617
1618 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1619 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1620 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1621 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1622 temp_val|=0x04;
1623 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1624 #else
1625 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1626 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1627 temp_val|=0x07;
1628 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1629 #endif
1630 }
1631 else
1632 {
1633 //parallel
1634 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1635 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1636
1637 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1638 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1639 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1640 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1641 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1642 temp_val|=0x05;
1643 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1644 #else
1645 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1646 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1647 temp_val|=0x07;
1648 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1649 #endif
1650 }
1651 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1652 INTERN_DVBC_Show_Demod_Version();
1653 #endif
1654
1655 return status;
1656 }
1657 /************************************************************************************************
1658 Subject: enable hw to lock channel
1659 Function: INTERN_DVBC_Active
1660 Parmeter: bEnable
1661 Return: MS_BOOL
1662 Remark:
1663 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1664 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1665 {
1666 MS_U8 status = true;
1667
1668 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_active\n"));
1669
1670 //// INTERN_DVBC Finite State Machine on/off //////////
1671 #if 0
1672 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1673
1674 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1675 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1676 #else
1677 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1678 #endif
1679
1680 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1681 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1682 return status;
1683 }
1684
1685
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,MS_U32 u32CurrRFPowerDbm,MS_U32 u32NoChannelRFPowerDbm,MS_U32 u32TimeInterval)1686 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1687 {
1688 MS_U16 u16Address = 0;
1689 MS_U8 cData = 0;
1690 MS_U8 cBitMask = 0;
1691
1692
1693 if (u32CurrRFPowerDbm < 1000)
1694 {
1695 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1696 {
1697 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1698 if (cData > 5)
1699 {
1700 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1701 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1702 }
1703 else
1704 {
1705 if ((u32CurrRFPowerDbm<u32NoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000*10))
1706 {
1707 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval*10;
1708 }
1709 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500*10)
1710 {
1711 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1712 #ifdef MS_DEBUG
1713 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1714 #endif
1715 return TRUE;
1716 }
1717 }
1718 #ifdef MS_DEBUG
1719 printf("INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%d Threshold:%d Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, u32CurrRFPowerDbm, u32NoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1720 #endif
1721 }
1722 }
1723
1724 {
1725 switch( eType )
1726 {
1727 case DMD_DVBC_GETLOCK_FEC_LOCK:
1728 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1729 #if (INTERN_DVBC_INTERNAL_DEBUG)
1730 INTERN_DVBC_info();
1731 #endif
1732 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_GetLock FSM 0x%x\n",cData));
1733 if (cData == 0x0C)
1734 {
1735 if(g_dvbc_lock == 0)
1736 {
1737 g_dvbc_lock = 1;
1738 DBG_INTERN_DVBC(printf("[T12][DVBC]lock++++\n"));
1739
1740 }
1741 return TRUE;
1742 }
1743 else
1744 {
1745 if(g_dvbc_lock == 1)
1746 {
1747 g_dvbc_lock = 0;
1748 DBG_INTERN_DVBC(printf("[T12][DVBC]unlock----\n"));
1749 }
1750 return FALSE;
1751 }
1752 break;
1753
1754 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1755 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1756 cBitMask = BIT(1);
1757 break;
1758
1759 case DMD_DVBC_GETLOCK_DCR_LOCK:
1760 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1761 cBitMask = BIT(0);
1762 break;
1763
1764 case DMD_DVBC_GETLOCK_AGC_LOCK:
1765 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1766 cBitMask = BIT(0);
1767 break;
1768
1769 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1770 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1771 cBitMask = BIT(2)|BIT(3)|BIT(4);
1772 #ifdef MS_DEBUG
1773 {
1774 MS_U8 reg_frz=0, FSM=0;
1775 MS_U16 u16Timer=0;
1776 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1777 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1778 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1779 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1780 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1781 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1782 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1783 u16Timer=(u16Timer<<8)+reg_frz;
1784 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1785 u16Timer=(u16Timer<<8)+reg_frz;
1786 printf("DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1787 }
1788 #endif
1789 break;
1790
1791 case DMD_DVBC_GETLOCK_ATV_DETECT:
1792 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1793 cBitMask = BIT(1); // check atv
1794 break;
1795
1796 case DMD_DVBC_GETLOCK_TR_LOCK:
1797 #if 0 // 20111108 temporarily solution
1798 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
1799 cBitMask = BIT(4);
1800 break;
1801 #endif
1802 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1803 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1804 cBitMask = BIT(4);
1805 break;
1806
1807 default:
1808 return FALSE;
1809 }
1810
1811 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1812 return FALSE;
1813
1814 if ((cData & cBitMask) != 0)
1815 {
1816 return TRUE;
1817 }
1818
1819 return FALSE;
1820 }
1821
1822 return FALSE;
1823 }
1824
1825
1826 /****************************************************************************
1827 Subject: To get the Post viterbi BER
1828 Function: INTERN_DVBC_GetPostViterbiBer
1829 Parmeter: Quility
1830 Return: E_RESULT_SUCCESS
1831 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1832 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1833 We will not read the Period, and have the "/256/8"
1834 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg)1835 MS_BOOL INTERN_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg)
1836 {
1837 MS_BOOL status = true;
1838 MS_U8 reg = 0, reg_frz = 0;
1839 //MS_U16 BitErrPeriod;
1840 //MS_U32 BitErr;
1841 //MS_U16 PktErr;
1842
1843 /////////// Post-Viterbi BER /////////////
1844
1845 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1847 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1848
1849 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1850 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1852 *BitErrPeriod_reg = reg;
1853
1854 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1855 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8)|reg;
1856
1857 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1858 // 0x6b [15:8] reg_bit_err_num_15_8
1859 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1860 // 0x6d [15:8] reg_bit_err_num_31_24
1861 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1862 *BitErr_reg = reg;
1863
1864 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1865 *BitErr_reg = (*BitErr_reg << 8)|reg;
1866
1867 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1868 *BitErr_reg = (*BitErr_reg << 8)|reg;
1869
1870 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1871 *BitErr_reg = (*BitErr_reg << 8)|reg;
1872
1873
1874 //INTERN_DVBC_GetPacketErr(&PktErr);
1875
1876 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1877 reg_frz=reg_frz&(~0x03);
1878 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1879 /*
1880 if (BitErrPeriod == 0 ) //protect 0
1881 BitErrPeriod = 1;
1882
1883 if (BitErr <=0 )
1884 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1885 else
1886 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1887
1888 DBG_GET_SIGNAL_DVBC(printf("INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1889 */
1890 return status;
1891 }
1892
1893 /****************************************************************************
1894 Subject: To get the Packet error
1895 Function: INTERN_DVBC_GetPacketErr
1896 Parmeter: pktErr
1897 Return: E_RESULT_SUCCESS
1898 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1899 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1900 We will not read the Period, and have the "/256/8"
1901 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1902 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1903 {
1904 MS_BOOL status = true;
1905 MS_U8 reg = 0, reg_frz = 0;
1906 MS_U16 PktErr;
1907
1908 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1909 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1910 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1911
1912 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1913 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1914 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1915 PktErr = reg;
1916
1917 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1918 PktErr = (PktErr << 8)|reg;
1919
1920 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1921 reg_frz=reg_frz&(~0x03);
1922 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1923
1924 DBG_GET_SIGNAL_DVBC(printf("INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1925
1926 *pktErr = PktErr;
1927
1928 return status;
1929 }
1930
1931 /****************************************************************************
1932 Subject: Read the signal to noise ratio (SNR)
1933 Function: INTERN_DVBC_GetSNR
1934 Parmeter: None
1935 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1936 Remark:
1937 *****************************************************************************/
INTERN_DVBC_GetSNR(MS_U16 * snr_reg)1938 MS_BOOL INTERN_DVBC_GetSNR(MS_U16 *snr_reg)
1939 {
1940 MS_BOOL status = true;
1941 MS_U8 u8Data = 0, reg_frz = 0;
1942 // MS_U8 freeze = 0;
1943 //MS_U16 noisepower = 0;
1944
1945 //if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1946 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200*10, -200*10, 0) )
1947 {
1948 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
1950 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
1951
1952 // read vk
1953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6f, &u8Data);
1954 //noisepower = u8Data;
1955 *snr_reg = u8Data;
1956 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x6e, &u8Data);
1957 //noisepower = (noisepower<<8)|u8Data;
1958 *snr_reg = ((*snr_reg)<<8)|u8Data;
1959
1960 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1961 reg_frz=reg_frz&(~0x01);
1962 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
1963
1964 //if(noisepower == 0x0000)
1965 // noisepower = 0x0001;
1966 if(*snr_reg == 0x0000)
1967 *snr_reg = 0x0001;
1968 /*
1969 #ifdef MSOS_TYPE_LINUX
1970 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1971 #else
1972 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1973 #endif
1974 */
1975 }
1976 else
1977 {
1978 *snr_reg = 0;
1979 }
1980 return status;
1981
1982
1983 }
1984
INTERN_DVBC_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1985 MS_BOOL INTERN_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1986 {
1987 MS_BOOL status = true;
1988
1989 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1990
1991 return status;
1992 }
1993
1994 //waiting mark
1995 #if(0)
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue)1996 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
1997 {
1998 MS_BOOL status = true;
1999 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
2000 DMD_DVBC_MODULATION_TYPE Qam_mode;
2001
2002 DBG_INTERN_DVBC_TIME(printf("INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi)));
2003
2004 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
2005 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
2006 /* Actually, it's more reasonable, that signal level depended on cable input power level
2007 * thougth the signal isn't dvb-t signal.
2008 */
2009 // use pointer of IFAGC table to identify
2010 // case 1: RFAGC from SAR, IFAGC controlled by demod
2011 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2012 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2013 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
2014 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2015 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2016 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
2017 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
2018
2019 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2020
2021 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
2022 {
2023 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
2024 }
2025 else
2026 {
2027 ch_power_db_rel = -100.0f;
2028 }
2029
2030 if(ch_power_db_rel <= -85.0f)
2031 {*strength = 0;}
2032 else if (ch_power_db_rel <= -80.0f)
2033 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
2034 else if (ch_power_db_rel <= -75.0f)
2035 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
2036 else if (ch_power_db_rel <= -70.0f)
2037 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
2038 else if (ch_power_db_rel <= -65.0f)
2039 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
2040 else if (ch_power_db_rel <= -55.0f)
2041 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
2042 else if (ch_power_db_rel <= -45.0f)
2043 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
2044 else
2045 {*strength = 100;}
2046
2047 DBG_GET_SIGNAL_DVBC(printf(">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2048 DBG_GET_SIGNAL_DVBC(printf(">>> SSI = %d <<<\n", (int)*strength));
2049
2050 return status;
2051 }
2052 #endif
2053
2054
2055 /****************************************************************************
2056 Subject: To get the DVT Signal quility
2057 Function: INTERN_DVBC_GetSignalQuality
2058 Parmeter: Quility
2059 Return: E_RESULT_SUCCESS
2060 E_RESULT_FAILURE
2061 Remark: Here we have 4 level range
2062 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2063 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2064 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2065 <4>.4th Range => Quality <10
2066 *****************************************************************************/
2067 //waiting mark
2068 /*
2069 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
2070 {
2071
2072 float fber;
2073 float log_ber;
2074 MS_BOOL status = true;
2075 DMD_DVBC_MODULATION_TYPE Qam_mode;
2076 float f_snr;
2077
2078 fRFPowerDbm = fRFPowerDbm;
2079 status &= INTERN_DVBC_GetSNR(&f_snr);
2080 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
2081 {
2082 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
2083 {
2084 DBG_INTERN_DVBC(printf("\nGetPostViterbiBer Fail!"));
2085 return FALSE;
2086 }
2087
2088 // log_ber = log10(fber)
2089 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
2090
2091 DBG_INTERN_DVBC(printf("\nLog(BER) = %f",log_ber));
2092 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2093 if (Qam_mode == DMD_DVBC_QAM16)
2094 {
2095 if(log_ber <= (-5.5f))
2096 *quality = 100;
2097 else if(log_ber <= (-5.1f))
2098 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
2099 else if(log_ber <= (-4.9f))
2100 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2101 else if(log_ber <= (-4.5f))
2102 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
2103 else if(log_ber <= (-3.7f))
2104 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
2105 else if(log_ber <= (-3.2f))
2106 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2107 else if(log_ber <= (-2.9f))
2108 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2109 else if(log_ber <= (-2.5f))
2110 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
2111 else if(log_ber <= (-2.2f))
2112 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
2113 else if(log_ber <= (-2.0f))
2114 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2115 else
2116 *quality = 0;
2117 }
2118 else if (Qam_mode == DMD_DVBC_QAM32)
2119 {
2120 if(log_ber <= (-5.0f))
2121 *quality = 100;
2122 else if(log_ber <= (-4.7f))
2123 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
2124 else if(log_ber <= (-4.5f))
2125 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
2126 else if(log_ber <= (-3.8f))
2127 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
2128 else if(log_ber <= (-3.5f))
2129 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
2130 else if(log_ber <= (-3.0f))
2131 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
2132 else if(log_ber <= (-2.7f))
2133 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
2134 else if(log_ber <= (-2.4f))
2135 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2136 else if(log_ber <= (-2.2f))
2137 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2138 else if(log_ber <= (-2.0f))
2139 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2140 else
2141 *quality = 0;
2142 }
2143 else if (Qam_mode == DMD_DVBC_QAM64)
2144 {
2145 if(log_ber <= (-5.4f))
2146 *quality = 100;
2147 else if(log_ber <= (-5.1f))
2148 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
2149 else if(log_ber <= (-4.9f))
2150 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2151 else if(log_ber <= (-4.3f))
2152 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
2153 else if(log_ber <= (-3.7f))
2154 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
2155 else if(log_ber <= (-3.2f))
2156 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2157 else if(log_ber <= (-2.9f))
2158 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2159 else if(log_ber <= (-2.4f))
2160 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
2161 else if(log_ber <= (-2.2f))
2162 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2163 else if(log_ber <= (-2.05f))
2164 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
2165 else
2166 *quality = 0;
2167 }
2168 else if (Qam_mode == DMD_DVBC_QAM128)
2169 {
2170 if(log_ber <= (-5.1f))
2171 *quality = 100;
2172 else if(log_ber <= (-4.9f))
2173 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2174 else if(log_ber <= (-4.7f))
2175 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
2176 else if(log_ber <= (-4.1f))
2177 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
2178 else if(log_ber <= (-3.5f))
2179 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
2180 else if(log_ber <= (-3.1f))
2181 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2182 else if(log_ber <= (-2.7f))
2183 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2184 else if(log_ber <= (-2.5f))
2185 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
2186 else if(log_ber <= (-2.06f))
2187 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
2188 //else if(log_ber <= (-2.05))
2189 else
2190 {
2191 if (f_snr >= 27.2f)
2192 *quality = 20;
2193 else if (f_snr >= 25.1f)
2194 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
2195 else
2196 *quality = 0;
2197 }
2198 }
2199 else //256QAM
2200 {
2201 if(log_ber <= (-4.8f))
2202 *quality = 100;
2203 else if(log_ber <= (-4.6f))
2204 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
2205 else if(log_ber <= (-4.4f))
2206 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
2207 else if(log_ber <= (-4.0f))
2208 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
2209 else if(log_ber <= (-3.5f))
2210 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
2211 else if(log_ber <= (-3.1f))
2212 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2213 else if(log_ber <= (-2.7f))
2214 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2215 else if(log_ber <= (-2.4f))
2216 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2217 else if(log_ber <= (-2.06f))
2218 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
2219 //else if(log_ber <= (-2.05))
2220 else
2221 {
2222 if (f_snr >= 29.6f)
2223 *quality = 20;
2224 else if (f_snr >= 27.3f)
2225 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
2226 else
2227 *quality = 0;
2228 }
2229 }
2230 }
2231 else
2232 {
2233 *quality = 0;
2234 }
2235
2236 //DBG_GET_SIGNAL_DVBC(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2237 DBG_GET_SIGNAL_DVBC(printf("BER = %8.3e\n", fber));
2238 DBG_GET_SIGNAL_DVBC(printf("Signal Quility = %d\n", *quality));
2239 return TRUE;
2240 }
2241 #endif
2242 */
2243
2244 /****************************************************************************
2245 Subject: To get the Cell ID
2246 Function: INTERN_DVBC_Get_CELL_ID
2247 Parmeter: point to return parameter cell_id
2248
2249 Return: TRUE
2250 FALSE
2251 Remark:
2252 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)2253 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
2254 {
2255 MS_BOOL status = true;
2256 MS_U8 value1 = 0;
2257 MS_U8 value2 = 0;
2258
2259 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
2260 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
2261
2262 *cell_id = ((MS_U16)value1<<8)|value2;
2263 return status;
2264 }
2265
2266 /****************************************************************************
2267 Subject: To get the DVBC Carrier Freq Offset
2268 Function: INTERN_DVBC_Get_FreqOffset
2269 Parmeter: Frequency offset (in KHz), bandwidth
2270 Return: E_RESULT_SUCCESS
2271 E_RESULT_FAILURE
2272 Remark:
2273 *****************************************************************************/
2274 #if(1)
INTERN_DVBC_Get_FreqOffset(MS_U32 * config_Fc_reg,MS_U32 * Fc_over_Fs_reg,MS_U16 * Cfo_offset_reg,MS_U8 u8BW)2275 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW)
2276 {
2277 MS_U8 reg_frz = 0, reg = 0;
2278 MS_BOOL status = TRUE;
2279
2280 // no use.
2281 u8BW = u8BW;
2282
2283 DBG_INTERN_DVBC(printf("INTERN_DVBC_Get_FreqOffset\n"));
2284
2285 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2286 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d, ®_frz);
2287 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz|0x01);
2288
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75, ®);
2290 *config_Fc_reg = reg;
2291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74, ®);
2292 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
2293 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73, ®);
2294 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
2295 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72, ®);
2296 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
2297
2298 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2299 reg_frz=reg_frz&(~0x01);
2300 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d, reg_frz);
2301
2302 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
2303 *Fc_over_Fs_reg = reg;
2304 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
2305 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
2306 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
2307 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
2308 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
2309 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
2310
2311 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
2312 *Cfo_offset_reg = reg;
2313 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
2314 *Cfo_offset_reg = (*Cfo_offset_reg<<8)|reg;
2315
2316 //waiting mark
2317 /*
2318 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
2319
2320 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
2321
2322 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
2323
2324 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
2325
2326 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
2327 DBG_INTERN_DVBC_LOCK(printf("[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
2328 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
2329
2330 *pFreqOff = FreqCfo_offset;
2331 */
2332 return status;
2333 }
2334 #endif
2335
2336
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)2337 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
2338 {
2339
2340 bPowerOn = bPowerOn;
2341 }
2342
INTERN_DVBC_Power_Save(void)2343 MS_BOOL INTERN_DVBC_Power_Save(void)
2344 {
2345
2346 return TRUE;
2347 }
2348
2349 /****************************************************************************
2350 Subject: To get the current modulation type at the DVB-C Demod
2351 Function: INTERN_DVBC_GetCurrentModulationType
2352 Parmeter: pointer for return QAM type
2353
2354 Return: TRUE
2355 FALSE
2356 Remark:
2357 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)2358 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
2359 {
2360 MS_U8 u8Data=0;
2361
2362 DBG_INTERN_DVBC(printf("INTERN_DVBC_GetCurrentModulationType\n"));
2363
2364 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0xC4, &u8Data);
2365
2366 switch(u8Data&0x07)
2367 {
2368 case 0:
2369 *pQAMMode = DMD_DVBC_QAM16;
2370 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=16\n"));
2371 return TRUE;
2372 break;
2373 case 1:
2374 *pQAMMode = DMD_DVBC_QAM32;
2375 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=32\n"));
2376 return TRUE;
2377 break;
2378 case 2:
2379 *pQAMMode = DMD_DVBC_QAM64;
2380 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=64\n"));
2381 return TRUE;
2382 break;
2383 case 3:
2384 *pQAMMode = DMD_DVBC_QAM128;
2385 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=128\n"));
2386 return TRUE;
2387 break;
2388 case 4:
2389 *pQAMMode = DMD_DVBC_QAM256;
2390 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=256\n"));
2391 return TRUE;
2392 break;
2393 default:
2394 *pQAMMode = DMD_DVBC_QAMAUTO;
2395 DBG_INTERN_DVBC_LOCK(printf("[dvbc]QAM=invalid\n"));
2396 return FALSE;
2397 }
2398 }
2399
2400 /****************************************************************************
2401 Subject: To get the current symbol rate at the DVB-C Demod
2402 Function: INTERN_DVBC_GetCurrentSymbolRate
2403 Parmeter: pointer pData for return Symbolrate
2404
2405 Return: TRUE
2406 FALSE
2407 Remark:
2408 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2409 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2410 {
2411 MS_U8 tmp = 0;
2412 MS_U16 u16SymbolRateTmp = 0;
2413
2414 // intp
2415 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd2, &tmp);
2416 u16SymbolRateTmp = tmp;
2417 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd1, &tmp);
2418 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2419
2420 if (abs(u16SymbolRateTmp-6900)<2)
2421 {
2422 u16SymbolRateTmp=6900;
2423 }
2424
2425 if (abs(u16SymbolRateTmp-6875)<2)
2426 {
2427 u16SymbolRateTmp=6875;
2428 }
2429
2430 *u16SymbolRate = u16SymbolRateTmp;
2431
2432 DBG_INTERN_DVBC_LOCK(printf("[dvbc]SR=%d\n",*u16SymbolRate));
2433
2434 return TRUE;
2435 }
2436
2437
2438 /****************************************************************************
2439 Subject: To get the current symbol rate offset at the DVB-C Demod
2440 Function: INTERN_DVBC_GetCurrentSymbolRate
2441 Parmeter: pointer pData for return Symbolrate offset
2442
2443 Return: TRUE
2444 FALSE
2445 Remark:
2446 *****************************************************************************/
2447
2448 #if(0)
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)2449 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2450 {
2451 MS_U8 u8Data = 0, reg_frz = 0;
2452 MS_U32 u32Data = 0;
2453 // MS_S32 s32Data = 0;
2454 MS_BOOL status = TRUE;
2455 MS_U16 u16SymbolRate = 0;
2456 float f_symb_offset = 0.0f;
2457
2458
2459
2460 // bank 26 0x03 [7] reg_bit_err_num_freeze
2461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
2462 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
2463
2464 // sel, SFO debug output.
2465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
2466 u32Data = u8Data;
2467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
2468 u32Data = (u32Data<<8)|u8Data;
2469 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
2470 u32Data = (u32Data<<8)|u8Data;
2471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
2472 u32Data = (u32Data<<8)|u8Data;
2473
2474 // bank 26 0x03 [7] reg_bit_err_num_freeze
2475 reg_frz=reg_frz&(~0x80);
2476 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
2477 // s32Data = (MS_S32)(u32Data<<8);
2478
2479 printf("[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2480
2481 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2482
2483 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
2484 // f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
2485 f_symb_offset = (float)((MS_S32)u32Data) * (0.000007276f) * (float)u16SymbolRate/(float)DVBC_FS;
2486
2487 *pData = (MS_U16)(f_symb_offset + 0.5f);
2488
2489 DBG_INTERN_DVBC_LOCK(printf("[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
2490
2491 return status;
2492 }
2493 #endif
2494
INTERN_DVBC_Version(MS_U16 * ver)2495 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2496 {
2497
2498 MS_U8 status = true;
2499 MS_U8 tmp = 0;
2500 MS_U16 u16_INTERN_DVBC_Version;
2501
2502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2503 u16_INTERN_DVBC_Version = tmp;
2504 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2505 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2506 *ver = u16_INTERN_DVBC_Version;
2507
2508 return status;
2509 }
2510
2511
INTERN_DVBC_Show_Demod_Version(void)2512 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2513 {
2514
2515 MS_BOOL status = true;
2516 MS_U16 u16_INTERN_DVBC_Version;
2517
2518 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2519
2520 printf("[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2521
2522 return status;
2523 }
2524
2525
2526
2527 #if (INTERN_DVBC_INTERNAL_DEBUG)
2528
INTERN_DVBC_Show_AGC_Info(void)2529 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2530 {
2531 MS_U8 tmp = 0;
2532 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2533 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2534 MS_U16 if_agc_err = 0;
2535 MS_BOOL status = TRUE;
2536
2537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2538 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2539 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2540 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2541 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2542 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2543
2544
2545 // select IF gain to read
2546 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2547 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2548
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2550 if_agc_gain = tmp;
2551 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2552 if_agc_gain = (if_agc_gain<<8)|tmp;
2553
2554
2555 // select d1 gain to read.
2556 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2557 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2558
2559 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2560 d1_gain = tmp;
2561 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2562 d1_gain = (d1_gain<<8)|tmp;
2563
2564 // select d2 gain to read.
2565 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2566 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2567
2568 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2569 d2_gain = tmp;
2570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2571 d2_gain = (d2_gain<<8)|tmp;
2572
2573 // select IF gain err to read
2574 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2575 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2576
2577 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2578 if_agc_err = tmp;
2579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2580 if_agc_err = (if_agc_err<<8)|tmp;
2581
2582 printf("[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2583 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2584
2585 printf("[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2586
2587 return status;
2588 }
2589
INTERN_DVBC_info(void)2590 void INTERN_DVBC_info(void)
2591 {
2592 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2593 MS_U8 qam,tmp = 0;
2594 MS_U8 fft_u8 = 0;
2595 MS_U16 fft_u16bw = 0;
2596 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2597 //float f_snr = 0,f_freq = 0;
2598 //DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2599 MS_U16 f_start = 0,f_end = 0;
2600 MS_U8 s0_count = 0;
2601 MS_U8 sc4 = 0,sc3 = 0;
2602 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2603 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2604 MS_U16 count = 0;
2605 MS_U16 fb_i_1,fb_q_1;
2606 MS_U8 e0,e1,e2,e3;
2607 MS_S16 reg_freq;
2608 //float freq,mag;
2609
2610
2611
2612 INTERN_DVBC_Version(&version);
2613
2614 // fb_fs
2615 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2616 fb_fs = tmp;
2617 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2618 fb_fs = (fb_fs<<8)|tmp;
2619 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2620 fb_fs = (fb_fs<<8)|tmp;
2621 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2622 fb_fs = (fb_fs<<8)|tmp;
2623 // fc_fs
2624 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2625 fc_fs = tmp;
2626 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2627 fc_fs = (fc_fs<<8)|tmp;
2628 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2629 fc_fs = (fc_fs<<8)|tmp;
2630 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2631 fc_fs = (fc_fs<<8)|tmp;
2632 // crv
2633 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2634 crv = tmp;
2635 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2636 crv = (crv<<8)|tmp;
2637 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2638 crv = (crv<<8)|tmp;
2639 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2640 crv = (crv<<8)|tmp;
2641 // tr_error
2642 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2643 tr_error = tmp;
2644 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2645 tr_error = (tr_error<<8)|tmp;
2646 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2647 tr_error = (tr_error<<8)|tmp;
2648
2649 // intp
2650 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2651 intp = tmp;
2652 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2653 intp = (intp<<8)|tmp;
2654 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2655 intp = (intp<<8)|tmp;
2656 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2657 intp = (intp<<8)|tmp;
2658
2659 //waiting mark
2660 // fft info
2661 // intp
2662 /*
2663 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2664 fft_u16bw = tmp;
2665 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2666 fft_u16bw = (fft_u16bw<<8)|tmp;
2667 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2668 fft_u8 = tmp;
2669 */
2670
2671 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2672 qam = tmp;
2673
2674 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2675 f_start = tmp;
2676 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2677 f_start = (f_start<<8)|tmp;
2678 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2679 f_end = tmp;
2680 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2681 f_end = (f_end<<8)|tmp;
2682 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2683 s0_count = tmp;
2684
2685 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2686 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2687
2688 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2689 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2690 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2691 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2692 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2693 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2694 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2695
2696
2697 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2698
2699 count = 0x400;
2700 while(count--);
2701
2702 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2703 aci_e0 = tmp&0x0f;
2704 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2705 aci_e0 = aci_e0<<8|tmp;
2706
2707 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2708
2709 count = 0x400;
2710 while(count--);
2711
2712
2713 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2714 aci_e1 = tmp&0x0f;
2715 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2716 aci_e1 = aci_e1<<8|tmp;
2717
2718 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2719
2720 count = 0x400;
2721 while(count--);
2722
2723 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2724 aci_e2 = tmp&0x0f;
2725 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2726 aci_e2 = aci_e2<<8|tmp;
2727
2728 // read aci coef
2729 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2730
2731 count = 0x400;
2732 while(count--);
2733
2734 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2735 aci_e3 = tmp&0x0f;
2736 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2737 aci_e3 = aci_e3<<8|tmp;
2738
2739 //waiting mark
2740 /*
2741 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2742 fb_i_1 = tmp;
2743 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2744 fb_i_1 = fb_i_1<<8|tmp;
2745
2746 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2747 fb_q_1 = tmp;
2748 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2749 fb_q_1 = fb_q_1<<8|tmp;
2750 */
2751
2752 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2753 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2754 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2755 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2756
2757 //reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2758 //freq = (float)reg_freq*45473.0/65536.0;
2759 //mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2760
2761
2762 INTERN_DVBC_GetPacketErr(&packetErr);
2763 //INTERN_DVBC_GetSNR(&f_snr);
2764 INTERN_DVBC_Show_AGC_Info();
2765 //INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2766 //INTERN_DVBC_Get_FreqOffset(&f_freq,8); //GetStatus
2767 //INTERN_DVBC_GetCurrentSymbolRate(&symb_rate); //GetStatus
2768 //INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2769 //INTERN_DVBC_GetCurrentModulationType(&QAMMode); //GetStatus
2770 /*
2771 printf("[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2772 //printf("[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2773 printf("[MStar_2][2]0x%lx\n",intp);
2774 printf("[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2775 printf("[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2776 printf("[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2777 //printf("[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2778 printf("[Mstar_6][3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2779 */
2780 return;
2781
2782 }
2783
2784
2785 #endif
2786
2787 /***********************************************************************************
2788 Subject: read register
2789 Function: MDrv_1210_IIC_Bypass_Mode
2790 Parmeter:
2791 Return:
2792 Remark:
2793 ************************************************************************************/
2794 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2795 //{
2796 // UNUSED(enable);
2797 // if (enable)
2798 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2799 // else
2800 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2801 //}
2802