1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #include <stdio.h>
101 #include <math.h>
102
103 #include "drvDMD_ATSC.h"
104
105 #include "MsTypes.h"
106 #if DMD_ATSC_UTOPIA_EN || DMD_ATSC_UTOPIA2_EN
107 #include "drvDMD_common.h"
108 #include "halDMD_INTERN_common.h"
109 #endif
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114
115 #define DMD_ATSC_CHIP_T3_T10 0x01
116 #define DMD_ATSC_CHIP_T7 0x02
117 #define DMD_ATSC_CHIP_T8_T9 0x03
118 #define DMD_ATSC_CHIP_A1 0x04
119 #define DMD_ATSC_CHIP_A3 0x05
120 #define DMD_ATSC_CHIP_A5 0x06
121 #define DMD_ATSC_CHIP_A7 0x07
122 #define DMD_ATSC_CHIP_A7P 0x08
123 #define DMD_ATSC_CHIP_AGATE 0x09
124 #define DMD_ATSC_CHIP_EDISON 0x0A
125 #define DMD_ATSC_CHIP_EINSTEIN 0x0B
126 #define DMD_ATSC_CHIP_EMERALD 0x0C
127 #define DMD_ATSC_CHIP_EIFFEL 0x0D
128 #define DMD_ATSC_CHIP_EDEN 0x0E
129 #define DMD_ATSC_CHIP_EINSTEIN3 0x0F
130 #define DMD_ATSC_CHIP_MONACO 0x10
131 #define DMD_ATSC_CHIP_MIAMI 0x11
132 #define DMD_ATSC_CHIP_MUJI 0x12
133 #define DMD_ATSC_CHIP_MUNICH 0x13
134 #define DMD_ATSC_CHIP_MAYA 0x14
135 #define DMD_ATSC_CHIP_MANHATTAN 0x15
136 #define DMD_ATSC_CHIP_WHISKY 0x16
137 #define DMD_ATSC_CHIP_MASERATI 0x17
138 #define DMD_ATSC_CHIP_MACAN 0x18
139
140 #define DMD_ATSC_CHIP_K3 0x80 //UTOF start from 0x80
141 #define DMD_ATSC_CHIP_KELTIC 0x81
142 #define DMD_ATSC_CHIP_KERES 0x82
143 #define DMD_ATSC_CHIP_KIRIN 0x83
144
145 #if defined(a1)
146 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A1
147 #elif defined(a3)
148 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A3
149 #elif defined(a5)
150 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A5
151 #elif defined(a7)
152 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7
153 #elif defined(amethyst)
154 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7P
155 #elif defined(agate)
156 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_AGATE
157 #elif defined(edison)
158 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDISON
159 #elif defined(einstein)
160 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN
161 #elif defined(einstein3)
162 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN3
163 #elif defined(monaco)
164 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MONACO
165 #elif defined(emerald)
166 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EMERALD
167 #elif defined(eiffel)
168 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EIFFEL
169 #elif defined(kaiser)
170 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_K3
171 #elif defined(keltic)
172 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KELTIC
173 #elif defined(eden)
174 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDEN
175 #elif defined(miami)
176 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MIAMI
177 #elif defined(keres)
178 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KERES
179 #elif defined(muji)
180 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUJI
181 #elif defined(munich)
182 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUNICH
183 #elif defined(kirin)
184 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KIRIN
185 #elif defined(maya)
186 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MAYA
187 #elif defined(manhattan)
188 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MANHATTAN
189 #elif defined(whisky)
190 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_WHISKY
191 #elif defined(maserati)
192 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MASERATI
193 #elif defined(macan)
194 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MACAN
195 #else
196 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MACAN
197 #endif
198
199 //-------------------------------------------------------------------------------------------------
200 // Local Defines
201 //-------------------------------------------------------------------------------------------------
202
203 #define HAL_INTERN_ATSC_DBINFO(y) //y
204
205 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
206 #ifndef MBRegBase
207 #define MBRegBase 0x112600UL
208 #endif
209 #ifndef MBRegBase_DMD1
210 #define MBRegBase_DMD1 0x112400UL
211 #endif
212 #else
213 #ifndef MBRegBase
214 #define MBRegBase 0x110500UL
215 #endif
216 #endif
217
218 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
219 #ifndef DMDMcuBase
220 #define DMDMcuBase 0x103460UL
221 #endif
222 #else
223 #ifndef DMDMcuBase
224 #define DMDMcuBase 0x103480UL
225 #endif
226 #endif
227
228 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
229 #define INTERN_ATSC_OUTER_STATE 0xF0
230 #else
231 #define INTERN_ATSC_OUTER_STATE 0x80
232 #endif
233 #define INTERN_ATSC_VSB_TRAIN_SNR_LIMIT 0x05//0xBE//14.5dB
234 #define INTERN_ATSC_FEC_ENABLE 0x1F
235
236 #define VSB_ATSC 0x04
237 #define QAM256_ATSC 0x02
238
239 #define QAM16_J83ABC 0x00
240 #define QAM32_J83ABC 0x01
241 #define QAM64_J83ABC 0x02
242 #define QAM128_J83ABC 0x03
243 #define QAM256_J83ABC 0x04
244
245 //-------------------------------------------------------------------------------------------------
246 // Local Variables
247 //-------------------------------------------------------------------------------------------------
248
249 const MS_U8 INTERN_ATSC_table[] = {
250 #include "DMD_INTERN_ATSC.dat"
251 };
252
253 static MS_U16 u16Lib_size = sizeof(INTERN_ATSC_table);
254
255 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
256
257 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
258 static MS_U8 Demod_Flow_register[17] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
259 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x08, 0x70, 0x68};
260 #else
261 static MS_U8 Demod_Flow_register[21] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
262 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x00, 0x00, 0x00, 0x00,
263 0x00, 0x00, 0x00};
264 #endif
265
266 #endif
267
268 //-------------------------------------------------------------------------------------------------
269 // Global Variables
270 //-------------------------------------------------------------------------------------------------
271
272 extern MS_U8 u8DMD_ATSC_DMD_ID;
273
274 extern DMD_ATSC_ResData *psDMD_ATSC_ResData;
275
276 //-------------------------------------------------------------------------------------------------
277 // Local Functions
278 //-------------------------------------------------------------------------------------------------
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)279 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
280 {
281 MS_U8 u8CheckCount;
282 MS_U8 u8CheckFlag = 0xFF;
283
284 if (u8DMD_ATSC_DMD_ID == 0)
285 {
286 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
287 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
288 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
289 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
290 }
291 else if (u8DMD_ATSC_DMD_ID == 1)
292 {
293 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff));
294 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8));
295 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x10, u8Data);
296 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x01);
297 }
298
299 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
300 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
301
302 if (u8DMD_ATSC_DMD_ID == 0)
303 {
304 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
305 {
306 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
307 if ((u8CheckFlag&0x01)==0)
308 break;
309 MsOS_DelayTask(1);
310 }
311 }
312 else if (u8DMD_ATSC_DMD_ID == 1)
313 {
314 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
315 {
316 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase_DMD1 + 0x1E);
317 if ((u8CheckFlag&0x01)==0)
318 break;
319 MsOS_DelayTask(1);
320 }
321 }
322
323
324 if (u8CheckFlag&0x01)
325 {
326 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
327 return FALSE;
328 }
329
330 return TRUE;
331 }
332
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)333 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
334 {
335 MS_U8 u8CheckCount;
336 MS_U8 u8CheckFlag = 0xFF;
337
338 if (u8DMD_ATSC_DMD_ID == 0)
339 {
340 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
341 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
342 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
343 }
344 else if (u8DMD_ATSC_DMD_ID == 1)
345 {
346 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff));
347 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8));
348 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x02);
349 }
350
351
352 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
353 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
354
355 if (u8DMD_ATSC_DMD_ID == 0)
356 {
357 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
358 {
359 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
360 if ((u8CheckFlag&0x02)==0)
361 {
362 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
363 break;
364 }
365 MsOS_DelayTask(1);
366 }
367 }
368 else if (u8DMD_ATSC_DMD_ID == 1)
369 {
370 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
371 {
372 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase_DMD1 + 0x1E);
373 if ((u8CheckFlag&0x02)==0)
374 {
375 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase_DMD1 + 0x10);
376 break;
377 }
378 MsOS_DelayTask(1);
379 }
380 }
381
382 if (u8CheckFlag&0x02)
383 {
384 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
385 return FALSE;
386 }
387
388 return TRUE;
389 }
390
391 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_SEL_DMD(void)392 static MS_BOOL _SEL_DMD(void)
393 {
394 MS_U8 u8data = 0;
395
396 u8data = HAL_DMD_RIU_ReadByte(0x101e3c);
397
398 if (u8DMD_ATSC_DMD_ID == 0) //select DMD0
399 u8data &= (~0x10);
400 else if (u8DMD_ATSC_DMD_ID == 1) //sel DMD1
401 u8data |= 0x10;
402
403 HAL_DMD_RIU_WriteByte(0x101e3c, u8data);
404
405 return TRUE;
406 }
407 #endif
408
409 #if ((DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1) && (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3))
_initTable(void)410 static void _initTable(void)
411 {
412 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
413
414 if (pRes->sDMD_ATSC_InitData.bTunerGainInvert)
415 Demod_Flow_register[12]=1;
416 else Demod_Flow_register[12]=0;
417
418 if (pRes->sDMD_ATSC_InitData.bIQSwap)
419 Demod_Flow_register[14] = 1;
420 else Demod_Flow_register[14] = 0;
421
422 Demod_Flow_register[15] = pRes->sDMD_ATSC_InitData.u16IF_KHZ&0xFF;
423 Demod_Flow_register[16] = (pRes->sDMD_ATSC_InitData.u16IF_KHZ)>>8;
424
425 printf("\n#### IF_KHz = [%d]\n", pRes->sDMD_ATSC_InitData.u16IF_KHZ);
426 printf("\n#### IQ_SWAP = [%d]\n", pRes->sDMD_ATSC_InitData.bIQSwap);
427 printf("\n#### Tuner Gain Invert = [%d]\n", pRes->sDMD_ATSC_InitData.bTunerGainInvert);
428 }
429 #endif
430
431 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)432 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
433 {
434 printf("--------------DMD_ATSC_CHIP_T3_T10--------------\n");
435
436 // MailBox
437 HAL_DMD_RIU_WriteByte(0x100b44, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 0--> aeon
438 HAL_DMD_RIU_WriteByte(0x100b45, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 1--> aeon
439
440 // Enable DMD MCU clock (108MHz)
441 if (HAL_DMD_RIU_ReadByte(0x001ecf) == 0x00)
442 HAL_DMD_RIU_WriteByte(0x100b42, 0x10);
443 else //after t3_u02
444 HAL_DMD_RIU_WriteByte(0x100b42, 0x0D);
445
446 HAL_DMD_RIU_WriteByte(0x100b43, 0x01); // Disable VD200 clock
447
448 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
449
450 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
451
452 // Enable ATSC clock
453 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
454 HAL_DMD_RIU_WriteByte(0x103303, 0x00);
455 HAL_DMD_RIU_WriteByte(0x103304, 0x00);
456 HAL_DMD_RIU_WriteByte(0x103305, 0x00);
457 HAL_DMD_RIU_WriteByte(0x103306, 0x00);
458 HAL_DMD_RIU_WriteByte(0x103307, 0x00);
459 HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
460
461 // Enable DVB INNERx1&2 clock
462 HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
463 HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
464
465 // Enable DVB SRAM0~SRAM3 clock
466 HAL_DMD_RIU_WriteByte(0x103318, 0x00);
467 HAL_DMD_RIU_WriteByte(0x103319, 0x00);
468
469 HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
470 HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
471
472 HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
473 HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
474
475 MsOS_DelayTaskUs(1);
476
477 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
478
479 HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
480 HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
481
482 HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
483 HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
484
485 if (bRFAGCTristateEnable)
486 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
487 else
488 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
489 }
490 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)491 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
492 {
493 printf("--------------DMD_ATSC_CHIP_T7--------------\n");
494
495 HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Enable DMD MCU clock (108MHz)
496
497 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
498
499 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
500
501 // Enable ATSC clock
502 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
503 HAL_DMD_RIU_WriteByte(0x103303, 0x00);
504 HAL_DMD_RIU_WriteByte(0x103304, 0x00);
505 HAL_DMD_RIU_WriteByte(0x103305, 0x00);
506 HAL_DMD_RIU_WriteByte(0x103306, 0x00);
507 HAL_DMD_RIU_WriteByte(0x103307, 0x00);
508 HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
509
510 // Enable DVB INNERx1&2&4 clock
511 HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
512 HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
513 HAL_DMD_RIU_WriteByte(0x10330e, 0x00);
514
515 // Enable DVB OUTERx1&2&2_c clock
516 HAL_DMD_RIU_WriteByte(0x103310, 0x00);
517 HAL_DMD_RIU_WriteByte(0x103311, 0x00);
518 HAL_DMD_RIU_WriteByte(0x103312, 0x00);
519
520 // Enable DVB EQx1&8c clock
521 HAL_DMD_RIU_WriteByte(0x103316, 0x00);
522 HAL_DMD_RIU_WriteByte(0x103317, 0x00);
523
524 // Enable DVB SRAM0~SRAM3 clock
525 HAL_DMD_RIU_WriteByte(0x103318, 0x00);
526 HAL_DMD_RIU_WriteByte(0x103319, 0x00);
527
528 HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
529 HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
530
531 HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
532 HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
533
534 MsOS_DelayTaskUs(1);
535
536 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
537
538 HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
539 HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
540
541 HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
542 HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
543
544 HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
545
546 if (bRFAGCTristateEnable)
547 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
548 else
549 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
550
551 HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
552
553 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x01);
554 HAL_DMD_RIU_WriteByteMask(0x112003, 0x20, 0x20); // Release Ana misc resest
555 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x01, 0x01);
556
557 // Set DMD ANA
558 HAL_DMD_RIU_WriteByte(0x112864, 0x00); // Set VCO first and second div
559 HAL_DMD_RIU_WriteByte(0x112865, 0x00);
560
561 HAL_DMD_RIU_WriteByte(0x11286C, 0x20); // Disable T&RF-AGC
562 HAL_DMD_RIU_WriteByte(0x11286D, 0x00);
563
564 HAL_DMD_RIU_WriteByte(0x112868, 0x00);
565 HAL_DMD_RIU_WriteByte(0x112869, 0x80);
566
567 HAL_DMD_RIU_WriteByte(0x112862, 0x00); // Set PLL first and second div
568 HAL_DMD_RIU_WriteByte(0x112863, 0x00);
569
570 HAL_DMD_RIU_WriteByte(0x112818, 0x03); // ADC I&Q pown down
571 HAL_DMD_RIU_WriteByte(0x112819, 0x00);
572
573 MsOS_DelayTaskUs(2);
574
575 HAL_DMD_RIU_WriteByte(0x11286A, 0x86); // Initial MPLL procedure
576 HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
577 MsOS_DelayTaskUs(2);
578 HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
579 HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
580 MsOS_DelayTaskUs(2);
581 HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
582 HAL_DMD_RIU_WriteByte(0x11286B, 0x06);
583
584 MsOS_DelayTaskUs(2);
585
586 HAL_DMD_RIU_WriteByte(0x112866, 0x01); // Set MPLL first and second div
587 HAL_DMD_RIU_WriteByte(0x112867, 0x1d);
588
589 HAL_DMD_RIU_WriteByte(0x112860, 0x00); // MPLL power up
590 HAL_DMD_RIU_WriteByte(0x112861, 0x1c); // Set ADC output div
591
592 HAL_DMD_RIU_WriteByte(0x112802, 0x40); // Set ADC I&Q
593 HAL_DMD_RIU_WriteByte(0x112803, 0x04);
594
595 HAL_DMD_RIU_WriteByte(0x112816, 0x05); // set PGA gain
596 HAL_DMD_RIU_WriteByte(0x112817, 0x05);
597
598 HAL_DMD_RIU_WriteByte(0x112818, 0x00); // ADC I&Q pown up
599 HAL_DMD_RIU_WriteByte(0x112819, 0x00);
600
601 HAL_DMD_RIU_WriteByte(0x112840, 0x00); // Disable SIF&VIF
602 HAL_DMD_RIU_WriteByte(0x112841, 0x00);
603 }
604 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)605 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
606 {
607 printf("--------------DMD_ATSC_CHIP_T8_T9--------------\n");
608
609 HAL_DMD_RIU_WriteByte(0x10331E, 0x10); // Enable DMD MCU clock (108MHz)
610
611 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
612
613 // Enable ATSC clock
614 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
615 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
616 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
617 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
618 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
619 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
620 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
621 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
622
623 // Disable DVB INNERx1&2&4 clock
624 HAL_DMD_RIU_WriteByte(0x111f0c, 0x01);
625 HAL_DMD_RIU_WriteByte(0x111f0d, 0x01);
626 HAL_DMD_RIU_WriteByte(0x111f0e, 0x01);
627
628 // Disable DVB OUTERx1&2&2_c clock
629 HAL_DMD_RIU_WriteByte(0x111f10, 0x01);
630 HAL_DMD_RIU_WriteByte(0x111f11, 0x01);
631 HAL_DMD_RIU_WriteByte(0x111f12, 0x01);
632
633 // Disable DVB INNER clock
634 HAL_DMD_RIU_WriteByte(0x111f15, 0x01);
635
636 // Disable DVB EQx1&8c clock
637 HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
638 HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
639
640 // Enable DVB SRAM0~SRAM3 clock
641 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
642 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
643
644 HAL_DMD_RIU_WriteByte(0x103300, 0x11); // Set DMD clock div
645 HAL_DMD_RIU_WriteByte(0x103301, 0x05); // Enable DMD clock
646
647 HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
648 HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
649
650 // Disable VIF clock
651 HAL_DMD_RIU_WriteByte(0x111f1c, 0x01);
652 HAL_DMD_RIU_WriteByte(0x111f1d, 0x01);
653 HAL_DMD_RIU_WriteByte(0x10331a, 0x01);
654 HAL_DMD_RIU_WriteByte(0x10331b, 0x01);
655
656 MsOS_DelayTaskUs(1);
657
658 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
659
660 HAL_DMD_RIU_WriteByteMask(0x101eaf, 0x10, 0x18); // Set TS PAD
661
662 if (bRFAGCTristateEnable)
663 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
664 else
665 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
666
667 HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
668
669 HAL_DMD_RIU_WriteByteMask(0x101ea0, 0x00, 0x03); // PWM2 uses PAD_PWM2 and PWM3 uses PAD_PWM3
670 HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
671
672 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
673 }
674 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A1)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)675 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
676 {
677 printf("--------------DMD_ATSC_CHIP_A1--------------\n");
678
679 //Set register at CLKGEN1
680 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
681 HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Denny: change 0x10!! 108M
682
683 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
684
685 // set parallet ts clock
686 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
687 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
688
689 // enable atsc, DVBTC ts clock
690 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
691 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
692
693 // enable dvbc adc clock
694 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
695
696 // enable vif DAC clock
697 HAL_DMD_RIU_WriteByte(0x10331b, 0x00);
698 HAL_DMD_RIU_WriteByte(0x10331a, 0x00);
699
700 // Set register at CLKGEN_DMD
701 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
702 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
703 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
704 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
705 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
706 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
707
708 // enable clk_atsc_adcd_sync
709 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
710 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
711
712 // enable dvbt inner clock
713 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
714 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
715
716 // enable dvbt inner clock
717 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
718 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
719
720 // enable dvbt inner clock
721 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
722 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
723
724 // enable dvbc outer clock
725 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
726 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
727
728 // enable dvbc inner-c clock
729 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
730 HAL_DMD_RIU_WriteByte(0x111f14, 0x00);
731
732 // enable dvbc eq clock
733 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
734 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
735
736 // enable vif clock
737 HAL_DMD_RIU_WriteByte(0x111f1d, 0x00);
738 HAL_DMD_RIU_WriteByte(0x111f1c, 0x00);
739
740 // For ADC DMA Dump
741 HAL_DMD_RIU_WriteByte(0x111f21, 0x00);
742 HAL_DMD_RIU_WriteByte(0x111f20, 0x00);
743
744 // select clock
745 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
746 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
747
748 MsOS_DelayTaskUs(1);
749
750 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
751
752 // Turn TSP
753 HAL_DMD_RIU_WriteByte(0x100b55, 0x00);
754 HAL_DMD_RIU_WriteByte(0x100b54, 0x00);
755
756 // set the ts0_clk from demod
757 HAL_DMD_RIU_WriteByte(0x100b51, 0x00);
758 HAL_DMD_RIU_WriteByte(0x100b50, 0x0C);
759 HAL_DMD_RIU_WriteByte(0x101e22, 0x02);
760
761 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
762 }
763 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)764 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
765 {
766 printf("--------------DMD_ATSC_CHIP_A7--------------\n");
767
768 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
769 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
770
771 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
772
773 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
774 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
775 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
776 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
777 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
778 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
779 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
780 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
781 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
782 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
783 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
784 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
785 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
786 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
787 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
788 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
789 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
790 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
791 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
792 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
793 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
794 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
795 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
796 HAL_DMD_RIU_WriteByte(0x111f25, 0x00);
797 HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
798 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
799 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
800
801 MsOS_DelayTaskUs(1);
802
803 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
804
805 HAL_DMD_RIU_WriteByteMask(0x000e13, 0x00, 0x04);
806
807 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
808 }
809 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)810 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
811 {
812 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
813
814 printf("--------------DMD_ATSC_CHIP_K3--------------\n");
815
816 if (pRes->sDMD_ATSC_InitData.u8IS_DUAL)
817 {
818 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
819 HAL_DMD_RIU_WriteByte(0x101e3d, 0x00);
820
821 /****************DMD0****************/
822
823 //set CLK_DMDMCU as 108M Hz
824 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
825
826 // set parallet ts clock
827 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
828 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
829
830 // enable DVBTC ts clock
831 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
832
833 // enable dvbc adc clock
834 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
835 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
836
837 // enable clk_atsc_adcd_sync
838 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
839 HAL_DMD_RIU_WriteByte(0x111f0a, 0x04);
840
841 // enable dvbt inner clock
842 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
843
844 // enable dvbt outer clock
845 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
846
847 // enable dvbc outer clock
848 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
849 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
850
851 // enable dvbc inner-c clock
852 HAL_DMD_RIU_WriteByte(0x111f15, 0x04);
853
854 // enable dvbc eq clock
855 HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
856 HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
857
858 // For ADC DMA Dump
859 HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
860
861 // Turn TSP
862 //HAL_DMD_RIU_WriteByte(0x000e13, 0x01);
863
864 //set reg_allpad_in
865 HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
866 HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
867 HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
868
869 /****************DMD1****************/
870 HAL_DMD_RIU_WriteByte(0x10331f, 0x10);
871
872 HAL_DMD_RIU_WriteByte(0x103321, 0x07);
873 HAL_DMD_RIU_WriteByte(0x103320, 0x11);
874
875 HAL_DMD_RIU_WriteByte(0x103323, 0x00);
876 HAL_DMD_RIU_WriteByte(0x103322, 0x00);
877
878 HAL_DMD_RIU_WriteByte(0x11220b, 0x00);
879 HAL_DMD_RIU_WriteByte(0x11220a, 0x04);
880
881 HAL_DMD_RIU_WriteByte(0x11220c, 0x00);
882 HAL_DMD_RIU_WriteByte(0x112211, 0x00);
883
884 HAL_DMD_RIU_WriteByte(0x112213, 0x00);
885 HAL_DMD_RIU_WriteByte(0x112212, 0x00);
886
887 HAL_DMD_RIU_WriteByte(0x112215, 0x04);
888
889 HAL_DMD_RIU_WriteByte(0x112217, 0x00);
890 HAL_DMD_RIU_WriteByte(0x112216, 0x00);
891
892 HAL_DMD_RIU_WriteByte(0x112222, 0x04);
893
894 HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
895 HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
896 }
897 else
898 {
899 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
900
901 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
902 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
903
904 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
905 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
906
907 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
908
909 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
910 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
911
912 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
913 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
914
915 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
916
917 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
918
919 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
920 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
921
922 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
923
924 HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
925 HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
926
927 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
928
929 HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
930 HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
931 HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
932
933 HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
934 HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
935 }
936 }
937 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KELTIC)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)938 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
939 {
940 printf("--------------DMD_ATSC_CHIP_KELTIC--------------\n");
941
942 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
943
944 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
945 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
946
947 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
948 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
949
950 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
951
952 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
953 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
954
955 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
956 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
957
958 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
959 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
960
961 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
962
963 HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
964 HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
965
966 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
967
968 HAL_DMD_RIU_WriteByte(0x1120bc, 0x00);
969
970 HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
971 HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
972
973 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
974 }
975 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KERES)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)976 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
977 {
978 MS_U8 u8Val=0x00;
979
980 printf("--------------DMD_ATSC_CHIP_KERES--------------\n");
981
982 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
983 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
984
985 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
986 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
987 HAL_DMD_RIU_WriteByte(0x103301,0x07);
988 HAL_DMD_RIU_WriteByte(0x103300,0x11);
989 HAL_DMD_RIU_WriteByte(0x103309,0x00);
990 HAL_DMD_RIU_WriteByte(0x103315,0x00);
991 HAL_DMD_RIU_WriteByte(0x103314,0x00);
992
993 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
994 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
995 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
996 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
997 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
998 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
999 HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1000 HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1001 HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1002 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1003 HAL_DMD_RIU_WriteByte(0x111f2b,0x00); //enable clk_rs
1004 HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1005 //HAL_DMD_RIU_WriteByte(0x000e13,0x01); // No need, it cause uart issue.
1006 HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1007
1008 HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1009 HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1010
1011 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1012 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1013 }
1014 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDEN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1015 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1016 {
1017 MS_U8 u8Val = 0x00;
1018
1019 printf("--------------DMD_ATSC_CHIP_EDEN--------------\n");
1020
1021 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1022 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1023
1024 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1025 HAL_DMD_RIU_WriteByte(0x103301,0x04);
1026 HAL_DMD_RIU_WriteByte(0x103300,0x0B);
1027 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1028 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1029 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1030 HAL_DMD_RIU_WriteByte(0x103314,0x04);
1031
1032 HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1033 HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1034 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1035 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1036 HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1037 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1038 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1039 HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1040
1041 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1042 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1043 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1044 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1045
1046 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1047 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1048 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1049 HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1050 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1051 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1052 HAL_DMD_RIU_WriteByte(0x111f23,0x40);
1053 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1054
1055 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1056 HAL_DMD_RIU_WriteByte(0x101e39, (u8Val|0x03));
1057 }
1058 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EMERALD)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1059 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1060 {
1061 MS_U8 u8Val = 0x00;
1062
1063 printf("--------------DMD_ATSC_CHIP_EMERALD--------------\n");
1064
1065 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1066 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1067
1068 HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1069 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1070 HAL_DMD_RIU_WriteByte(0x103301,0x05);//Different with EDEN!
1071 HAL_DMD_RIU_WriteByte(0x103300,0x11);//Different with EDEN!
1072 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1073 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1074 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1075 HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1076
1077 HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1078 HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1079 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1080 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1081 HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1082 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1083 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1084 HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1085
1086 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1087 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1088 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1089 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1090
1091 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1092 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1093 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1094 HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1095 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1096 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1097 HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1098 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1099
1100 HAL_DMD_RIU_WriteByte(0x111f25,0x00);//Different with EDEN!
1101 HAL_DMD_RIU_WriteByte(0x111f24,0x00);//Different with EDEN!
1102 HAL_DMD_RIU_WriteByte(0x111f1E,0x00);//Different with EDEN!
1103 HAL_DMD_RIU_WriteByte(0x111f09,0x00);//Different with EDEN!
1104
1105 u8Val = HAL_DMD_RIU_ReadByte(0x000e13);
1106 HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1107
1108 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1109 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1110 }
1111 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1112 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1113 {
1114 MS_U8 u8Val = 0;
1115
1116 printf("--------------DMD_ATSC_CHIP_EINSTEIN--------------\n");
1117
1118 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1119 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1120
1121 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1122 HAL_DMD_RIU_WriteByte(0x10331e, 0x10); //Denny: change 0x10!! 108M
1123 HAL_DMD_RIU_WriteByte(0x103301, 0x05); //addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1124 HAL_DMD_RIU_WriteByte(0x103300, 0x11); //addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1125 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1126 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1127 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1128 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1129
1130 HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1131 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1132 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1133 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1134 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1135 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1136 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1137 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1138 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1139
1140 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1141 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1142 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1143 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1144
1145 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1146 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1147 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1148 HAL_DMD_RIU_WriteByte(0x111f12, 0x08); //0406 update 0->8
1149 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1150 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1151
1152 HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1153 HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1154 HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1155 HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1156 HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1157 HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1158 HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1159 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1160 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1161 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1162
1163 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1164 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1165
1166 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1167 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1168 }
1169 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1170 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1171 {
1172 MS_U8 u8Val = 0;
1173
1174 printf("--------------DMD_ATSC_CHIP_EINSTEIN3--------------\n");
1175
1176 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1177 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1178
1179 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1180 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);// Denny: change 0x10!! 108M
1181 HAL_DMD_RIU_WriteByte(0x103301, 0x05);//addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1182 HAL_DMD_RIU_WriteByte(0x103300, 0x11);//addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1183 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1184 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1185 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1186 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1187
1188 HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1189 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1190 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1191 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1192 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1193 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1194 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1195 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1196 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1197
1198 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1199 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1200 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1201 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1202
1203 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1204 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1205 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1206 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);//0406 update 0->8
1207 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1208 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1209
1210 HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1211 HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1212 HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1213 HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1214 HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1215 HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1216 HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1217 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1218 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1219 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1220
1221 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1222 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1223
1224 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1225 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1226 }
1227 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MONACO)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1228 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1229 {
1230 MS_U8 u8Val = 0;
1231
1232 printf("--------------DMD_ATSC_CHIP_MONACO--------------\n");
1233
1234 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1235 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1236
1237 // DMDMCU 108M
1238 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1239 // Set parallel TS clock
1240 // [11] : reg_ckg_demod_test_in_en = 0
1241 // 0: select internal ADC CLK
1242 // 1: select external test-in clock
1243 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1244 // 0: select gated clock
1245 // 1: select free-run clock
1246 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1247 // 0: normal phase to pad
1248 // 1: invert phase to pad
1249 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1250 // 0: select clk_dmplldiv5
1251 // 1: select clk_dmplldiv3
1252 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1253 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1254 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1255 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1256 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1257 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1258 // Enable ATSC, DVBTC TS clock
1259 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1260 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1261 // Enable ADC clock in clkgen_demod
1262 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1263 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1264 // Enable VIF DAC clock in clkgen_demod
1265 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1266 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1267 // Enable ATSC clock
1268 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1269 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1270 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1271 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1272 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1273 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1274 // Enable clk_atsc_adcd_sync = 25.41
1275 // [3:0]: reg_ckg_atsc_adcd_sync
1276 // [0] : disable clock
1277 // [1] : invert clock
1278 // [3:2]: Select clock source
1279 // 00: clk_dmdadc_sync
1280 // 01: clk_atsc50_p
1281 // ^^^^^^^^^^^^
1282 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1283 // else => clk_dmplldiv17(50.82 MHz)
1284 // 10: clk_atsc25_p
1285 // ^^^^^^^^^^^^
1286 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1287 // else => clk_dmplldiv17_div2(25.41 MHz)
1288 // 11: 1'b0
1289 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1290 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1291 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1292 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1293 // Enable DVBT inner clock
1294 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1295 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1296 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1297 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1298 // Enable DVBT outer clock
1299 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1300 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1301 // Enable DVBC outer clock
1302 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1303 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1304 // Enable SRAM clock
1305 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1306 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1307 // Enable ISDBT SRAM share clock and symbol rate clock
1308 HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1309 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1310 // select clock
1311 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1312 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1313 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1314 // [0] : disable clock
1315 // [1] : invert clock
1316 // [3:2]: Select clock source
1317 // 00: dtmb_clk288_buf(256 MHz)
1318 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1319 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1320 // 11: 1'b0
1321 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1322 // ^^^^^^^^^^
1323 // [0] : disable clock
1324 // [1] : invert clock
1325 // [3:2]: Select clock source
1326 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1327 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1328 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1329 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1330 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1331 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1332 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1333 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1334 // ^^^^^^^^^^
1335 // [0] : disable clock
1336 // [1] : invert clock
1337 // [3:2]: Select clock source
1338 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1339 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1340 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1341 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1342 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1343 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1344 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1345 // [15:12]: reg_ckg_dtmb_sram_dump
1346 // [0] : disable clock
1347 // [1] : invert clock
1348 // [3:2]: Select clock source
1349 // 00: dtmb_clk18_buf(16 MHz)
1350 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1351 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1352 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1353 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1354 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1355 HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1356 HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1357 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1358 // ^^^^^^^^^^^^^^^^^^
1359 // [0] : disable clock
1360 // [1] : invert clock
1361 // [4:2]: Select clock source
1362 // 000: adc_clk_buf
1363 // 001: clk_atsc25_p
1364 // ^^^^^^^^^^^^
1365 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1366 // else => clk_dmplldiv17_div2(25.41 MHz)
1367 // 010: clk_atsc_eq25_p
1368 // ^^^^^^^^^^^^^^^
1369 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1370 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1371 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1372 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1373 // 2'b11: 1'b0
1374 // endcase
1375 // 011: dtmb_clk72_buf(72 MHz)
1376 // 100: dtmb_clk18_buf(18 MHz)
1377 // 101: 1'b0
1378 // 110: 1'b0
1379 // 111: 1'b0
1380 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1381 // ^^^^^^^^^^^^^^^^^^^^
1382 // [0] : disable clock
1383 // [1] : invert clock
1384 // [4:2]: Select clock source
1385 // 000: clk_adc_div2_buf
1386 // 001: clk_frontend_d2_p0
1387 // ^^^^^^^^^^^^^^^^^^
1388 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1389 // else => clk_dmplldiv17_div4(12.705 MHz)
1390 // 010: clk_atsc_eq25_div2_p
1391 // ^^^^^^^^^^^^^^^^^^^^
1392 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1393 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1394 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1395 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1396 // 2'b11: 1'b0
1397 // endcase
1398 // 011: dtmb_clk36_buf(36 MHz)
1399 // 100: dtmb_clk9_buf(9 MHz)
1400 // 101: 1'b0
1401 // 110: 1'b0
1402 // 111: 1'b0
1403 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1404 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1405 HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1406 HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1407
1408 //Enable SRAM power saving
1409 HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1410 HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1411
1412 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1413 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1414 }
1415 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDISON)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1416 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1417 {
1418 MS_U8 u8Val = 0x00;
1419
1420 printf("--------------DMD_ATSC_CHIP_EDISON--------------\n");
1421
1422 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1423 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1424
1425 HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1426 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1427 HAL_DMD_RIU_WriteByte(0x103301,0x06);//Different with EDEN!
1428 HAL_DMD_RIU_WriteByte(0x103300,0x0B);//Different with EDEN!
1429 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1430 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1431 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1432 HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1433
1434 HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1435 HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1436 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1437 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1438 HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1439 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1440 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1441 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1442
1443 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1444 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1445 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1446 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1447
1448 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1449 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1450 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1451 HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1452 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1453 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1454 HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1455 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1456
1457 HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1458 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1459
1460 HAL_DMD_RIU_WriteByte(0x111F1E,0x00);
1461 HAL_DMD_RIU_WriteByte(0x111F09,0x00);
1462
1463 u8Val = HAL_DMD_RIU_ReadByte(0x000e13);
1464 HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1465
1466 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1467 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1468 }
1469 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EIFFEL)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1470 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1471 {
1472 MS_U8 u8Val = 0x00;
1473
1474 printf("--------------DMD_ATSC_CHIP_EIFFEL--------------\n");
1475
1476 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1477 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1478
1479 HAL_DMD_RIU_WriteByte(0x101e39 ,0x00);
1480 HAL_DMD_RIU_WriteByte(0x10331f ,0x00);
1481 HAL_DMD_RIU_WriteByte(0x10331e ,0x10);
1482 HAL_DMD_RIU_WriteByte(0x103301 ,0x05);
1483 HAL_DMD_RIU_WriteByte(0x103300 ,0x11);
1484 HAL_DMD_RIU_WriteByte(0x103309 ,0x00);
1485 HAL_DMD_RIU_WriteByte(0x103308 ,0x00);
1486 HAL_DMD_RIU_WriteByte(0x103315 ,0x00);
1487 HAL_DMD_RIU_WriteByte(0x103314 ,0x00);
1488 HAL_DMD_RIU_WriteByte(0x111f28 ,0x00);
1489 // HAL_DMD_RIU_WriteByte(0x112028 ,0x03);
1490 HAL_DMD_RIU_WriteByte(0x111f03 ,0x00);
1491 HAL_DMD_RIU_WriteByte(0x111f02 ,0x00);
1492 HAL_DMD_RIU_WriteByte(0x111f05 ,0x00);
1493 HAL_DMD_RIU_WriteByte(0x111f04 ,0x00);
1494 HAL_DMD_RIU_WriteByte(0x111f07 ,0x00);
1495 HAL_DMD_RIU_WriteByte(0x111f06 ,0x00);
1496 HAL_DMD_RIU_WriteByte(0x111f0b ,0x00);
1497 HAL_DMD_RIU_WriteByte(0x111f0a ,0x08);
1498 HAL_DMD_RIU_WriteByte(0x111f0d ,0x00);
1499 HAL_DMD_RIU_WriteByte(0x111f0c ,0x00);
1500 HAL_DMD_RIU_WriteByte(0x111f0f ,0x00);
1501 HAL_DMD_RIU_WriteByte(0x111f0e ,0x00);
1502 HAL_DMD_RIU_WriteByte(0x111f11 ,0x00);
1503 HAL_DMD_RIU_WriteByte(0x111f10 ,0x00);
1504 HAL_DMD_RIU_WriteByte(0x111f13 ,0x00);
1505 HAL_DMD_RIU_WriteByte(0x111f12 ,0x08);
1506 HAL_DMD_RIU_WriteByte(0x111f19 ,0x00);
1507 HAL_DMD_RIU_WriteByte(0x111f18 ,0x00);
1508 HAL_DMD_RIU_WriteByte(0x111f23 ,0x00);
1509 HAL_DMD_RIU_WriteByte(0x111f22 ,0x00);
1510
1511 u8Val = HAL_DMD_RIU_ReadByte(0x000e61);
1512 HAL_DMD_RIU_WriteByte(0x000e61, u8Val&0xFE);
1513
1514 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1515 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1516 }
1517 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MIAMI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1518 stativ void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1519 {
1520 MS_U8 u8Val = 0;
1521
1522 printf("--------------DMD_ATSC_CHIP_MIAMI--------------\n");
1523
1524 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1525 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1526
1527 // DMDMCU 108M
1528 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1529 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1530 // Set parallel TS clock
1531 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1532 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1533 // Enable ATSC, DVBTC TS clock
1534 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1535 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1536 // Enable ADC clock in clkgen_demod
1537 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1538 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1539 // Select MPLLDIV17
1540 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1541 // Enable ATSC clock
1542 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1543 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1544 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1545 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1546 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1547 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1548 // enable clk_atsc_adcd_sync
1549 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1550 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1551 // Enable DVBT inner clock
1552 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1553 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1554 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1555 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1556 // Enable DVBT outer clock
1557 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1558 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1559 // Enable DVBC outer clock
1560 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1561 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1562 // Enable SRAM clock
1563 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1564 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1565 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1566 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1567 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1568 // select clock
1569 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1570 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1571 // enable CCI LMS clock
1572 HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1573 HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1574
1575 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1576 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1577 }
1578 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUJI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1579 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1580 {
1581 MS_U8 u8Val = 0;
1582
1583 printf("--------------DMD_ATSC_CHIP_MUJI--------------\n");
1584
1585 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1586 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1587
1588 // DMDMCU 108M
1589 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1590 // Set parallel TS clock
1591 // [11] : reg_ckg_demod_test_in_en = 0
1592 // 0: select internal ADC CLK
1593 // 1: select external test-in clock
1594 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1595 // 0: select gated clock
1596 // 1: select free-run clock
1597 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1598 // 0: normal phase to pad
1599 // 1: invert phase to pad
1600 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1601 // 0: select clk_dmplldiv5
1602 // 1: select clk_dmplldiv3
1603 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1604 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1605 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1606 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1607 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1608 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1609 // Enable ATSC, DVBTC TS clock
1610 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1611 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1612 // Enable ADC clock in clkgen_demod
1613 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1614 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1615 // Reset TS divider
1616 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1617 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1618 // Enable VIF DAC clock in clkgen_demod
1619 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1620 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1621 // Enable ATSC clock
1622 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1623 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1624 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1625 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1626 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1627 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1628 // Enable clk_atsc_adcd_sync = 25.41
1629 // [3:0]: reg_ckg_atsc_adcd_sync
1630 // [0] : disable clock
1631 // [1] : invert clock
1632 // [3:2]: Select clock source
1633 // 00: clk_dmdadc_sync
1634 // 01: clk_atsc50_p
1635 // ^^^^^^^^^^^^
1636 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1637 // else => clk_dmplldiv17(50.82 MHz)
1638 // 10: clk_atsc25_p
1639 // ^^^^^^^^^^^^
1640 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1641 // else => clk_dmplldiv17_div2(25.41 MHz)
1642 // 11: 1'b0
1643 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1644 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1645 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1646 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1647 // Enable DVBT inner clock
1648 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1649 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1650 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1651 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1652 // Enable DVBT outer clock
1653 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1654 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1655 // Enable DVBC outer clock
1656 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1657 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1658 // Enable SRAM clock
1659 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1660 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1661 // Enable ISDBT SRAM share clock and symbol rate clock
1662 HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1663 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1664 // select clock
1665 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1666 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1667 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1668 // [0] : disable clock
1669 // [1] : invert clock
1670 // [3:2]: Select clock source
1671 // 00: dtmb_clk288_buf(256 MHz)
1672 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1673 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1674 // 11: 1'b0
1675 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1676 // ^^^^^^^^^^
1677 // [0] : disable clock
1678 // [1] : invert clock
1679 // [3:2]: Select clock source
1680 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1681 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1682 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1683 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1684 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1685 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1686 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1687 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1688 // ^^^^^^^^^^
1689 // [0] : disable clock
1690 // [1] : invert clock
1691 // [3:2]: Select clock source
1692 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1693 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1694 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1695 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1696 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1697 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1698 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1699 // [15:12]: reg_ckg_dtmb_sram_dump
1700 // [0] : disable clock
1701 // [1] : invert clock
1702 // [3:2]: Select clock source
1703 // 00: dtmb_clk18_buf(16 MHz)
1704 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1705 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1706 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1707 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1708 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1709 HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1710 HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1711 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1712 // ^^^^^^^^^^^^^^^^^^
1713 // [0] : disable clock
1714 // [1] : invert clock
1715 // [4:2]: Select clock source
1716 // 000: adc_clk_buf
1717 // 001: clk_atsc25_p
1718 // ^^^^^^^^^^^^
1719 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1720 // else => clk_dmplldiv17_div2(25.41 MHz)
1721 // 010: clk_atsc_eq25_p
1722 // ^^^^^^^^^^^^^^^
1723 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1724 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1725 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1726 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1727 // 2'b11: 1'b0
1728 // endcase
1729 // 011: dtmb_clk72_buf(72 MHz)
1730 // 100: dtmb_clk18_buf(18 MHz)
1731 // 101: 1'b0
1732 // 110: 1'b0
1733 // 111: 1'b0
1734 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1735 // ^^^^^^^^^^^^^^^^^^^^
1736 // [0] : disable clock
1737 // [1] : invert clock
1738 // [4:2]: Select clock source
1739 // 000: clk_adc_div2_buf
1740 // 001: clk_frontend_d2_p0
1741 // ^^^^^^^^^^^^^^^^^^
1742 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1743 // else => clk_dmplldiv17_div4(12.705 MHz)
1744 // 010: clk_atsc_eq25_div2_p
1745 // ^^^^^^^^^^^^^^^^^^^^
1746 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1747 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1748 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1749 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1750 // 2'b11: 1'b0
1751 // endcase
1752 // 011: dtmb_clk36_buf(36 MHz)
1753 // 100: dtmb_clk9_buf(9 MHz)
1754 // 101: 1'b0
1755 // 110: 1'b0
1756 // 111: 1'b0
1757 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1758 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1759 HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1760 HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1761
1762 // Muji
1763 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
1764 // [0] : disable clock
1765 // [1] : invert clock
1766 // [3:2]: Select clock source
1767 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
1768 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
1769 // sel[1]= (~reg_demod_isdbt_on)
1770 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1771 // 00: isdbt_clk6_lat(6 MHz)
1772 // 01: isdbt_clk8_lat(8 MHz)
1773 // 10: clk_dmplldiv10_div2(43.2 MHz)
1774 // 11: 1'b0
1775 // [6:4] : reg_ckg_miu_dvbtc_outer2x
1776 // [0] : disable clock
1777 // [1] : invert clock
1778 // [2] : Select clock source
1779 // 0: clk_miu_p
1780 // 1: clk_dmplldiv10(86.4 MHz)
1781 // [12:8] : reg_ckg_dvbtc_rs
1782 // [0] : disable clock
1783 // [1] : invert clock
1784 // [4:2]: Select clock source
1785 // 000: clk_dmplldiv10(86.4 MHz)
1786 // 001: clk_dmplldiv10_div2(43.2 MHz)
1787 // 010: clk_atsc50_p
1788 // ^^^^^^^^^^^^
1789 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1790 // else => clk_dmplldiv17(50.82 MHz)
1791 // 011: clk_dvbtc_rs_216_buf(216 MHz)
1792 // 100: clk_dvbtc_rs_172_buf(172 MHz)
1793 // 101: clk_dvbtc_rs_144_buf(144 MHz)
1794 // 110: 1'b0
1795 // 111: 1'b0
1796 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1797 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1798 HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
1799
1800 //Enable SRAM power saving
1801 HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1802 HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1803
1804 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1805 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1806 }
1807 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUNICH)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1808 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1809 {
1810 MS_U8 u8Val = 0;
1811
1812 printf("--------------DMD_ATSC_CHIP_MUNICH--------------\n");
1813
1814 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1815 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1816
1817 // DMDMCU 108M
1818 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1819 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1820 // Set parallel TS clock
1821 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1822 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1823 // Enable ATSC, DVBTC TS clock
1824 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1825 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1826 // Enable ADC clock in clkgen_demod
1827 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1828 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1829 // Select MPLLDIV17
1830 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1831 // Enable ATSC clock
1832 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1833 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1834 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1835 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1836 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1837 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1838 // enable clk_atsc_adcd_sync
1839 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1840 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1841 // Enable DVBT inner clock
1842 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1843 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1844 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1845 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1846 // Enable DVBT outer clock
1847 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1848 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1849 // Enable DVBC outer clock
1850 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1851 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1852 // Enable SRAM clock
1853 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1854 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1855 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1856 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1857 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1858 // select clock
1859 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1860 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1861 // enable CCI LMS clock
1862 HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1863 HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1864
1865 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1866 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1867 }
1868 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KIRIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1869 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1870 {
1871 MS_U8 u8Val=0x00;
1872
1873 printf("--------------DMD_ATSC_CHIP_KIRIN--------------\n");
1874
1875 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1876 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1877
1878 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
1879 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1880 HAL_DMD_RIU_WriteByte(0x103301,0x07);
1881 HAL_DMD_RIU_WriteByte(0x103300,0x11);
1882 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1883 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1884 HAL_DMD_RIU_WriteByte(0x103314,0x00);
1885
1886 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1887 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1888 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1889 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1890 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1891 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1892 HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1893 HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1894 HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1895 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1896 HAL_DMD_RIU_WriteByte(0x111f2b,0x00);
1897 HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1898 HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1899
1900 HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1901 HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1902
1903 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1904 HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1905 }
1906 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAYA)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1907 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1908 {
1909 MS_U8 u8Val=0x00;
1910
1911 printf("--------------DMD_ATSC_CHIP_MAYA--------------\n");
1912
1913 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1914 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1915
1916 // DMDMCU 108M
1917 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1918 // Set parallel TS clock
1919 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1920 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1921 // Enable ATSC, DVBTC TS clock
1922 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1923 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1924 // Enable ADC clock in clkgen_demod
1925 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1926 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1927 // Reset TS divider
1928 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1929 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1930 // ADC select MPLLDIV17 & EQ select MPLLDIV5
1931 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1932 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1933 // Enable ATSC clock
1934 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1935 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1936 // configure reg_ckg_atsc50, reg_ckg_atsc25, reg_ckg_atsc_eq25 and reg_ckg_atsc_ce25
1937 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1938 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1939 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1940 // enable clk_atsc_adcd_sync
1941 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1942 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1943 // Enable DVBC outer clock
1944 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1945 // Enable SRAM clock
1946 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1947 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1948 // select clock
1949 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1950 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1951 // enable CCI LMS clock
1952 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
1953 HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
1954 // set symbol rate
1955 HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1956 HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1957 // reg_ckg_adc1x_eq1x
1958 HAL_DMD_RIU_WriteByte(0x111f49, 0x04);
1959
1960 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1961 HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1962 }
1963 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MANHATTAN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1964 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1965 {
1966 MS_U8 u8Val = 0;
1967
1968 printf("--------------DMD_ATSC_CHIP_MANHATTAN--------------\n");
1969
1970 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1971 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1972
1973 // DMDMCU 108M
1974 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1975 // Set parallel TS clock
1976 // [11] : reg_ckg_demod_test_in_en = 0
1977 // 0: select internal ADC CLK
1978 // 1: select external test-in clock
1979 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1980 // 0: select gated clock
1981 // 1: select free-run clock
1982 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1983 // 0: normal phase to pad
1984 // 1: invert phase to pad
1985 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1986 // 0: select clk_dmplldiv5
1987 // 1: select clk_dmplldiv3
1988 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1989 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1990 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1991 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1992 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1993 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1994 // Enable ATSC, DVBTC TS clock
1995 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1996 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1997 // Enable ADC clock in clkgen_demod
1998 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1999 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
2000 // Reset TS divider
2001 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2002 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2003 // Enable VIF DAC clock in clkgen_demod
2004 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
2005 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
2006 // Enable ATSC clock
2007 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
2008 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
2009 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
2010 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
2011 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
2012 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
2013 // Enable clk_atsc_adcd_sync = 25.41
2014 // [3:0]: reg_ckg_atsc_adcd_sync
2015 // [0] : disable clock
2016 // [1] : invert clock
2017 // [3:2]: Select clock source
2018 // 00: clk_dmdadc_sync
2019 // 01: clk_atsc50_p
2020 // ^^^^^^^^^^^^
2021 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
2022 // else => clk_dmplldiv17(50.82 MHz)
2023 // 10: clk_atsc25_p
2024 // ^^^^^^^^^^^^
2025 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
2026 // else => clk_dmplldiv17_div2(25.41 MHz)
2027 // 11: 1'b0
2028 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
2029 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
2030 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2031 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2032 // Enable DVBT inner clock
2033 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
2034 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
2035 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
2036 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
2037 // Enable DVBT outer clock
2038 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
2039 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
2040 // Enable DVBC outer clock
2041 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
2042 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
2043 // Enable SRAM clock
2044 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
2045 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
2046 // Enable ISDBT SRAM share clock and symbol rate clock
2047 HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
2048 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
2049 // select clock
2050 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
2051 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
2052 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
2053 // [0] : disable clock
2054 // [1] : invert clock
2055 // [3:2]: Select clock source
2056 // 00: dtmb_clk288_buf(256 MHz)
2057 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
2058 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
2059 // 11: 1'b0
2060 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
2061 // ^^^^^^^^^^
2062 // [0] : disable clock
2063 // [1] : invert clock
2064 // [3:2]: Select clock source
2065 // 00: dtmb_clk18_buf(16 MHz) => DTMB
2066 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
2067 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
2068 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
2069 // ^^^^^^^^^^^^^^^^^^^^^^^^^
2070 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
2071 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
2072 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
2073 // ^^^^^^^^^^
2074 // [0] : disable clock
2075 // [1] : invert clock
2076 // [3:2]: Select clock source
2077 // 00: dtmb_clk72_buf(64 MHz) => DTMB
2078 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
2079 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
2080 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
2081 // ^^^^^^^^^^^^^^^^^^^^^^^^^
2082 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
2083 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
2084 // [15:12]: reg_ckg_dtmb_sram_dump
2085 // [0] : disable clock
2086 // [1] : invert clock
2087 // [3:2]: Select clock source
2088 // 00: dtmb_clk18_buf(16 MHz)
2089 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
2090 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
2091 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
2092 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
2093 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
2094 HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
2095 HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
2096 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
2097 // ^^^^^^^^^^^^^^^^^^
2098 // [0] : disable clock
2099 // [1] : invert clock
2100 // [4:2]: Select clock source
2101 // 000: adc_clk_buf
2102 // 001: clk_atsc25_p
2103 // ^^^^^^^^^^^^
2104 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
2105 // else => clk_dmplldiv17_div2(25.41 MHz)
2106 // 010: clk_atsc_eq25_p
2107 // ^^^^^^^^^^^^^^^
2108 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
2109 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
2110 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
2111 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
2112 // 2'b11: 1'b0
2113 // endcase
2114 // 011: dtmb_clk72_buf(72 MHz)
2115 // 100: dtmb_clk18_buf(18 MHz)
2116 // 101: 1'b0
2117 // 110: 1'b0
2118 // 111: 1'b0
2119 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
2120 // ^^^^^^^^^^^^^^^^^^^^
2121 // [0] : disable clock
2122 // [1] : invert clock
2123 // [4:2]: Select clock source
2124 // 000: clk_adc_div2_buf
2125 // 001: clk_frontend_d2_p0
2126 // ^^^^^^^^^^^^^^^^^^
2127 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
2128 // else => clk_dmplldiv17_div4(12.705 MHz)
2129 // 010: clk_atsc_eq25_div2_p
2130 // ^^^^^^^^^^^^^^^^^^^^
2131 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
2132 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
2133 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
2134 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
2135 // 2'b11: 1'b0
2136 // endcase
2137 // 011: dtmb_clk36_buf(36 MHz)
2138 // 100: dtmb_clk9_buf(9 MHz)
2139 // 101: 1'b0
2140 // 110: 1'b0
2141 // 111: 1'b0
2142 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
2143 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
2144 HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
2145 HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
2146
2147 // Muji
2148 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
2149 // [0] : disable clock
2150 // [1] : invert clock
2151 // [3:2]: Select clock source
2152 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
2153 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
2154 // sel[1]= (~reg_demod_isdbt_on)
2155 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2156 // 00: isdbt_clk6_lat(6 MHz)
2157 // 01: isdbt_clk8_lat(8 MHz)
2158 // 10: clk_dmplldiv10_div2(43.2 MHz)
2159 // 11: 1'b0
2160 // [6:4] : reg_ckg_miu_dvbtc_outer2x
2161 // [0] : disable clock
2162 // [1] : invert clock
2163 // [2] : Select clock source
2164 // 0: clk_miu_p
2165 // 1: clk_dmplldiv10(86.4 MHz)
2166 // [12:8] : reg_ckg_dvbtc_rs
2167 // [0] : disable clock
2168 // [1] : invert clock
2169 // [4:2]: Select clock source
2170 // 000: clk_dmplldiv10(86.4 MHz)
2171 // 001: clk_dmplldiv10_div2(43.2 MHz)
2172 // 010: clk_atsc50_p
2173 // ^^^^^^^^^^^^
2174 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
2175 // else => clk_dmplldiv17(50.82 MHz)
2176 // 011: clk_dvbtc_rs_216_buf(216 MHz)
2177 // 100: clk_dvbtc_rs_172_buf(172 MHz)
2178 // 101: clk_dvbtc_rs_144_buf(144 MHz)
2179 // 110: 1'b0
2180 // 111: 1'b0
2181 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
2182 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
2183 HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
2184
2185 // ================================================================
2186 // ISDBT SRAM pool clock enable
2187 // ================================================================
2188 // [3:0] : reg_ckg_share_dtmb_inner12x_isdbt_inner2x
2189 // [0] : disable clock
2190 // [1] : invert clock
2191 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2192 // 1 : clk_isdbt_inner2x_p /
2193 // 2 : clk_dtmb_inner12x_4x_dvbtc_rs_mux --------> clk_dtmb_inner12x_4x_dvbtc_rs
2194 // 3 : 1'b0
2195 // [7:4] : reg_ckg_share_dtmb_inner8x_rs_isdbt_inner2x
2196 // [0] : disable clock
2197 // [1] : invert clock
2198 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2199 // : 1 : clk_isdbt_inner2x_p /
2200 // : 2 : dtmb_clk144_buf \_________________> clk_dtmb_inner8x_dvbtc_rs, *sel[0] = reg_ckg_dtmb_inner8x_dvbtc_rs[2] | TEST_CLK_EN
2201 // : 3 : clk_dvbtc_rs_mux /
2202 // [11:8] : reg_ckg_share_dtmb_inner8x_isdbt_inner2x
2203 // [0] : disable clock
2204 // [1] : invert clock
2205 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2206 // : 1 : clk_isdbt_inner2x_p /
2207 // : 2 : dtmb_clk144_buf ------------------> clk_dtmb_inner8x
2208 // : 3 : 1'b0
2209 // [15:12] : reg_ckg_share_dtmb_outer2x_isdbt_inner2x
2210 // [0] : disable clock
2211 // [1] : invert clock
2212 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2213 // : 1 : clk_isdbt_inner2x_p /
2214 // : 2 : dtmb_eq_clk36_buf ------------------> clk_dtmb_outer2x
2215 // : 3 : 1'b0
2216 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h40, 2'b11, 16'h0000);
2217 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h40, 2'b11, 16'h0000);
2218 HAL_DMD_RIU_WriteByte(0x111f81, 0x00);
2219 HAL_DMD_RIU_WriteByte(0x111f80, 0x00);
2220
2221
2222 // [3:0] : reg_ckg_share_dtmb_inner2x_isdbt_inner2x
2223 // [0] : disable clock
2224 // [1] : invert clock
2225 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2226 // : 1 : clk_isdbt_inner2x_p /
2227 // : 2 : dtmb_clk36_buf ------------------> clk_dtmb_inner2x
2228 // : 3 : 1'b0
2229 // [7:4] : reg_ckg_share_dtmb_inner12x_isdbt_inner4x
2230 // [0] : disable clock
2231 // [1] : invert clock
2232 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_dvbtc_sram4_isdbt_inner4x, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN;
2233 // : 1 : clk_isdbt_inner4x_p /
2234 // : 2 : clk_dtmb_inner12x_4x_dvbtc_rs_mux --------> clk_dtmb_inner12x_4x_dvbtc_rs,
2235 // : 3 : 1'b0
2236 // [11:8] : reg_ckg_share_dtmb_eq2x_isdbt_outer6x
2237 // [0] : disable clock
2238 // [1] : invert clock
2239 // [3:2] : 0 : isdbt_clk36_lat \_________________> clk_isdbt_outer6x, *sel[0] = reg_ckg_isdbt_outer6x[2] | TEST_CLK_EN
2240 // : 1 : isdbt_clk48_lat /
2241 // : 2 : clk_dtmb_eq2x_inner12x_mux ---------------> clk_dtmb_eq2x_inner12x
2242 // : 3 : 1'b0
2243 // [15:12] : reg_ckg_share_dtmb_eq0p5x_isdbt_sram0
2244 // [0] : disable clock
2245 // [1] : invert clock
2246 // [3:2] : 0 : clk_dvbtc_sram0_p \_________________> clk_sram0, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN
2247 // : 1 : clk_isdbt_inner4x_p /
2248 // : 2 : dtmb_eq_clk72_buf \_________________> clk_dtmb_eq0p5x_inner4x *sel[0] = reg_ckg_dtmb_eq0p5x_inner4x[2] | extmd
2249 // : 3 : dtmb_clk72_buf /
2250 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h41, 2'b11, 16'h0000);
2251 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h41, 2'b11, 16'h0000);
2252 HAL_DMD_RIU_WriteByte(0x111f83, 0x00);
2253 HAL_DMD_RIU_WriteByte(0x111f82, 0x00);
2254
2255
2256 // [3:0] : reg_ckg_share_dtmb_eq2x_isdbt_sram1
2257 // [0] : disable clock
2258 // [1] : invert clock
2259 // [3:2] : 0 : clk_dvbtc_sram1_p \_________________> clk_sram1, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN
2260 // : 1 : clk_isdbt_inner4x_p /
2261 // : 2 : clk_dtmb_eq2x_inner2x_12x_mux ------------> clk_dtmb_eq2x_inner2x_12x
2262 // : 3 : 1'b0
2263 // [7:4] : reg_ckg_share_dtmb_inner6x_isdbt_sram3
2264 // [0] : disable clock
2265 // [1] : invert clock
2266 // [3:2] : 0 : clk_dvbtc_sram3_p \_________________> clk_sram3, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2267 // : 1 : clk_isdbt_inner2x_p /
2268 // : 2 : dtmb_clk108_buf ------------------> clk_dtmb_inner6x
2269 // : 3 : 1'b0
2270 // [11:8] : reg_ckg_share_dtmb_eq2x_isdbt_sram3
2271 // [0] : disable clock
2272 // [1] : invert clock
2273 // [3:2] : 0 : clk_dvbtc_sram3_p \_________________> clk_sram3, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2274 // : 1 : clk_isdbt_inner2x_p /
2275 // : 2 : clk_dtmb_eq2x_inner12x_mux ---------------> clk_dtmb_eq2x_inner12x
2276 // : 3 : 1'b0
2277 // [15:12] : reg_ckg_share_dtmb_inner12x_isdbt_sram4
2278 // [0] : disable clock
2279 // [1] : invert clock
2280 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2281 // : 1 : clk_isdbt_inner2x_p /
2282 // : 2 : dtmb_clk216_buf ------------------> clk_dtmb_inner12x
2283 // : 3 : 1'b0
2284 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h42, 2'b11, 16'h0000);
2285 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h42, 2'b11, 16'h0000);
2286 HAL_DMD_RIU_WriteByte(0x111f85, 0x00);
2287 HAL_DMD_RIU_WriteByte(0x111f84, 0x00);
2288
2289
2290 // [3:0] : reg_ckg_share_dtmb_inner12x_eq0p5x_isdbt_sram4
2291 // [0] : disable clock
2292 // [1] : invert clock
2293 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2294 // : 1 : clk_isdbt_inner2x_p /
2295 // : 2 : dtmb_clk216_buf \_________________> clk_dtmb_inner12x_eq0p5x, *sel[0] = reg_ckg_dtmb_inner12x_eq0p5x[2] | extmd
2296 // : 3 : dtmb_eq_clk72_buf /
2297 // [7:4] : reg_ckg_share_dtmb_eq0p25x_isdbt_sram4
2298 // [0] : disable clock
2299 // [1] : invert clock
2300 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2301 // : 1 : clk_isdbt_inner2x_p /
2302 // : 2 : dtmb_eq_clk36_buf ------------------> clk_dtmb_eq0p25x
2303 // : 3 : 1'b0
2304 // [11:8] : reg_ckg_share_dtmb_inner2x_isdbt_sram4
2305 // [0] : disable clock
2306 // [1] : invert clock
2307 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2308 // : 1 : clk_isdbt_inner2x_p /
2309 // : 2 : dtmb_clk36_buf \_________________> clk_dtmb_inner2x_dvbtc_rs, *sel[0] = reg_ckg_dtmb_inner2x_dvbtc_rs[2] | TEST_CLK_EN
2310 // : 3 : clk_dvbtc_rs_mux /
2311 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h43, 2'b11, 16'h0000);
2312 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h43, 2'b11, 16'h0000);
2313 HAL_DMD_RIU_WriteByte(0x111f87, 0x00);
2314 HAL_DMD_RIU_WriteByte(0x111f86, 0x00);
2315
2316 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
2317 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2318 }
2319 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2320 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2321 {
2322 MS_U8 u8Val = 0;
2323
2324 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MACAN--------------\n"));
2325
2326 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
2327 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2328
2329 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
2330
2331 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2332 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2333
2334 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2335 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2336
2337 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2338 HAL_DMD_RIU_WriteByte(0x103314, 0x08);
2339
2340 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2341 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2342
2343 HAL_DMD_RIU_WriteByte(0x152928, 0x00);
2344
2345 HAL_DMD_RIU_WriteByte(0x152903, 0x00);
2346 HAL_DMD_RIU_WriteByte(0x152902, 0x00);
2347
2348 HAL_DMD_RIU_WriteByte(0x152905, 0x00);
2349 HAL_DMD_RIU_WriteByte(0x152904, 0x00);
2350
2351 HAL_DMD_RIU_WriteByte(0x152907, 0x00);
2352 HAL_DMD_RIU_WriteByte(0x152906, 0x00);
2353
2354 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2355 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2356
2357 HAL_DMD_RIU_WriteByte(0x111f21, 0x44);
2358 HAL_DMD_RIU_WriteByte(0x111f20, 0x40);
2359
2360 HAL_DMD_RIU_WriteByte(0x111f23, 0x10);
2361 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
2362
2363 HAL_DMD_RIU_WriteByte(0x111f3b, 0x08);
2364 HAL_DMD_RIU_WriteByte(0x111f3a, 0x08);
2365
2366 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
2367 HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
2368
2369 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
2370 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
2371
2372 HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
2373 HAL_DMD_RIU_WriteByte(0x111f78, 0x18);
2374
2375 HAL_DMD_RIU_WriteByte(0x152991, 0x88);
2376 HAL_DMD_RIU_WriteByte(0x152990, 0x88);
2377
2378 HAL_DMD_RIU_WriteByte(0x111f69, 0x44);
2379 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
2380
2381 HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
2382 HAL_DMD_RIU_WriteByte(0x111f74, 0x11);
2383
2384 HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
2385 HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
2386
2387 HAL_DMD_RIU_WriteByte(0x15298f, 0x11);
2388 HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
2389
2390 HAL_DMD_RIU_WriteByte(0x152923, 0x00);
2391 HAL_DMD_RIU_WriteByte(0x152922, 0x00);
2392
2393 HAL_DMD_RIU_WriteByte(0x111f25, 0x10);
2394 HAL_DMD_RIU_WriteByte(0x111f24, 0x11);
2395
2396 HAL_DMD_RIU_WriteByte(0x152971, 0x1c);
2397 HAL_DMD_RIU_WriteByte(0x152970, 0xc1);
2398
2399 HAL_DMD_RIU_WriteByte(0x152977, 0x04);
2400 HAL_DMD_RIU_WriteByte(0x152976, 0x04);
2401
2402 HAL_DMD_RIU_WriteByte(0x111f6f, 0x11);
2403 HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
2404
2405 HAL_DMD_RIU_WriteByte(0x111feb, 0x18);
2406
2407 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
2408 HAL_DMD_RIU_WriteByte(0x111f7e, 0x11);
2409
2410 HAL_DMD_RIU_WriteByte(0x111f31, 0x14);
2411
2412 HAL_DMD_RIU_WriteByte(0x152981, 0x00);
2413 HAL_DMD_RIU_WriteByte(0x152980, 0x00);
2414
2415 HAL_DMD_RIU_WriteByte(0x152983, 0x00);
2416 HAL_DMD_RIU_WriteByte(0x152982, 0x00);
2417
2418 HAL_DMD_RIU_WriteByte(0x152985, 0x00);
2419 HAL_DMD_RIU_WriteByte(0x152984, 0x00);
2420
2421 HAL_DMD_RIU_WriteByte(0x152987, 0x00);
2422 HAL_DMD_RIU_WriteByte(0x152986, 0x00);
2423
2424 HAL_DMD_RIU_WriteByte(0x152979, 0x11);
2425 HAL_DMD_RIU_WriteByte(0x152978, 0x14);
2426
2427 HAL_DMD_RIU_WriteByte(0x15298d, 0x81);
2428 HAL_DMD_RIU_WriteByte(0x15298c, 0x44);
2429
2430 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
2431 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2432 }
2433 #else
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2434 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2435 {
2436 printf("--------------DMD_ATSC_CHIP_NONE--------------\n");
2437 }
2438 #endif
2439
_HAL_INTERN_ATSC_Download(void)2440 static MS_BOOL _HAL_INTERN_ATSC_Download(void)
2441 {
2442 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
2443
2444 MS_U8 udata = 0x00;
2445 MS_U16 i=0;
2446 MS_U16 fail_cnt=0;
2447 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2448 MS_U8 u8TmpData;
2449 MS_U16 u16AddressOffset;
2450 #endif
2451
2452 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
2453 if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x08) HAL_PWS_Stop_VDMCU();
2454 else
2455 {
2456 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
2457 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
2458 MsOS_DelayTask(20);
2459 return TRUE;
2460 }
2461 #else
2462 if (pRes->sDMD_ATSC_PriData.bDownloaded)
2463 {
2464 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
2465 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
2466 MsOS_DelayTask(20);
2467 return TRUE;
2468 }
2469 #endif
2470
2471 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
2472 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
2473
2474 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
2475
2476 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
2477 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
2478 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
2479 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
2480
2481 //// Load code thru VDMCU_IF ////
2482 HAL_INTERN_ATSC_DBINFO(printf(">Load Code...\n"));
2483
2484 for (i = 0; i < u16Lib_size; i++)
2485 {
2486 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, INTERN_ATSC_table[i]); // write data to VD MCU 51 code sram
2487 }
2488
2489 //// Content verification ////
2490 HAL_INTERN_ATSC_DBINFO(printf(">Verify Code...\n"));
2491
2492 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
2493 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
2494
2495 for (i = 0; i < u16Lib_size; i++)
2496 {
2497 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
2498
2499 if (udata != INTERN_ATSC_table[i])
2500 {
2501 HAL_INTERN_ATSC_DBINFO(printf(">fail add = 0x%x\n", i));
2502 HAL_INTERN_ATSC_DBINFO(printf(">code = 0x%x\n", INTERN_ATSC_table[i]));
2503 HAL_INTERN_ATSC_DBINFO(printf(">data = 0x%x\n", udata));
2504
2505 if (fail_cnt++ > 10)
2506 {
2507 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode fail!"));
2508 return FALSE;
2509 }
2510 }
2511 }
2512
2513 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2514 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2515 _initTable();
2516 #endif
2517
2518 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x80); // sram address low byte
2519 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9 || DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2520 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x6B); // sram address high byte
2521 #else
2522 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x5B); // sram address high byte
2523 #endif
2524
2525 for (i = 0; i < sizeof(Demod_Flow_register); i++)
2526 {
2527 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, Demod_Flow_register[i]);
2528 }
2529 #else // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2530 u16AddressOffset = (INTERN_ATSC_table[0x400] << 8)|INTERN_ATSC_table[0x401];
2531
2532 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
2533 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
2534
2535 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16IF_KHZ;
2536 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2537 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16IF_KHZ >> 8);
2538 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2539 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.bIQSwap;
2540 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2541 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE;
2542 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2543 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE >> 8);
2544 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2545 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u8IS_DUAL;
2546 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2547 u8TmpData = (MS_U8)u8DMD_ATSC_DMD_ID;
2548 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2549 #endif // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2550
2551 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
2552 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
2553
2554 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2555
2556 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
2557 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
2558
2559 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
2560 HAL_DMD_RIU_WriteByte(0x101E3E, 0x08); // ATSC = BIT3 -> 0x08
2561 HAL_DMD_RIU_WriteByte(0x11051C, 0x00);
2562 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
2563 HAL_DMD_RIU_WriteByte(0x11261C, 0x00);
2564 pRes->sDMD_ATSC_PriData.bDownloaded = true;
2565 #else
2566 pRes->sDMD_ATSC_PriData.bDownloaded = true;
2567 #endif
2568
2569 MsOS_DelayTask(20);
2570
2571 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode done.\n"));
2572
2573 return TRUE;
2574 }
2575
_HAL_INTERN_ATSC_FWVERSION(void)2576 static void _HAL_INTERN_ATSC_FWVERSION(void)
2577 {
2578 MS_U8 data1,data2,data3;
2579
2580 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2581 _MBX_ReadReg(0x20C4, &data1);
2582 _MBX_ReadReg(0x20C5, &data2);
2583 _MBX_ReadReg(0x20C6, &data3);
2584 #else
2585 _MBX_ReadReg(0x20C4, &data1);
2586 _MBX_ReadReg(0x20CF, &data2);
2587 _MBX_ReadReg(0x20D0, &data3);
2588 #endif
2589
2590 HAL_INTERN_ATSC_DBINFO(printf("INTERN_ATSC_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
2591 }
2592
_HAL_INTERN_ATSC_Exit(void)2593 static MS_BOOL _HAL_INTERN_ATSC_Exit(void)
2594 {
2595 MS_U8 u8CheckCount = 0;
2596
2597 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
2598
2599 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
2600 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
2601
2602 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
2603 {
2604 MsOS_DelayTaskUs(10);
2605
2606 if (u8CheckCount++ == 0xFF)
2607 {
2608 printf(">> ATSC Exit Fail!\n");
2609 return FALSE;
2610 }
2611 }
2612
2613 printf(">> ATSC Exit Ok!\n");
2614
2615 return TRUE;
2616 }
2617
_HAL_INTERN_ATSC_SoftReset(void)2618 static MS_BOOL _HAL_INTERN_ATSC_SoftReset(void)
2619 {
2620 MS_U8 u8Data = 0xFF;
2621
2622 //Reset FSM
2623 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
2624
2625 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2626 while (u8Data != 0x02)
2627 #else
2628 while (u8Data != 0x00)
2629 #endif
2630 {
2631 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
2632 }
2633
2634 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2635 //Execute demod top reset
2636 _MBX_ReadReg(0x2002, &u8Data);
2637 _MBX_WriteReg(0x2002, (u8Data|0x10));
2638 return _MBX_WriteReg(0x2002, (u8Data&(~0x10)));
2639 #else
2640 return TRUE;
2641 #endif
2642 }
2643
_HAL_INTERN_ATSC_SetVsbMode(void)2644 static MS_BOOL _HAL_INTERN_ATSC_SetVsbMode(void)
2645 {
2646 return _MBX_WriteReg(0x20C0, 0x08);
2647 }
2648
_HAL_INTERN_ATSC_Set64QamMode(void)2649 static MS_BOOL _HAL_INTERN_ATSC_Set64QamMode(void)
2650 {
2651 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2652 if (_MBX_WriteReg(0x20C3, 0x00)==FALSE) return FALSE;
2653 #endif
2654 return _MBX_WriteReg(0x20C0, 0x04);
2655 }
2656
_HAL_INTERN_ATSC_Set256QamMode(void)2657 static MS_BOOL _HAL_INTERN_ATSC_Set256QamMode(void)
2658 {
2659 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2660 if (_MBX_WriteReg(0x20C3, 0x01)==FALSE) return FALSE;
2661 #endif
2662 return _MBX_WriteReg(0x20C0, 0x04);
2663 }
2664
_HAL_INTERN_ATSC_SetModeClean(void)2665 static MS_BOOL _HAL_INTERN_ATSC_SetModeClean(void)
2666 {
2667 return _MBX_WriteReg(0x20C0, 0x00);
2668 }
2669
_HAL_INTERN_ATSC_Check8VSB64_256QAM(void)2670 static DMD_ATSC_DEMOD_TYPE _HAL_INTERN_ATSC_Check8VSB64_256QAM(void)
2671 {
2672 MS_U8 mode = 0;
2673
2674 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2675 _MBX_ReadReg(0x2A02, &mode); //EQ mode check
2676
2677 mode &= 0x07;
2678
2679 if (mode == QAM16_J83ABC) return DMD_ATSC_DEMOD_ATSC_16QAM;
2680 else if (mode == QAM32_J83ABC) return DMD_ATSC_DEMOD_ATSC_32QAM;
2681 else if (mode == QAM64_J83ABC) return DMD_ATSC_DEMOD_ATSC_64QAM;
2682 else if (mode == QAM128_J83ABC) return DMD_ATSC_DEMOD_ATSC_128QAM;
2683 else if (mode == QAM256_J83ABC) return DMD_ATSC_DEMOD_ATSC_256QAM;
2684 else return DMD_ATSC_DEMOD_ATSC_256QAM;
2685 #else
2686 _MBX_ReadReg(0x1700, &mode); //mode check
2687
2688 if ((mode&VSB_ATSC) == VSB_ATSC) return DMD_ATSC_DEMOD_ATSC_VSB;
2689 else if ((mode & QAM256_ATSC) == QAM256_ATSC) return DMD_ATSC_DEMOD_ATSC_256QAM;
2690 else return DMD_ATSC_DEMOD_ATSC_64QAM;
2691 #endif
2692 }
2693
_HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)2694 static MS_BOOL _HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)
2695 {
2696 MS_U8 data1 = 0;
2697
2698 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2699 _MBX_ReadReg(0x2829, &data1); //AGC_LOCK
2700 #else
2701 _MBX_ReadReg(0x293A, &data1); //AGC_LOCK
2702 #endif
2703
2704 if(data1&0x01)
2705 {
2706 return TRUE;
2707 }
2708 else
2709 {
2710 return FALSE;
2711 }
2712 }
2713
_HAL_INTERN_ATSC_Vsb_PreLock(void)2714 static MS_BOOL _HAL_INTERN_ATSC_Vsb_PreLock(void)
2715 {
2716 MS_U8 data1 = 0;
2717 MS_U8 data2 = 0;
2718 MS_U16 checkValue;
2719
2720 _MBX_ReadReg(0x20C2, &data1); //<0>TR_LOCK, <1>PTK_LOCK
2721
2722 if ((data1&0x02) == 0x02)
2723 {
2724 _MBX_ReadReg(0x18EA, &data1);
2725 _MBX_ReadReg(0x18EB, &data2);
2726
2727 checkValue = data1 << 8;
2728 checkValue |= data2;
2729
2730 HAL_INTERN_ATSC_DBINFO(printf("Internal Pre Locking time :[%d]ms\n",checkValue));
2731
2732 return TRUE;
2733 }
2734 else
2735 {
2736 HAL_INTERN_ATSC_DBINFO(printf("\nPreLock - FALSE"));
2737
2738 return FALSE;
2739 }
2740 }
2741
_HAL_INTERN_ATSC_Vsb_FSync_Lock(void)2742 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FSync_Lock(void)
2743 {
2744 MS_U8 data1 = 0;
2745 MS_U8 data2 = 0;
2746 MS_U16 checkValue;
2747
2748 _MBX_ReadReg(0x1824, &data1); //<4>1:Field Sync lock = Fsync lock
2749
2750 if ((data1&0x10) == 0x10)
2751 {
2752 _MBX_ReadReg(0x18EE, &data1);
2753 _MBX_ReadReg(0x18EF, &data2);
2754
2755 checkValue = data1 << 8;
2756 checkValue |= data2;
2757
2758 HAL_INTERN_ATSC_DBINFO(printf("Internal Fsync Locking time :[%d]ms\n",checkValue));
2759
2760 return TRUE;
2761 }
2762 else
2763 {
2764 HAL_INTERN_ATSC_DBINFO(printf("\nFsync Lock - FALSE"));
2765
2766 return FALSE;
2767 }
2768 }
2769
_HAL_INTERN_ATSC_Vsb_CE_Lock(void)2770 static MS_BOOL _HAL_INTERN_ATSC_Vsb_CE_Lock(void)
2771 {
2772 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2773 return TRUE;
2774 #else
2775 MS_U8 data1 = 0;
2776
2777 _MBX_ReadReg(0x20C2, &data1); //<4>1:CE Search Fail
2778
2779 if((data1&0x10) == 0)
2780 {
2781 HAL_INTERN_ATSC_DBINFO(printf("\nCE Lock"));
2782 return TRUE;
2783 }
2784 else
2785 {
2786 HAL_INTERN_ATSC_DBINFO(printf("\nCE unLock"));
2787 return FALSE;
2788 }
2789 #endif
2790 }
2791
_HAL_INTERN_ATSC_Vsb_FEC_Lock(void)2792 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FEC_Lock(void)
2793 {
2794 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0;
2795 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2796 MS_U8 data6 =0, data7 = 0;
2797 #endif
2798
2799 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2800 _MBX_ReadReg(0x20C1, &data1);
2801 _MBX_ReadReg(0x1A17, &data2);//AD_NOISE_PWR_TRAIN1
2802 _MBX_ReadReg(0x20C2, &data3);//<0>TR_LOCK, <1>PTK_LOCK
2803 _MBX_ReadReg(0x1901, &data4);//FEC_EN_CTL
2804 _MBX_ReadReg(0x1C67, &data5);//addy
2805 _MBX_ReadReg(0x1F01, &data6);
2806 _MBX_ReadReg(0x1F40, &data7);
2807
2808 //Driver update 0426 :suggestion for field claim
2809 if (data1==INTERN_ATSC_OUTER_STATE &&
2810 ((data2<=INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
2811 ((data3&0x02)==0x02) &&
2812 ((data4&INTERN_ATSC_FEC_ENABLE)==INTERN_ATSC_FEC_ENABLE) &&
2813 ((data6&0x10) == 0x10) && ((data7&0x01) == 0x01))
2814 {
2815 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
2816 return TRUE;
2817 }
2818 else
2819 {
2820 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
2821 return FALSE;
2822 }
2823 #else
2824 _MBX_ReadReg(0x20C1, &data1);
2825 _MBX_ReadReg(0x2C17, &data2); //AD_NOISE_PWR_TRAIN1 (DFS)
2826 _MBX_ReadReg(0x20C2, &data3); //<0>TR_LOCK, <1>PTK_LOCK
2827 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
2828 _MBX_ReadReg(0x2C15, &data5); //AD_NOISE_PWR_TRAIN1 (DSS)
2829
2830 if ((data1 == INTERN_ATSC_OUTER_STATE) &&
2831 ((data2 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
2832 ((data3&0x02)==0x02) &&
2833 ((data4&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE))
2834 {
2835 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
2836 return TRUE;
2837 }
2838 else
2839 {
2840 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
2841 return FALSE;
2842 }
2843 #endif
2844 }
2845
_HAL_INTERN_ATSC_QAM_PreLock(void)2846 static MS_BOOL _HAL_INTERN_ATSC_QAM_PreLock(void)
2847 {
2848 MS_U8 data1 = 0;
2849
2850 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2851 _MBX_ReadReg(0x2950, &data1); //TR_LOCK
2852 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2853 _MBX_ReadReg(0x1B15, &data1); //TR_LOCK
2854 #else
2855 _MBX_ReadReg(0x2921, &data1); //TR_LOCK
2856 #endif
2857
2858 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2859 if (data1&0x01)
2860 {
2861 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
2862 return TRUE;
2863 }
2864 else
2865 {
2866 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
2867 return FALSE;
2868 }
2869 #else
2870 if((data1&0x10) == 0x10)
2871 {
2872 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
2873 return TRUE;
2874 }
2875 else
2876 {
2877 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
2878 return FALSE;
2879 }
2880 #endif
2881 }
2882
_HAL_INTERN_ATSC_QAM_Main_Lock(void)2883 static MS_BOOL _HAL_INTERN_ATSC_QAM_Main_Lock(void)
2884 {
2885 #if DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1
2886 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0, data6=0;
2887 #else
2888 MS_U8 data1=0, data4=0, data5=0, data6=0;
2889 #endif
2890
2891 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2892 _MBX_ReadReg(0x20C1, &data1);
2893 _MBX_ReadReg(0x2B18, &data2); //boundary detected
2894 _MBX_ReadReg(0x2950, &data3); //TR_LOCK
2895 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
2896 _MBX_ReadReg(0x2101, &data5); //RS_backend
2897 _MBX_ReadReg(0x2140, &data6); //RS_backend
2898
2899 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
2900 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x01) ==0x01 &&
2901 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
2902 {
2903 return TRUE;
2904 }
2905 else
2906 {
2907 return FALSE;
2908 }
2909 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2910 _MBX_ReadReg(0x20C1, &data1);
2911 _MBX_ReadReg(0x1918, &data2); //boundary detected
2912 _MBX_ReadReg(0x1B15, &data3); //TR_LOCK
2913 _MBX_ReadReg(0x1901, &data4); //FEC_EN_CTL
2914 _MBX_ReadReg(0x1F01, &data5);
2915 _MBX_ReadReg(0x1F40, &data6);
2916
2917 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
2918 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x10)==0x10 &&
2919 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
2920 {
2921 return TRUE;
2922 }
2923 else
2924 {
2925 return FALSE;
2926 }
2927 #else
2928 _MBX_ReadReg(0x2B18, &data4); //boundary detected
2929 _MBX_ReadReg(0x2B01, &data5); //FEC_EN_CTL
2930 _MBX_ReadReg(0x2921, &data6); //TR_LOCK
2931 _MBX_ReadReg(0x20C1, &data1);
2932
2933 if (data1==INTERN_ATSC_OUTER_STATE && (data4&0x01) == 0x01 &&
2934 (data5&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE &&
2935 (data6&0x10) == 0x10)
2936 {
2937 return TRUE;
2938 }
2939 else
2940 {
2941 return FALSE;
2942 }
2943 #endif
2944 }
2945
_HAL_INTERN_ATSC_ReadIFAGC(void)2946 static MS_U8 _HAL_INTERN_ATSC_ReadIFAGC(void)
2947 {
2948 MS_U8 data = 0;
2949
2950 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2951 _MBX_ReadReg(0x2726, ((MS_U8*)(&data))+1); //reg_frontend
2952 _MBX_ReadReg(0x2727, (MS_U8*)(&data));
2953 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2954 _MBX_ReadReg(0x280F, &data);
2955 #endif
2956
2957 return data;
2958 }
2959
_HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION * pstatus)2960 static void _HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION* pstatus)
2961 {
2962 DMD_ATSC_DEMOD_TYPE eMode;
2963 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2964 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
2965 static MS_U8 u8NoisePowerL_Last = 0xff;
2966 #else
2967 MS_U8 u8NoisePowerH=0;
2968 #endif
2969 static MS_U8 u8NoisePowerH_Last = 0xff;
2970
2971 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
2972
2973 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2974 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
2975 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
2976 #else
2977 _MBX_ReadReg(0x1A15, &u8NoisePowerH);
2978 #endif
2979
2980 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
2981 {
2982 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) u8NoisePowerH=0xFF;
2983 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
2984 u8NoisePowerH_Last = u8NoisePowerH;
2985 else u8NoisePowerH = u8NoisePowerH_Last;
2986
2987 if (u8NoisePowerH > 0xBE) //SNR<14.5
2988 *pstatus=DMD_ATSC_SIGNAL_NO;
2989 else if (u8NoisePowerH > 0x4D) //SNR<18.4
2990 *pstatus=DMD_ATSC_SIGNAL_WEAK;
2991 else if (u8NoisePowerH > 0x23) //SNR<21.8
2992 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
2993 else if (u8NoisePowerH > 0x0A) //SNR<26.9
2994 *pstatus=DMD_ATSC_SIGNAL_STRONG;
2995 else
2996 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
2997 }
2998 else //QAM MODE
2999 {
3000 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3001 if (!_HAL_INTERN_ATSC_QAM_Main_Lock() || u8NoisePowerH) u8NoisePowerL=0xFF;
3002 else if (abs(u8NoisePowerL_Last-u8NoisePowerL) > 5)
3003 u8NoisePowerL_Last = u8NoisePowerL;
3004 else u8NoisePowerL = u8NoisePowerL_Last;
3005
3006 //SNR=10*log10(65536/noisepower)
3007 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM)
3008 {
3009 if (u8NoisePowerL > 0x71) //SNR<27.6
3010 *pstatus=DMD_ATSC_SIGNAL_NO;
3011 else if (u8NoisePowerL > 0x31) //SNR<31.2
3012 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3013 else if (u8NoisePowerL > 0x25) //SNR<32.4
3014 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3015 else if (u8NoisePowerL > 0x17) //SNR<34.4
3016 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3017 else
3018 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3019 }
3020 else
3021 {
3022 if (u8NoisePowerL > 0x1D) //SNR<21.5
3023 *pstatus=DMD_ATSC_SIGNAL_NO;
3024 else if (u8NoisePowerL > 0x14) //SNR<25.4
3025 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3026 else if (u8NoisePowerL > 0x0F) //SNR<27.8
3027 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3028 else if (u8NoisePowerL > 0x0B) //SNR<31.4
3029 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3030 else
3031 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3032 }
3033 #else
3034 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) u8NoisePowerH=0xFF;
3035 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
3036 u8NoisePowerH_Last = u8NoisePowerH;
3037 else u8NoisePowerH = u8NoisePowerH_Last;
3038
3039 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//SNR=10*log10((2720<<10)/noisepower)
3040 {
3041 if (u8NoisePowerH > 0x13) //SNR<27.5
3042 *pstatus=DMD_ATSC_SIGNAL_NO;
3043 else if (u8NoisePowerH > 0x08) //SNR<31.2
3044 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3045 else if (u8NoisePowerH > 0x06) //SNR<32.4
3046 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3047 else if (u8NoisePowerH > 0x04) //SNR<34.2
3048 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3049 else
3050 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3051 }
3052 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
3053 {
3054 if (u8NoisePowerH > 0x4C) //SNR<21.5
3055 *pstatus=DMD_ATSC_SIGNAL_NO;
3056 else if (u8NoisePowerH > 0x1F) //SNR<25.4
3057 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3058 else if (u8NoisePowerH > 0x11) //SNR<27.8
3059 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3060 else if (u8NoisePowerH > 0x07) //SNR<31.4
3061 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3062 else
3063 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3064 }
3065 #endif
3066 }
3067 }
3068
_HAL_INTERN_ATSC_ReadSNRPercentage(void)3069 static MS_U8 _HAL_INTERN_ATSC_ReadSNRPercentage(void)
3070 {
3071 DMD_ATSC_DEMOD_TYPE eMode;
3072 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
3073 MS_U16 u16NoisePower;
3074
3075 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3076
3077 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3078 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
3079 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
3080 #else
3081 _MBX_ReadReg(0x1A14, &u8NoisePowerL);
3082 _MBX_ReadReg(0x1A15, &u8NoisePowerH);
3083 #endif
3084
3085 u16NoisePower = (u8NoisePowerH<<8) | u8NoisePowerL;
3086
3087 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
3088 {
3089 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock())
3090 return 0;//SNR=0;
3091 else if (u16NoisePower<=0x008A)//SNR>=40dB
3092 return 100;//SNR=MAX_SNR;
3093 else if (u16NoisePower<=0x0097)//SNR>=39.6dB
3094 return 99;//
3095 else if (u16NoisePower<=0x00A5)//SNR>=39.2dB
3096 return 98;//
3097 else if (u16NoisePower<=0x00B5)//SNR>=38.8dB
3098 return 97;//
3099 else if (u16NoisePower<=0x00C7)//SNR>=38.4dB
3100 return 96;//
3101 else if (u16NoisePower<=0x00DA)//SNR>=38.0dB
3102 return 95;//
3103 else if (u16NoisePower<=0x00EF)//SNR>=37.6dB
3104 return 94;//
3105 else if (u16NoisePower<=0x0106)//SNR>=37.2dB
3106 return 93;//
3107 else if (u16NoisePower<=0x0120)//SNR>=36.8dB
3108 return 92;//
3109 else if (u16NoisePower<=0x013B)//SNR>=36.4dB
3110 return 91;//
3111 else if (u16NoisePower<=0x015A)//SNR>=36.0dB
3112 return 90;//
3113 else if (u16NoisePower<=0x017B)//SNR>=35.6dB
3114 return 89;//
3115 else if (u16NoisePower<=0x01A0)//SNR>=35.2dB
3116 return 88;//
3117 else if (u16NoisePower<=0x01C8)//SNR>=34.8dB
3118 return 87;//
3119 else if (u16NoisePower<=0x01F4)//SNR>=34.4dB
3120 return 86;//
3121 else if (u16NoisePower<=0x0224)//SNR>=34.0dB
3122 return 85;//
3123 else if (u16NoisePower<=0x0259)//SNR>=33.6dB
3124 return 84;//
3125 else if (u16NoisePower<=0x0293)//SNR>=33.2dB
3126 return 83;//
3127 else if (u16NoisePower<=0x02D2)//SNR>=32.8dB
3128 return 82;//
3129 else if (u16NoisePower<=0x0318)//SNR>=32.4dB
3130 return 81;//
3131 else if (u16NoisePower<=0x0364)//SNR>=32.0dB
3132 return 80;//
3133 else if (u16NoisePower<=0x03B8)//SNR>=31.6dB
3134 return 79;//
3135 else if (u16NoisePower<=0x0414)//SNR>=31.2dB
3136 return 78;//
3137 else if (u16NoisePower<=0x0479)//SNR>=30.8dB
3138 return 77;//
3139 else if (u16NoisePower<=0x04E7)//SNR>=30.4dB
3140 return 76;//
3141 else if (u16NoisePower<=0x0560)//SNR>=30.0dB
3142 return 75;//
3143 else if (u16NoisePower<=0x05E5)//SNR>=29.6dB
3144 return 74;//
3145 else if (u16NoisePower<=0x0677)//SNR>=29.2dB
3146 return 73;//
3147 else if (u16NoisePower<=0x0716)//SNR>=28.8dB
3148 return 72;//
3149 else if (u16NoisePower<=0x07C5)//SNR>=28.4dB
3150 return 71;//
3151 else if (u16NoisePower<=0x0885)//SNR>=28.0dB
3152 return 70;//
3153 else if (u16NoisePower<=0x0958)//SNR>=27.6dB
3154 return 69;//
3155 else if (u16NoisePower<=0x0A3E)//SNR>=27.2dB
3156 return 68;//
3157 else if (u16NoisePower<=0x0B3B)//SNR>=26.8dB
3158 return 67;//
3159 else if (u16NoisePower<=0x0C51)//SNR>=26.4dB
3160 return 66;//
3161 else if (u16NoisePower<=0x0D81)//SNR>=26.0dB
3162 return 65;//
3163 else if (u16NoisePower<=0x0ECF)//SNR>=25.6dB
3164 return 64;//
3165 else if (u16NoisePower<=0x103C)//SNR>=25.2dB
3166 return 63;//
3167 else if (u16NoisePower<=0x11CD)//SNR>=24.8dB
3168 return 62;//
3169 else if (u16NoisePower<=0x1385)//SNR>=24.4dB
3170 return 61;//
3171 else if (u16NoisePower<=0x1567)//SNR>=24.0dB
3172 return 60;//
3173 else if (u16NoisePower<=0x1778)//SNR>=23.6dB
3174 return 59;//
3175 else if (u16NoisePower<=0x19BB)//SNR>=23.2dB
3176 return 58;//
3177 else if (u16NoisePower<=0x1C37)//SNR>=22.8dB
3178 return 57;//
3179 else if (u16NoisePower<=0x1EF0)//SNR>=22.4dB
3180 return 56;//
3181 else if (u16NoisePower<=0x21EC)//SNR>=22.0dB
3182 return 55;//
3183 else if (u16NoisePower<=0x2531)//SNR>=21.6dB
3184 return 54;//
3185 else if (u16NoisePower<=0x28C8)//SNR>=21.2dB
3186 return 53;//
3187 else if (u16NoisePower<=0x2CB7)//SNR>=20.8dB
3188 return 52;//
3189 else if (u16NoisePower<=0x3108)//SNR>=20.4dB
3190 return 51;//
3191 else if (u16NoisePower<=0x35C3)//SNR>=20.0dB
3192 return 50;//
3193 else if (u16NoisePower<=0x3AF2)//SNR>=19.6dB
3194 return 49;//
3195 else if (u16NoisePower<=0x40A2)//SNR>=19.2dB
3196 return 48;//
3197 else if (u16NoisePower<=0x46DF)//SNR>=18.8dB
3198 return 47;//
3199 else if (u16NoisePower<=0x4DB5)//SNR>=18.4dB
3200 return 46;//
3201 else if (u16NoisePower<=0x5534)//SNR>=18.0dB
3202 return 45;//
3203 else if (u16NoisePower<=0x5D6D)//SNR>=17.6dB
3204 return 44;//
3205 else if (u16NoisePower<=0x6670)//SNR>=17.2dB
3206 return 43;//
3207 else if (u16NoisePower<=0x7052)//SNR>=16.8dB
3208 return 42;//
3209 else if (u16NoisePower<=0x7B28)//SNR>=16.4dB
3210 return 41;//
3211 else if (u16NoisePower<=0x870A)//SNR>=16.0dB
3212 return 40;//
3213 else if (u16NoisePower<=0x9411)//SNR>=15.6dB
3214 return 39;//
3215 else if (u16NoisePower<=0xA25A)//SNR>=15.2dB
3216 return 38;//
3217 else if (u16NoisePower<=0xB204)//SNR>=14.8dB
3218 return 37;//
3219 else if (u16NoisePower<=0xC331)//SNR>=14.4dB
3220 return 36;//
3221 else if (u16NoisePower<=0xD606)//SNR>=14.0dB
3222 return 35;//
3223 else if (u16NoisePower<=0xEAAC)//SNR>=13.6dB
3224 return 34;//
3225 else// if (u16NoisePower>=0xEAAC)//SNR<13.6dB
3226 return 33;//
3227 }
3228 else //QAM MODE
3229 {
3230 if( eMode == DMD_ATSC_DEMOD_ATSC_256QAM ) //256QAM//SNR=10*log10((2720<<10)/noisepower)
3231 {
3232 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
3233 return 0;//SNR=0;
3234 else if (u16NoisePower<=0x0117)//SNR>=40dB
3235 return 100;//
3236 else if (u16NoisePower<=0x0131)//SNR>=39.6dB
3237 return 99;//
3238 else if (u16NoisePower<=0x014F)//SNR>=39.2dB
3239 return 98;//
3240 else if (u16NoisePower<=0x016F)//SNR>=38.8dB
3241 return 97;//
3242 else if (u16NoisePower<=0x0193)//SNR>=38.4dB
3243 return 96;//
3244 else if (u16NoisePower<=0x01B9)//SNR>=38.0dB
3245 return 95;//
3246 else if (u16NoisePower<=0x01E4)//SNR>=37.6dB
3247 return 94;//
3248 else if (u16NoisePower<=0x0213)//SNR>=37.2dB
3249 return 93;//
3250 else if (u16NoisePower<=0x0246)//SNR>=36.8dB
3251 return 92;//
3252 else if (u16NoisePower<=0x027E)//SNR>=36.4dB
3253 return 91;//
3254 else if (u16NoisePower<=0x02BC)//SNR>=36.0dB
3255 return 90;//
3256 else if (u16NoisePower<=0x02FF)//SNR>=35.6dB
3257 return 89;//
3258 else if (u16NoisePower<=0x0349)//SNR>=35.2dB
3259 return 88;//
3260 else if (u16NoisePower<=0x039A)//SNR>=34.8dB
3261 return 87;//
3262 else if (u16NoisePower<=0x03F3)//SNR>=34.4dB
3263 return 86;//
3264 else if (u16NoisePower<=0x0455)//SNR>=34.0dB
3265 return 85;//
3266 else if (u16NoisePower<=0x04C0)//SNR>=33.6dB
3267 return 84;//
3268 else if (u16NoisePower<=0x0535)//SNR>=33.2dB
3269 return 83;//
3270 else if (u16NoisePower<=0x05B6)//SNR>=32.8dB
3271 return 82;//
3272 else if (u16NoisePower<=0x0643)//SNR>=32.4dB
3273 return 81;//
3274 else if (u16NoisePower<=0x06DD)//SNR>=32.0dB
3275 return 80;//
3276 else if (u16NoisePower<=0x0787)//SNR>=31.6dB
3277 return 79;//
3278 else if (u16NoisePower<=0x0841)//SNR>=31.2dB
3279 return 78;//
3280 else if (u16NoisePower<=0x090D)//SNR>=30.8dB
3281 return 77;//
3282 else if (u16NoisePower<=0x09EC)//SNR>=30.4dB
3283 return 76;//
3284 else if (u16NoisePower<=0x0AE1)//SNR>=30.0dB
3285 return 75;//
3286 else if (u16NoisePower<=0x0BEE)//SNR>=29.6dB
3287 return 74;//
3288 else if (u16NoisePower<=0x0D15)//SNR>=29.2dB
3289 return 73;//
3290 else if (u16NoisePower<=0x0E58)//SNR>=28.8dB
3291 return 72;//
3292 else if (u16NoisePower<=0x0FBA)//SNR>=28.4dB
3293 return 71;//
3294 else if (u16NoisePower<=0x113E)//SNR>=28.0dB
3295 return 70;//
3296 else if (u16NoisePower<=0x12E8)//SNR>=27.6dB
3297 return 69;//
3298 else if (u16NoisePower<=0x14BB)//SNR>=27.2dB
3299 return 68;//
3300 else if (u16NoisePower<=0x16BB)//SNR>=26.8dB
3301 return 67;//
3302 else if (u16NoisePower<=0x18ED)//SNR>=26.4dB
3303 return 66;//
3304 else if (u16NoisePower<=0x1B54)//SNR>=26.0dB
3305 return 65;//
3306 else if (u16NoisePower<=0x1DF7)//SNR>=25.6dB
3307 return 64;//
3308 else if (u16NoisePower<=0x20DB)//SNR>=25.2dB
3309 return 63;//
3310 else if (u16NoisePower<=0x2407)//SNR>=24.8dB
3311 return 62;//
3312 else if (u16NoisePower<=0x2781)//SNR>=24.4dB
3313 return 61;//
3314 else if (u16NoisePower<=0x2B50)//SNR>=24.0dB
3315 return 60;//
3316 else if (u16NoisePower<=0x2F7E)//SNR>=23.6dB
3317 return 59;//
3318 else if (u16NoisePower<=0x3413)//SNR>=23.2dB
3319 return 58;//
3320 else if (u16NoisePower<=0x3919)//SNR>=22.8dB
3321 return 57;//
3322 else if (u16NoisePower<=0x3E9C)//SNR>=22.4dB
3323 return 56;//
3324 else if (u16NoisePower<=0x44A6)//SNR>=22.0dB
3325 return 55;//
3326 else if (u16NoisePower<=0x4B45)//SNR>=21.6dB
3327 return 54;//
3328 else if (u16NoisePower<=0x5289)//SNR>=21.2dB
3329 return 53;//
3330 else if (u16NoisePower<=0x5A7F)//SNR>=20.8dB
3331 return 52;//
3332 else if (u16NoisePower<=0x633A)//SNR>=20.4dB
3333 return 51;//
3334 else if (u16NoisePower<=0x6CCD)//SNR>=20.0dB
3335 return 50;//
3336 else if (u16NoisePower<=0x774C)//SNR>=19.6dB
3337 return 49;//
3338 else if (u16NoisePower<=0x82CE)//SNR>=19.2dB
3339 return 48;//
3340 else if (u16NoisePower<=0x8F6D)//SNR>=18.8dB
3341 return 47;//
3342 else if (u16NoisePower<=0x9D44)//SNR>=18.4dB
3343 return 46;//
3344 else if (u16NoisePower<=0xAC70)//SNR>=18.0dB
3345 return 45;//
3346 else if (u16NoisePower<=0xBD13)//SNR>=17.6dB
3347 return 44;//
3348 else if (u16NoisePower<=0xCF50)//SNR>=17.2dB
3349 return 43;//
3350 else if (u16NoisePower<=0xE351)//SNR>=16.8dB
3351 return 42;//
3352 else if (u16NoisePower<=0xF93F)//SNR>=16.4dB
3353 return 41;//
3354 else// if (u16NoisePower>=0xF93F)//SNR<16.4dB
3355 return 40;//
3356 }
3357 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
3358 {
3359 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
3360 return 0;//SNR=0;
3361 else if (u16NoisePower<=0x0113)//SNR>=40dB
3362 return 100;//
3363 else if (u16NoisePower<=0x012E)//SNR>=39.6dB
3364 return 99;//
3365 else if (u16NoisePower<=0x014B)//SNR>=39.2dB
3366 return 98;//
3367 else if (u16NoisePower<=0x016B)//SNR>=38.8dB
3368 return 97;//
3369 else if (u16NoisePower<=0x018E)//SNR>=38.4dB
3370 return 96;//
3371 else if (u16NoisePower<=0x01B4)//SNR>=38.0dB
3372 return 95;//
3373 else if (u16NoisePower<=0x01DE)//SNR>=37.6dB
3374 return 94;//
3375 else if (u16NoisePower<=0x020C)//SNR>=37.2dB
3376 return 93;//
3377 else if (u16NoisePower<=0x023F)//SNR>=36.8dB
3378 return 92;//
3379 else if (u16NoisePower<=0x0277)//SNR>=36.4dB
3380 return 91;//
3381 else if (u16NoisePower<=0x02B3)//SNR>=36.0dB
3382 return 90;//
3383 else if (u16NoisePower<=0x02F6)//SNR>=35.6dB
3384 return 89;//
3385 else if (u16NoisePower<=0x033F)//SNR>=35.2dB
3386 return 88;//
3387 else if (u16NoisePower<=0x038F)//SNR>=34.8dB
3388 return 87;//
3389 else if (u16NoisePower<=0x03E7)//SNR>=34.4dB
3390 return 86;//
3391 else if (u16NoisePower<=0x0448)//SNR>=34.0dB
3392 return 85;//
3393 else if (u16NoisePower<=0x04B2)//SNR>=33.6dB
3394 return 84;//
3395 else if (u16NoisePower<=0x0525)//SNR>=33.2dB
3396 return 83;//
3397 else if (u16NoisePower<=0x05A5)//SNR>=32.8dB
3398 return 82;//
3399 else if (u16NoisePower<=0x0630)//SNR>=32.4dB
3400 return 81;//
3401 else if (u16NoisePower<=0x06C9)//SNR>=32.0dB
3402 return 80;//
3403 else if (u16NoisePower<=0x0770)//SNR>=31.6dB
3404 return 79;//
3405 else if (u16NoisePower<=0x0828)//SNR>=31.2dB
3406 return 78;//
3407 else if (u16NoisePower<=0x08F1)//SNR>=30.8dB
3408 return 77;//
3409 else if (u16NoisePower<=0x09CE)//SNR>=30.4dB
3410 return 76;//
3411 else if (u16NoisePower<=0x0AC1)//SNR>=30.0dB
3412 return 75;//
3413 else if (u16NoisePower<=0x0BCA)//SNR>=29.6dB
3414 return 74;//
3415 else if (u16NoisePower<=0x0CED)//SNR>=29.2dB
3416 return 73;//
3417 else if (u16NoisePower<=0x0E2D)//SNR>=28.8dB
3418 return 72;//
3419 else if (u16NoisePower<=0x0F8B)//SNR>=28.4dB
3420 return 71;//
3421 else if (u16NoisePower<=0x110A)//SNR>=28.0dB
3422 return 70;//
3423 else if (u16NoisePower<=0x12AF)//SNR>=27.6dB
3424 return 69;//
3425 else if (u16NoisePower<=0x147D)//SNR>=27.2dB
3426 return 68;//
3427 else if (u16NoisePower<=0x1677)//SNR>=26.8dB
3428 return 67;//
3429 else if (u16NoisePower<=0x18A2)//SNR>=26.4dB
3430 return 66;//
3431 else if (u16NoisePower<=0x1B02)//SNR>=26.0dB
3432 return 65;//
3433 else if (u16NoisePower<=0x1D9D)//SNR>=25.6dB
3434 return 64;//
3435 else if (u16NoisePower<=0x2078)//SNR>=25.2dB
3436 return 63;//
3437 else if (u16NoisePower<=0x239A)//SNR>=24.8dB
3438 return 62;//
3439 else if (u16NoisePower<=0x270A)//SNR>=24.4dB
3440 return 61;//
3441 else if (u16NoisePower<=0x2ACE)//SNR>=24.0dB
3442 return 60;//
3443 else if (u16NoisePower<=0x2EEF)//SNR>=23.6dB
3444 return 59;//
3445 else if (u16NoisePower<=0x3376)//SNR>=23.2dB
3446 return 58;//
3447 else if (u16NoisePower<=0x386D)//SNR>=22.8dB
3448 return 57;//
3449 else if (u16NoisePower<=0x3DDF)//SNR>=22.4dB
3450 return 56;//
3451 else if (u16NoisePower<=0x43D7)//SNR>=22.0dB
3452 return 55;//
3453 else if (u16NoisePower<=0x4A63)//SNR>=21.6dB
3454 return 54;//
3455 else if (u16NoisePower<=0x5190)//SNR>=21.2dB
3456 return 53;//
3457 else if (u16NoisePower<=0x596E)//SNR>=20.8dB
3458 return 52;//
3459 else if (u16NoisePower<=0x620F)//SNR>=20.4dB
3460 return 51;//
3461 else if (u16NoisePower<=0x6B85)//SNR>=20.0dB
3462 return 50;//
3463 else if (u16NoisePower<=0x75E5)//SNR>=19.6dB
3464 return 49;//
3465 else if (u16NoisePower<=0x8144)//SNR>=19.2dB
3466 return 48;//
3467 else if (u16NoisePower<=0x8DBD)//SNR>=18.8dB
3468 return 47;//
3469 else if (u16NoisePower<=0x9B6A)//SNR>=18.4dB
3470 return 46;//
3471 else if (u16NoisePower<=0xAA68)//SNR>=18.0dB
3472 return 45;//
3473 else if (u16NoisePower<=0xBAD9)//SNR>=17.6dB
3474 return 44;//
3475 else if (u16NoisePower<=0xCCE0)//SNR>=17.2dB
3476 return 43;//
3477 else if (u16NoisePower<=0xE0A4)//SNR>=16.8dB
3478 return 42;//
3479 else if (u16NoisePower<=0xF650)//SNR>=16.4dB
3480 return 41;//
3481 else// if (u16NoisePower>=0xF650)//SNR<16.4dB
3482 return 40;//
3483 }
3484 }
3485 }
3486
3487 // for J83ABC Kx series
_HAL_INTERN_ATSC_GET_QAM_SNR(float * f_snr)3488 static MS_BOOL _HAL_INTERN_ATSC_GET_QAM_SNR(float *f_snr)
3489 {
3490 MS_U8 u8Data = 0;
3491 MS_U16 noisepower = 0;
3492
3493 if (_HAL_INTERN_ATSC_QAM_Main_Lock())
3494 {
3495 // latch
3496 _MBX_WriteReg(0x2905, 0x80);
3497 // read noise power
3498 _MBX_ReadReg(0x2A45, &u8Data);
3499 noisepower = u8Data;
3500 _MBX_ReadReg(0x2A44, &u8Data);
3501 noisepower = (noisepower<<8)|u8Data;
3502 // unlatch
3503 _MBX_WriteReg(0x2905, 0x00);
3504
3505 if (noisepower == 0x0000)
3506 noisepower = 0x0001;
3507
3508 #ifdef MSOS_TYPE_LINUX
3509 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
3510 #else
3511 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
3512 #endif
3513 }
3514 else
3515 {
3516 *f_snr = 0.0f;
3517 }
3518
3519 return TRUE;
3520 }
3521
_HAL_INTERN_ATSC_ReadPKTERR(void)3522 static MS_U16 _HAL_INTERN_ATSC_ReadPKTERR(void)
3523 {
3524 MS_U16 data = 0;
3525 MS_U8 reg = 0;
3526 DMD_ATSC_DEMOD_TYPE eMode;
3527
3528 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3529
3530 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
3531 {
3532 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) data = 0;
3533 else
3534 {
3535 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_A1)
3536 _MBX_ReadReg(0x2B20, ®);
3537 data = reg;
3538 _MBX_ReadReg(0x2B21, ®);
3539 data = (data << 8)|reg;
3540 #else
3541 _MBX_ReadReg(0x1F66, ®);
3542 data = reg;
3543 _MBX_ReadReg(0x1F67, ®);
3544 data = (data << 8)|reg;
3545 #endif
3546 }
3547 }
3548 else
3549 {
3550 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) data = 0;
3551 else
3552 {
3553 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3554 _MBX_ReadReg(0x2166, ®);
3555 data = reg;
3556 _MBX_ReadReg(0x2167, ®);
3557 data = (data << 8)|reg;
3558 #elif (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_A1)
3559 _MBX_ReadReg(0x2B20, ®);
3560 data = reg;
3561 _MBX_ReadReg(0x2B21, ®);
3562 data = (data << 8)|reg;
3563 #else
3564 _MBX_ReadReg(0x1F66, ®);
3565 data = reg;
3566 _MBX_ReadReg(0x1F67, ®);
3567 data = (data << 8)|reg;
3568 #endif
3569 }
3570 }
3571
3572 return data;
3573 }
3574
_HAL_INTERN_ATSC_ReadBER(float * pBer)3575 static MS_BOOL _HAL_INTERN_ATSC_ReadBER(float *pBer)
3576 {
3577 MS_BOOL status = true;
3578 MS_U8 reg = 0, reg_frz = 0;
3579 MS_U16 BitErrPeriod;
3580 MS_U32 BitErr;
3581 DMD_ATSC_DEMOD_TYPE eMode;
3582
3583 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3584
3585 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
3586 {
3587 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) *pBer = 0;
3588 else
3589 {
3590 _MBX_ReadReg(0x1F03, ®_frz);
3591 _MBX_WriteReg(0x1F03, reg_frz|0x03);
3592
3593 _MBX_ReadReg(0x1F47, ®);
3594 BitErrPeriod = reg;
3595 _MBX_ReadReg(0x1F46, ®);
3596 BitErrPeriod = (BitErrPeriod << 8)|reg;
3597
3598 status &= _MBX_ReadReg(0x1F6d, ®);
3599 BitErr = reg;
3600 status &= _MBX_ReadReg(0x1F6c, ®);
3601 BitErr = (BitErr << 8)|reg;
3602 status &= _MBX_ReadReg(0x1F6b, ®);
3603 BitErr = (BitErr << 8)|reg;
3604 status &= _MBX_ReadReg(0x1F6a, ®);
3605 BitErr = (BitErr << 8)|reg;
3606
3607 reg_frz=reg_frz&(~0x03);
3608 _MBX_WriteReg(0x1F03, reg_frz);
3609
3610 if (BitErrPeriod == 0 ) //protect 0
3611 BitErrPeriod = 1;
3612 if (BitErr <=0 )
3613 *pBer = 0.5f / ((float)BitErrPeriod*8*187*128);
3614 else
3615 *pBer = (float)BitErr / ((float)BitErrPeriod*8*187*128);
3616 }
3617 }
3618 else
3619 {
3620 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) *pBer = 0;
3621 else
3622 {
3623 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3624 _MBX_ReadReg(0x2103, ®_frz);
3625 _MBX_WriteReg(0x2103, reg_frz|0x03);
3626
3627 _MBX_ReadReg(0x2147, ®);
3628 BitErrPeriod = reg;
3629 _MBX_ReadReg(0x2146, ®);
3630 BitErrPeriod = (BitErrPeriod << 8)|reg;
3631
3632 status &= _MBX_ReadReg(0x216d, ®);
3633 BitErr = reg;
3634 status &= _MBX_ReadReg(0x216c, ®);
3635 BitErr = (BitErr << 8)|reg;
3636 status &= _MBX_ReadReg(0x216b, ®);
3637 BitErr = (BitErr << 8)|reg;
3638 status &= _MBX_ReadReg(0x216a, ®);
3639 BitErr = (BitErr << 8)|reg;
3640
3641 reg_frz=reg_frz&(~0x03);
3642 _MBX_WriteReg(0x2103, reg_frz);
3643
3644 if (BitErrPeriod == 0) //protect 0
3645 BitErrPeriod = 1;
3646 if (BitErr <=0)
3647 *pBer = 0.5f / ((float)BitErrPeriod*8*188*128);
3648 else
3649 *pBer = (float)BitErr / ((float)BitErrPeriod*8*188*128);
3650 #else
3651 _MBX_ReadReg(0x1F03, ®_frz);
3652 _MBX_WriteReg(0x1F03, reg_frz|0x03);
3653
3654 _MBX_ReadReg(0x1F47, ®);
3655 BitErrPeriod = reg;
3656 _MBX_ReadReg(0x1F46, ®);
3657 BitErrPeriod = (BitErrPeriod << 8)|reg;
3658
3659 BitErr = reg;
3660 status &= _MBX_ReadReg(0x1F6c, ®);
3661 BitErr = (BitErr << 8)|reg;
3662 status &= _MBX_ReadReg(0x1F6b, ®);
3663 BitErr = (BitErr << 8)|reg;
3664 status &= _MBX_ReadReg(0x1F6a, ®);
3665 BitErr = (BitErr << 8)|reg;
3666
3667 reg_frz=reg_frz&(~0x03);
3668 _MBX_WriteReg(0x1F03, reg_frz);
3669
3670 if (BitErrPeriod == 0 ) //protect 0
3671 BitErrPeriod = 1;
3672 if (BitErr <=0 )
3673 *pBer = 0.5f / ((float)BitErrPeriod*7*122*128);
3674 else
3675 *pBer = (float)BitErr / ((float)BitErrPeriod*7*122*128);
3676 #endif
3677 }
3678 }
3679
3680 return status;
3681 }
3682
_HAL_INTERN_ATSC_ReadFrequencyOffset(void)3683 static MS_S16 _HAL_INTERN_ATSC_ReadFrequencyOffset(void)
3684 {
3685 DMD_ATSC_DEMOD_TYPE eMode;
3686 MS_U8 u8PTK_LOOP_FF_R3=0, u8PTK_LOOP_FF_R2=0;
3687 MS_U8 u8PTK_RATE_2=0;
3688 MS_U8 u8AD_CRL_LOOP_VALUE0=0, u8AD_CRL_LOOP_VALUE1=0;
3689 MS_U8 u8MIX_RATE_0=0, u8MIX_RATE_1=0, u8MIX_RATE_2=0;
3690 MS_S16 PTK_LOOP_FF;
3691 MS_S16 AD_CRL_LOOP_VALUE;
3692 MS_S16 MIX_RATE;
3693 MS_S16 FreqOffset = 0; //kHz
3694
3695 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3696
3697 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//
3698 {
3699 _MBX_WriteReg(0x177E, 0x01);
3700 _MBX_WriteReg(0x17E6, 0xff);
3701 _MBX_ReadReg(0x177C, &u8PTK_LOOP_FF_R2);
3702 _MBX_ReadReg(0x177D, &u8PTK_LOOP_FF_R3);
3703 _MBX_WriteReg(0x177E, 0x00);
3704 _MBX_WriteReg(0x17E6, 0xff);
3705
3706 PTK_LOOP_FF = (u8PTK_LOOP_FF_R3<<8) | u8PTK_LOOP_FF_R2;
3707 FreqOffset = (float)(-PTK_LOOP_FF*0.04768);
3708
3709 _MBX_ReadReg(0x1782, &u8PTK_RATE_2);
3710
3711 if (u8PTK_RATE_2 == 0x07)
3712 FreqOffset = FreqOffset-100;
3713 else if (u8PTK_RATE_2 == 0x08)
3714 FreqOffset = FreqOffset-500;
3715 }
3716 else //QAM MODE
3717 {
3718 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3719 _MBX_ReadReg(0x2A40, &u8AD_CRL_LOOP_VALUE0);
3720 _MBX_ReadReg(0x2A41, &u8AD_CRL_LOOP_VALUE1);
3721 _MBX_ReadReg(0x2758, &u8MIX_RATE_0);
3722 _MBX_ReadReg(0x2759, &u8MIX_RATE_1);
3723 _MBX_ReadReg(0x275A, &u8MIX_RATE_2);
3724
3725 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1 << 8) | u8AD_CRL_LOOP_VALUE0;
3726 MIX_RATE = ((u8MIX_RATE_2 << 16) | (u8MIX_RATE_1 << 8) | u8MIX_RATE_0) >> 4;
3727
3728 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
3729 {
3730 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000199); //5.360537E6/2^28*1000
3731 }
3732 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
3733 {
3734 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000188); //5.056941E6/2^21*1000
3735 }
3736
3737 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3A07)/330.13018; //(0.001/25.41*2^27/16)???
3738 #else
3739 _MBX_ReadReg(0x1A04, &u8AD_CRL_LOOP_VALUE0);
3740 _MBX_ReadReg(0x1A05, &u8AD_CRL_LOOP_VALUE1);
3741
3742 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1<<8) | u8AD_CRL_LOOP_VALUE0;
3743
3744 _MBX_ReadReg(0x1704, &u8MIX_RATE_0);
3745 _MBX_ReadReg(0x1705, &u8MIX_RATE_1);
3746 _MBX_ReadReg(0x1706, &u8MIX_RATE_2);
3747
3748 MIX_RATE = (u8MIX_RATE_2<<12)|(u8MIX_RATE_1<<4)|(u8MIX_RATE_0>>4);
3749
3750 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
3751 {
3752 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0025561); //5.360537E6/2^21*1000
3753 }
3754 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
3755 {
3756 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.00241134); //5.056941E6/2^21*1000
3757 }
3758
3759 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3D70)/2.62144; //(0.001/25*2^20/16)
3760 #endif
3761 }
3762
3763 return FreqOffset;
3764 }
3765
_HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)3766 static MS_BOOL _HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
3767 {
3768 return _MBX_ReadReg(u16Addr, pu8Data);
3769 }
3770
_HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr,MS_U8 u8Data)3771 static MS_BOOL _HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
3772 {
3773 return _MBX_WriteReg(u16Addr, u8Data);
3774 }
3775
3776 //-------------------------------------------------------------------------------------------------
3777 // Global Functions
3778 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd,void * pArgs)3779 MS_BOOL HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd, void *pArgs)
3780 {
3781 MS_BOOL bResult = TRUE;
3782
3783 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
3784 _SEL_DMD();
3785 #endif
3786
3787 switch(eCmd)
3788 {
3789 case DMD_ATSC_HAL_CMD_Exit:
3790 bResult = _HAL_INTERN_ATSC_Exit();
3791 break;
3792 case DMD_ATSC_HAL_CMD_InitClk:
3793 _HAL_INTERN_ATSC_InitClk(false);
3794 break;
3795 case DMD_ATSC_HAL_CMD_Download:
3796 bResult = _HAL_INTERN_ATSC_Download();
3797 break;
3798 case DMD_ATSC_HAL_CMD_FWVERSION:
3799 _HAL_INTERN_ATSC_FWVERSION();
3800 break;
3801 case DMD_ATSC_HAL_CMD_SoftReset:
3802 bResult = _HAL_INTERN_ATSC_SoftReset();
3803 break;
3804 case DMD_ATSC_HAL_CMD_SetVsbMode:
3805 bResult = _HAL_INTERN_ATSC_SetVsbMode();
3806 break;
3807 case DMD_ATSC_HAL_CMD_Set64QamMode:
3808 bResult = _HAL_INTERN_ATSC_Set64QamMode();
3809 break;
3810 case DMD_ATSC_HAL_CMD_Set256QamMode:
3811 bResult = _HAL_INTERN_ATSC_Set256QamMode();
3812 break;
3813 case DMD_ATSC_HAL_CMD_SetModeClean:
3814 bResult = _HAL_INTERN_ATSC_SetModeClean();
3815 break;
3816 case DMD_ATSC_HAL_CMD_Set_QAM_SR:
3817 break;
3818 case DMD_ATSC_HAL_CMD_Active:
3819 break;
3820 case DMD_ATSC_HAL_CMD_Check8VSB64_256QAM:
3821 *((DMD_ATSC_DEMOD_TYPE *)pArgs) = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3822 break;
3823 case DMD_ATSC_HAL_CMD_AGCLock:
3824 bResult = _HAL_INTERN_ATSC_Vsb_QAM_AGCLock();
3825 break;
3826 case DMD_ATSC_HAL_CMD_Vsb_PreLock:
3827 bResult = _HAL_INTERN_ATSC_Vsb_PreLock();
3828 break;
3829 case DMD_ATSC_HAL_CMD_Vsb_FSync_Lock:
3830 bResult = _HAL_INTERN_ATSC_Vsb_FSync_Lock();
3831 break;
3832 case DMD_ATSC_HAL_CMD_Vsb_CE_Lock:
3833 bResult = _HAL_INTERN_ATSC_Vsb_CE_Lock();
3834 break;
3835 case DMD_ATSC_HAL_CMD_Vsb_FEC_Lock:
3836 bResult = _HAL_INTERN_ATSC_Vsb_FEC_Lock();
3837 break;
3838 case DMD_ATSC_HAL_CMD_QAM_PreLock:
3839 bResult = _HAL_INTERN_ATSC_QAM_PreLock();
3840 break;
3841 case DMD_ATSC_HAL_CMD_QAM_Main_Lock:
3842 bResult = _HAL_INTERN_ATSC_QAM_Main_Lock();
3843 break;
3844 case DMD_ATSC_HAL_CMD_ReadIFAGC:
3845 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadIFAGC();
3846 break;
3847 case DMD_ATSC_HAL_CMD_CheckSignalCondition:
3848 _HAL_INTERN_ATSC_CheckSignalCondition((DMD_ATSC_SIGNAL_CONDITION *)pArgs);
3849 break;
3850 case DMD_ATSC_HAL_CMD_ReadSNRPercentage:
3851 *((MS_U8 *)pArgs) = _HAL_INTERN_ATSC_ReadSNRPercentage();
3852 break;
3853 case DMD_ATSC_HAL_CMD_GET_QAM_SNR:
3854 bResult = _HAL_INTERN_ATSC_GET_QAM_SNR((float *)pArgs);
3855 break;
3856 case DMD_ATSC_HAL_CMD_ReadPKTERR:
3857 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadPKTERR();
3858 break;
3859 case DMD_ATSC_HAL_CMD_GetPreViterbiBer:
3860 break;
3861 case DMD_ATSC_HAL_CMD_GetPostViterbiBer:
3862 bResult = _HAL_INTERN_ATSC_ReadBER((float *)pArgs);
3863 break;
3864 case DMD_ATSC_HAL_CMD_ReadFrequencyOffset:
3865 *((MS_S16 *)pArgs) = _HAL_INTERN_ATSC_ReadFrequencyOffset();
3866 break;
3867 case DMD_ATSC_HAL_CMD_TS_INTERFACE_CONFIG:
3868 break;
3869 case DMD_ATSC_HAL_CMD_IIC_Bypass_Mode:
3870 break;
3871 case DMD_ATSC_HAL_CMD_SSPI_TO_GPIO:
3872 break;
3873 case DMD_ATSC_HAL_CMD_GPIO_GET_LEVEL:
3874 break;
3875 case DMD_ATSC_HAL_CMD_GPIO_SET_LEVEL:
3876 break;
3877 case DMD_ATSC_HAL_CMD_GPIO_OUT_ENABLE:
3878 break;
3879 case DMD_ATSC_HAL_CMD_GET_REG:
3880 bResult = _HAL_INTERN_ATSC_GetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ATSC_REG_DATA *)pArgs)).u8Data));
3881 break;
3882 case DMD_ATSC_HAL_CMD_SET_REG:
3883 bResult = _HAL_INTERN_ATSC_SetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, (*((DMD_ATSC_REG_DATA *)pArgs)).u8Data);
3884 break;
3885 default:
3886 break;
3887 }
3888
3889 return bResult;
3890 }
3891
MDrv_DMD_ATSC_Initial_Hal_Interface(void)3892 MS_BOOL MDrv_DMD_ATSC_Initial_Hal_Interface(void)
3893 {
3894 return TRUE;
3895 }
3896