1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_DTMB.h"
106
107 #include "MsTypes.h"
108 #if DMD_DTMB_UTOPIA_EN || DMD_DTMB_UTOPIA2_EN
109 #include "drvDMD_common.h"
110 #include "halDMD_INTERN_common.h"
111 #endif
112
113 //-------------------------------------------------------------------------------------------------
114 // Driver Compiler Options
115 //-------------------------------------------------------------------------------------------------
116
117 #define DMD_DTMB_CHIP_NIKON 0x00
118 #define DMD_DTMB_CHIP_NASA 0x01
119 #define DMD_DTMB_CHIP_MADISON 0x02
120 #define DMD_DTMB_CHIP_MONACO 0x03
121 #define DMD_DTMB_CHIP_MUJI 0x04
122 #define DMD_DTMB_CHIP_MONET 0x05
123 #define DMD_DTMB_CHIP_MANHATTAN 0x06
124 #define DMD_DTMB_CHIP_MESSI 0x07
125 #define DMD_DTMB_CHIP_MASERATI 0x08
126 #define DMD_DTMB_CHIP_MACAN 0x09
127 #define DMD_DTMB_CHIP_MOONEY 0x0A
128
129 #if defined(nikon)
130 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
131 #elif defined(nasa)
132 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
133 #elif defined(madison)
134 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
135 #elif defined(monaco)
136 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
137 #elif defined(muji)
138 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
139 #elif defined(monet)
140 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
141 #elif defined(manhattan)
142 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
143 #elif defined(messi)
144 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
145 #elif defined(maserati)
146 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MASERATI
147 #elif defined(macan)
148 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MACAN
149 #elif defined(mooney)
150 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MOONEY
151 #else
152 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
153 #endif
154
155 //-------------------------------------------------------------------------------------------------
156 // Local Defines
157 //-------------------------------------------------------------------------------------------------
158 #if 0
159 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr) ) )
160 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr), val) )
161 #endif
162 #define HAL_INTERN_DTMB_DBINFO(y) //y
163
164 //#define MBRegBase 0x112600
165 //#define DMDMcuBase 0x103480
166
167 #define DTMB_REG_BASE 0x2600
168
169 #define DTMB_ACI_COEF_SIZE 112
170
171 #define DMD_DTMB_CHIP_ID_NASA 0x6E
172 #define DMD_DTMB_CHIP_ID_WALTZ 0x9C
173
174 //-------------------------------------------------------------------------------------------------
175 // Local Variables
176 //-------------------------------------------------------------------------------------------------
177
178 const MS_U8 INTERN_DTMB_table[] = {
179 #include "DMD_INTERN_DTMB.dat"
180 };
181
182 const MS_U8 INTERN_DTMB_6M_table[] = {
183 #include "DMD_INTERN_DTMB_6M.dat"
184 };
185
186 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
187 const MS_U8 INTERN_DTMB_table_Waltz[] = {
188 #include "DMD_INTERN_DTMB_Waltz.dat"
189 };
190
191 const MS_U8 INTERN_DTMB_6M_table_Waltz[] = {
192 #include "DMD_INTERN_DTMB_6M_Waltz.dat"
193 };
194 #endif
195
196 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
197 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
198 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
199 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
200 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
201
202 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
203 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
204 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
205 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
206 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
207
208 //-------------------------------------------------------------------------------------------------
209 // Global Variables
210 //-------------------------------------------------------------------------------------------------
211
212 extern MS_U8 u8DMD_DTMB_DMD_ID;
213
214 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
215
216 //-------------------------------------------------------------------------------------------------
217 // Local Functions
218 //-------------------------------------------------------------------------------------------------
219 #if 0
220 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
221 {
222 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
223 }
224
225 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
226 {
227 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
228 }
229 #endif
230 //static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
231 //{
232 // _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
233 //}
234
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)235 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
236 {
237 MS_U8 u8CheckCount;
238 MS_U8 u8CheckFlag;
239
240 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
241 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
242 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
243 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
244
245 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
246 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
247
248 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
249 {
250 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
251 if ((u8CheckFlag&0x01)==0)
252 break;
253 MsOS_DelayTask(1);
254 }
255
256 if (u8CheckFlag&0x01)
257 {
258 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
259 return FALSE;
260 }
261
262 return TRUE;
263 }
264
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)265 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
266 {
267 MS_U8 u8CheckCount;
268 MS_U8 u8CheckFlag;
269
270 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
271 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
272 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
273
274 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
275 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
276
277 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
278 {
279 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
280 if ((u8CheckFlag&0x02)==0)
281 {
282 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
283 break;
284 }
285 MsOS_DelayTask(1);
286 }
287
288 if (u8CheckFlag&0x02)
289 {
290 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
291 return FALSE;
292 }
293
294 return TRUE;
295 }
296
297 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)298 static void _HAL_INTERN_DTMB_InitClk(void)
299 {
300 MS_U8 u8Val = 0;
301
302 printf("--------------DMD_DTMB_CHIP_NIKON--------------\n");
303
304 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
305 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
306
307 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
308 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
309 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
310 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
311 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
312 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
313 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
314 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
315
316 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
317 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
318 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
319 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
320 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
321 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
322 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
323 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
324 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
325 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
326 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
327 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
328 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
329 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
330 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
331 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
332 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
333 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
334 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
335 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
336 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
337 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
338 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
339 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
340 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
341 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
342 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
343 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
344 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
345
346 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
347 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
348 }
349 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)350 static void _HAL_INTERN_DTMB_InitClk(void)
351 {
352 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
353
354 MS_U8 u8Val = 0;
355
356 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
357 {
358 printf("--------------DMD_DTMB_CHIP_WALTZ--------------\n");
359
360 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
361 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
362
363 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
364 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
365
366 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
367 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
368
369 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
370 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
371 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
372 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
373
374 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
375 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
376
377 HAL_DMD_RIU_WriteByte(0x111f49, 0xcc);
378 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
379
380 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
381 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
382 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
383 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
384 HAL_DMD_RIU_WriteByte(0x111f75, 0x00);
385 HAL_DMD_RIU_WriteByte(0x111f74, 0x00);
386 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
387 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
388
389 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
390 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
391 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
392 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
393 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
394 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
395 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
396 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
397
398 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
399 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
400 HAL_DMD_RIU_WriteByte(0x111f7a, 0x00);
401 HAL_DMD_RIU_WriteByte(0x111f7b, 0x00);
402 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
403 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
404
405 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
406 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
407
408 HAL_DMD_RIU_WriteByte(0x111f79, 0x00);
409 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
410
411 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
412 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
413
414 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
415 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
416 }
417 else
418 {
419 printf("--------------DMD_DTMB_CHIP_NASA--------------\n");
420
421 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
422 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
423
424 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
425 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
426 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
427 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
428 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
429 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
430 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
431 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
432
433 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
434 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
435 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
436 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
437 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
438 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
439 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
440 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
441 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
442 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
443 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
444 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
445 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
446 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
447 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
448 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
449 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
450 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
451 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
452 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
453 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
454 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
455 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
456 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
457 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
458 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
459 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
460 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
461 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
462
463 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
464 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
465 }
466 }
467 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)468 static void _HAL_INTERN_DTMB_InitClk(void)
469 {
470 MS_U8 u8Val = 0;
471
472 printf("--------------DMD_DTMB_CHIP_MADISON--------------\n");
473
474 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
475 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
476
477 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
478 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
479 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
480 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
481 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
482 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
483 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
484 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
485
486 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
487 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
488
489 //carl
490 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
491 HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
492 HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
493 HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
494
495 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
496 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
497 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
498 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
499 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
500 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
501 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
502 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
503
504 //carl
505 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
506 HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
507
508 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
509 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
510 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
511 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
512 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
513 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
514 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
515 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
516 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
517 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
518 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
519 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
520 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
521 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
522 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
523 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
524 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
525 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
526 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
527
528 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
529 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
530 }
531 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)532 static void _HAL_INTERN_DTMB_InitClk(void)
533 {
534 MS_U8 u8Val = 0;
535
536 printf("--------------DMD_DTMB_CHIP_MONACO--------------\n");
537
538 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
539 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
540
541 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
542 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
543
544 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
545 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
546
547 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
548 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
549 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
550 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
551
552 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
553 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
554
555 //carl
556 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
557 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
558
559 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
560 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
561 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
562 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
563 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
564 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
565 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
566 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
567 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
568 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
569
570 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
571 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
572 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
573 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
574
575 //carl
576 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
577 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
578 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
579 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
580
581 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
582 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
583
584 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
585
586 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
587 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
588 }
589 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)590 static void _HAL_INTERN_DTMB_InitClk(void)
591 {
592 MS_U8 u8Val = 0;
593
594 printf("--------------DMD_DTMB_CHIP_MUJI--------------\n");
595
596 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
597 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
598
599 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
600 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
601
602 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
603 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
604
605 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
606 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
607 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
608 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
609 HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
610 HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
611
612 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
613 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
614
615 //carl
616 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
617 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
618
619 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
620 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
621 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
622 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
623 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
624 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
625 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
626 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
627 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
628 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
629
630 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
631 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
632 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
633 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
634
635 //carl
636 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
637 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
638 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
639 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
640
641 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
642 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
643
644 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
645
646 HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
647 HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
648
649 HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
650 HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
651
652 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
653 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
654 }
655 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)656 static void _HAL_INTERN_DTMB_InitClk(void)
657 {
658 MS_U8 u8Val = 0;
659
660 printf("--------------DMD_DTMB_CHIP_MONET--------------\n");
661
662 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
663 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
664
665 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
666 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
667
668 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
669 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
670
671 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
672 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
673 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
674 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
675 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
676 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
677
678 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
679 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
680
681 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
682 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
683
684 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
685 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
686 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
687 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
688
689 HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
690 HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
691
692 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
693 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
694 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
695 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
696 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
697 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
698
699 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
700 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
701 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
702 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
703
704 //carl
705 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
706 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
707
708 HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
709 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
710
711
712 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
713 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
714
715 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
716 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
717
718 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
719 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
720
721 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
722 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
723
724 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
725 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
726
727 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
728 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
729 }
730 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)731 static void _HAL_INTERN_DTMB_InitClk(void)
732 {
733 MS_U8 u8Val = 0;
734
735 printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n");
736
737 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
738 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
739
740 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
741 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
742
743 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
744 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
745
746 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
747 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
748 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
749 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
750 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
751 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
752
753 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
754 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
755
756 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
757 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
758
759 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
760 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
761 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
762 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
763
764 // HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
765 // HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
766
767 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
768 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
769 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
770 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
771 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
772 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
773
774 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
775 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
776 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
777 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
778
779 //carl
780 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
781 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
782
783 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
784 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
785
786
787 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
788 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
789
790 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
791 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
792
793 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
794 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
795
796 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
797 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
798
799 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
800 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
801
802 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
803 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
804
805 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
806 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
807
808 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
809 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
810
811 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
812 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
813
814 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
815 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
816
817
818 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
819 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
820
821 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
822 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
823 }
824 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI)
_HAL_INTERN_DTMB_InitClk(void)825 static void _HAL_INTERN_DTMB_InitClk(void)
826 {
827 MS_U8 u8Val = 0;
828
829 printf("--------------DMD_DTMB_CHIP_MESSI--------------\n");
830
831 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
832 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
833
834 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
835 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
836
837 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
838 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
839
840 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
841 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
842 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
843 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
844 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
845 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
846
847 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
848 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
849
850 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
851 //_HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
852 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
853
854 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
855 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
856 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
857 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
858
859 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
860 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
861
862 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
863 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
864 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
865 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
866 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
867 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
868
869 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
870 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
871 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
872 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
873
874 //carl
875 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
876 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
877
878 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
879 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
880
881
882 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
883 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
884
885 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
886 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
887
888 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
889 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
890
891 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
892 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
893
894 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
895 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
896
897 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
898 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
899
900 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
901 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
902
903 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
904 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
905
906 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
907 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
908
909 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
910 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
911
912
913 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
914 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
915
916 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
917 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
918 }
919 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
_HAL_INTERN_DTMB_InitClk(void)920 static void _HAL_INTERN_DTMB_InitClk(void)
921 {
922 MS_U8 u8Val = 0;
923
924 printf("--------------DMD_DTMB_CHIP_MASERATI_MACAN--------------\n");
925
926 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
927 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
928
929 HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
930
931 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
932 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
933
934 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
935 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
936
937 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
938 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
939
940 //HAL_DMD_RIU_WriteByte(0x103315, 0x00);
941 //HAL_DMD_RIU_WriteByte(0x103314, 0x00);
942
943 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
944 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
945
946 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
947 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
948
949 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
950 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
951
952 HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
953
954 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
955 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
956
957 HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
958 HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
959
960 HAL_DMD_RIU_WriteByte(0x152923, 0x00);
961 HAL_DMD_RIU_WriteByte(0x152922, 0x14);
962
963 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
964 HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
965
966 HAL_DMD_RIU_WriteByte(0x152973, 0x00);
967 HAL_DMD_RIU_WriteByte(0x152972, 0x00);
968
969 HAL_DMD_RIU_WriteByte(0x152975, 0x00);
970 HAL_DMD_RIU_WriteByte(0x152974, 0x00);
971
972 HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
973 HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
974
975 HAL_DMD_RIU_WriteByte(0x152961, 0x00);
976 HAL_DMD_RIU_WriteByte(0x152960, 0x00);
977
978 HAL_DMD_RIU_WriteByte(0x152963, 0x00);
979 HAL_DMD_RIU_WriteByte(0x152962, 0x00);
980
981 HAL_DMD_RIU_WriteByte(0x152965, 0x00);
982 HAL_DMD_RIU_WriteByte(0x152964, 0x00);
983
984 HAL_DMD_RIU_WriteByte(0x152969, 0x00);
985 HAL_DMD_RIU_WriteByte(0x152968, 0x00);
986
987 HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
988 HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
989
990 HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
991
992 HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
993 HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
994
995 HAL_DMD_RIU_WriteByte(0x152971, 0x00);
996 HAL_DMD_RIU_WriteByte(0x152970, 0x04);
997
998 HAL_DMD_RIU_WriteByte(0x152979, 0x00);
999 HAL_DMD_RIU_WriteByte(0x152978, 0x00);
1000
1001 HAL_DMD_RIU_WriteByte(0x152951, 0x04);
1002 HAL_DMD_RIU_WriteByte(0x152950, 0x00);
1003
1004 HAL_DMD_RIU_WriteByte(0x152981, 0x88);
1005 HAL_DMD_RIU_WriteByte(0x152980, 0x88);
1006
1007 HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
1008 HAL_DMD_RIU_WriteByte(0x152982, 0x88);
1009
1010 HAL_DMD_RIU_WriteByte(0x152985, 0x88);
1011 HAL_DMD_RIU_WriteByte(0x152984, 0x88);
1012
1013 HAL_DMD_RIU_WriteByte(0x152987, 0x08);
1014 HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
1015
1016 HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
1017 HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
1018
1019 HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
1020 HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
1021
1022 HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
1023 HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
1024
1025 HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
1026 HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
1027
1028 HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
1029 HAL_DMD_RIU_WriteByte(0x152990, 0x88);
1030
1031 HAL_DMD_RIU_WriteByte(0x152993, 0x11);
1032 HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1033
1034 HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1035 HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1036
1037 HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1038 HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1039
1040 HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1041 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1042
1043 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1044 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1045
1046 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1047 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1048
1049 HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1050
1051 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1052 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1053 }
1054 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MOONEY)
_HAL_INTERN_DTMB_InitClk(void)1055 static void _HAL_INTERN_DTMB_InitClk(void)
1056 {
1057 MS_U8 u8Val = 0;
1058
1059 printf("--------------DMD_DTMB_CHIP_MOONEY--------------\n");
1060
1061 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1062 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1063
1064 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1065 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1066
1067 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
1068 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1069
1070 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1071 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1072
1073 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1074 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1075
1076 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1077 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1078
1079 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1080 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1081
1082 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1083 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1084
1085 HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
1086 HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
1087
1088 HAL_DMD_RIU_WriteByte(0x152923, 0x00);
1089 HAL_DMD_RIU_WriteByte(0x152922, 0x14);
1090
1091 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1092 HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
1093
1094 HAL_DMD_RIU_WriteByte(0x152973, 0x00);
1095 HAL_DMD_RIU_WriteByte(0x152972, 0x00);
1096
1097 HAL_DMD_RIU_WriteByte(0x152975, 0x00);
1098 HAL_DMD_RIU_WriteByte(0x152974, 0x00);
1099
1100 HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
1101 HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
1102
1103 HAL_DMD_RIU_WriteByte(0x152961, 0x00);
1104 HAL_DMD_RIU_WriteByte(0x152960, 0x00);
1105
1106 HAL_DMD_RIU_WriteByte(0x152963, 0x00);
1107 HAL_DMD_RIU_WriteByte(0x152962, 0x00);
1108
1109 HAL_DMD_RIU_WriteByte(0x152965, 0x00);
1110 HAL_DMD_RIU_WriteByte(0x152964, 0x00);
1111
1112 HAL_DMD_RIU_WriteByte(0x152969, 0x00);
1113 HAL_DMD_RIU_WriteByte(0x152968, 0x00);
1114
1115 HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
1116 HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
1117
1118 HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
1119 HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
1120
1121 HAL_DMD_RIU_WriteByte(0x152971, 0x00);
1122 HAL_DMD_RIU_WriteByte(0x152970, 0x04);
1123
1124 HAL_DMD_RIU_WriteByte(0x152979, 0x00);
1125 HAL_DMD_RIU_WriteByte(0x152978, 0x00);
1126
1127 HAL_DMD_RIU_WriteByte(0x152951, 0x04);
1128 HAL_DMD_RIU_WriteByte(0x152950, 0x00);
1129
1130 HAL_DMD_RIU_WriteByte(0x152981, 0x88);
1131 HAL_DMD_RIU_WriteByte(0x152980, 0x88);
1132
1133 HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
1134 HAL_DMD_RIU_WriteByte(0x152982, 0x88);
1135
1136 HAL_DMD_RIU_WriteByte(0x152985, 0x88);
1137 HAL_DMD_RIU_WriteByte(0x152984, 0x88);
1138
1139 HAL_DMD_RIU_WriteByte(0x152987, 0x08);
1140 HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
1141
1142 HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
1143 HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
1144
1145 HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
1146 HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
1147
1148 HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
1149 HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
1150
1151 HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
1152 HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
1153
1154 HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
1155 HAL_DMD_RIU_WriteByte(0x152990, 0x88);
1156
1157 HAL_DMD_RIU_WriteByte(0x152993, 0x11);
1158 HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1159
1160 HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1161 HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1162
1163 HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1164 HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1165
1166 HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1167 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1168
1169
1170 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1171 HAL_DMD_RIU_WriteByte(0x111fe2, 0x11);
1172
1173 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1174
1175 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1176 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1177
1178 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1179 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1180
1181 HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1182
1183 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1184 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1185 }
1186 #else
_HAL_INTERN_DTMB_InitClk(void)1187 static void _HAL_INTERN_DTMB_InitClk(void)
1188 {
1189 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
1190 }
1191 #endif
1192
_HAL_INTERN_DTMB_Ready(void)1193 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
1194 {
1195 MS_U8 udata = 0x00;
1196
1197 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1198
1199 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1200 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1201
1202 MsOS_DelayTask(1);
1203
1204 udata = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1205
1206 if (udata) return FALSE;
1207
1208 return TRUE;
1209 }
1210
_HAL_INTERN_DTMB_Download(void)1211 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
1212 {
1213 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1214 MS_U8 udata = 0x00;
1215 MS_U16 i = 0;
1216 MS_U16 fail_cnt = 0;
1217 MS_U8 u8TmpData;
1218 MS_U16 u16AddressOffset;
1219 const MS_U8 *DTMB_table;
1220 MS_U16 u16Lib_size;
1221
1222 if (pRes->sDMD_DTMB_PriData.bDownloaded)
1223 {
1224 if (_HAL_INTERN_DTMB_Ready())
1225 {
1226 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1227 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1228 MsOS_DelayTask(20);
1229 return TRUE;
1230 }
1231 }
1232
1233 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1234 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1235 {
1236 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1237 {
1238 DTMB_table = &INTERN_DTMB_6M_table_Waltz[0];
1239 u16Lib_size = sizeof(INTERN_DTMB_6M_table_Waltz);
1240 }
1241 else
1242 {
1243 DTMB_table = &INTERN_DTMB_table_Waltz[0];
1244 u16Lib_size = sizeof(INTERN_DTMB_table_Waltz);
1245 }
1246 }
1247 else
1248 {
1249 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1250 {
1251 DTMB_table = &INTERN_DTMB_6M_table[0];
1252 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1253 }
1254 else
1255 {
1256 DTMB_table = &INTERN_DTMB_table[0];
1257 u16Lib_size = sizeof(INTERN_DTMB_table);
1258 }
1259 }
1260 #else
1261 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1262 {
1263 DTMB_table = &INTERN_DTMB_6M_table[0];
1264 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1265 }
1266 else
1267 {
1268 DTMB_table = &INTERN_DTMB_table[0];
1269 u16Lib_size = sizeof(INTERN_DTMB_table);
1270 }
1271 #endif
1272
1273 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1274 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1275
1276 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1277
1278 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1279 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1280 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1281 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1282
1283 //// Load code thru VDMCU_IF ////
1284 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
1285
1286 for (i = 0; i < u16Lib_size; i++)
1287 {
1288 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
1289 }
1290
1291 //// Content verification ////
1292 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
1293
1294 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1295 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1296
1297 for (i = 0; i < u16Lib_size; i++)
1298 {
1299 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1300
1301 if (udata != DTMB_table[i])
1302 {
1303 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
1304 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
1305 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
1306
1307 if (fail_cnt++ > 10)
1308 {
1309 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
1310 return FALSE;
1311 }
1312 }
1313 }
1314
1315 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
1316
1317 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1318 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1319
1320 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
1321 HAL_INTERN_DTMB_DBINFO(printf("u16IF_KHZ=%d\n",pRes->sDMD_DTMB_InitData.u16IF_KHZ));
1322 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1323 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
1324 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1325 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
1326 HAL_INTERN_DTMB_DBINFO(printf("bIQSwap=%d\n",pRes->sDMD_DTMB_InitData.bIQSwap));
1327 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1328 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
1329 HAL_INTERN_DTMB_DBINFO(printf("u16AGC_REFERENCE=%X\n",pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE));
1330 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1331 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
1332 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1333 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
1334 HAL_INTERN_DTMB_DBINFO(printf("u32TdiStartAddr=%X\n",pRes->sDMD_DTMB_InitData.u32TdiStartAddr));
1335 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1336 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
1337 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1338 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
1339 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1340 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
1341 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1342 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
1343 HAL_INTERN_DTMB_DBINFO(printf("eLastType=%d\n",pRes->sDMD_DTMB_PriData.eLastType));
1344 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1345
1346 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1347 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1348
1349 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1350
1351 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1352 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1353
1354 pRes->sDMD_DTMB_PriData.bDownloaded = true;
1355
1356 MsOS_DelayTask(20);
1357
1358 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
1359
1360 return TRUE;
1361 }
1362
_HAL_INTERN_DTMB_FWVERSION(void)1363 static void _HAL_INTERN_DTMB_FWVERSION(void)
1364 {
1365 MS_U8 data1,data2,data3;
1366
1367 _MBX_ReadReg(0x20C4, &data1);
1368 _MBX_ReadReg(0x20C5, &data2);
1369 _MBX_ReadReg(0x20C6, &data3);
1370
1371 HAL_INTERN_DTMB_DBINFO(printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
1372 }
1373
_HAL_INTERN_DTMB_Exit(void)1374 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
1375 {
1376 MS_U8 u8CheckCount = 0;
1377
1378 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1379
1380 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1381 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1382
1383 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1384 {
1385 MsOS_DelayTaskUs(10);
1386
1387 if (u8CheckCount++ == 0xFF)
1388 {
1389 printf(">> DTMB Exit Fail!\n");
1390 return FALSE;
1391 }
1392 }
1393
1394 printf(">> DTMB Exit Ok!\n");
1395
1396 return TRUE;
1397 }
1398
_HAL_INTERN_DTMB_SoftReset(void)1399 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
1400 {
1401 MS_U8 u8Data = 0;
1402
1403 //Reset FSM
1404 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1405
1406 while (u8Data!=0x02)
1407 {
1408 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1409 }
1410
1411 return TRUE;
1412 }
1413
_HAL_INTERN_DTMB_SetACICoef(void)1414 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1415 {
1416 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1417
1418 MS_U8 *ACI_table;
1419 MS_U8 i;
1420 MS_U16 u16AddressOffset;
1421
1422 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1423 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1424 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1425 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1426 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1427 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1428 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1429 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1430 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1431
1432 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1433 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1434
1435 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1436
1437 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1438 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1439 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1440 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1441
1442 //SET SR value
1443 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1444 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1445 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1446 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1447
1448 //set ACI coefficient
1449 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1450 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1451 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1452 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1453 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1454 {
1455 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1456 }
1457
1458 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1459 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1460
1461 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1462
1463 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1464 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1465
1466 MsOS_DelayTask(20);
1467
1468 return TRUE;
1469 }
1470
_HAL_INTERN_DTMB_SetDtmbMode(void)1471 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1472 {
1473 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1474 return _MBX_WriteReg(0x20C0, 0x04);
1475 }
1476
_HAL_INTERN_DTMB_SetModeClean(void)1477 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1478 {
1479 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1480 return _MBX_WriteReg(0x20C0, 0x00);
1481 }
1482
_HAL_INTERN_DTMB_Set_QAM_SR(void)1483 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1484 {
1485 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1486 return _MBX_WriteReg(0x20C0, 0x04);
1487 }
1488
_HAL_INTERN_DTMB_AGCLock(void)1489 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1490 {
1491 MS_U8 data = 0;
1492
1493 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MOONEY)
1494 _MBX_ReadReg(0x2829, &data);//AGC_LOCK
1495 #else
1496 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1497 #endif
1498 if (data&0x01)
1499 {
1500 return TRUE;
1501 }
1502 else
1503 {
1504 return FALSE;
1505 }
1506 }
1507
_HAL_INTERN_DTMB_PNP_Lock(void)1508 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1509 {
1510 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1511 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1512 #endif
1513
1514 MS_U8 data = 0;
1515 MS_U8 data1 = 0;
1516
1517 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1518 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1519 {
1520 _MBX_ReadReg(0x3BBA, &data);
1521 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1522 }
1523 else
1524 {
1525 _MBX_ReadReg(0x22BA, &data);
1526 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1527 }
1528 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1529 _MBX_ReadReg(0x37BA, &data);
1530 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1531 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1532 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1533 _MBX_ReadReg(0x11BA, &data);
1534 _MBX_ReadReg(0x1249, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1535 #else
1536 _MBX_ReadReg(0x3BBA, &data);
1537 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1538 #endif
1539 #else
1540 _MBX_ReadReg(0x22BA, &data);
1541 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1542 #endif
1543
1544 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1545 {
1546 return TRUE;
1547 }
1548 else
1549 {
1550 return FALSE;
1551 }
1552 }
1553
_HAL_INTERN_DTMB_FEC_Lock(void)1554 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1555 {
1556 MS_U8 u8state=0;
1557
1558
1559 _MBX_ReadReg(0x20C1, &u8state);
1560
1561 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1562 {
1563 return TRUE;
1564 }
1565 else
1566 {
1567 return FALSE;
1568 }
1569 }
1570
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1571 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1572 {
1573 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1574
1575 MS_U8 CM, QAM, IL, CR, SiNR;
1576 MS_U8 data_L = 0;
1577 MS_U8 data_H = 0;
1578
1579 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1580 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1581 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1582 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1583 {
1584 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1585 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1586 {
1587 _MBX_ReadReg(0x3B90, &data_L);
1588 _MBX_ReadReg(0x3B91, &data_H);
1589 }
1590 else
1591 {
1592 _MBX_ReadReg(0x2290, &data_L);
1593 _MBX_ReadReg(0x2291, &data_H);
1594 }
1595 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1596 _MBX_ReadReg(0x3790, &data_L);
1597 _MBX_ReadReg(0x3791, &data_H);
1598 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1599 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1600 _MBX_ReadReg(0x1190, &data_L);
1601 _MBX_ReadReg(0x1191, &data_H);
1602 #else
1603 _MBX_ReadReg(0x3B90, &data_L);
1604 _MBX_ReadReg(0x3B91, &data_H);
1605 #endif
1606 #else
1607 _MBX_ReadReg(0x2290, &data_L);
1608 _MBX_ReadReg(0x2291, &data_H);
1609 #endif
1610
1611 if (data_L & 0x1)
1612 {
1613 CR = (data_L >> 6) & 0x03;
1614 IL = (data_L >> 3) & 0x01;
1615 QAM = (data_L >> 4) & 0x03;
1616 SiNR = (data_L >> 2) & 0x01;
1617 CM = (data_L >> 1) & 0x01;
1618 }
1619 else
1620 {
1621 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1622 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1623 {
1624 _MBX_ReadReg(0x3B9E, &data_L);
1625 _MBX_ReadReg(0x3B9F, &data_H);
1626 }
1627 else
1628 {
1629 _MBX_ReadReg(0x229E, &data_L);
1630 _MBX_ReadReg(0x229F, &data_H);
1631 }
1632 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1633 _MBX_ReadReg(0x379E, &data_L);
1634 _MBX_ReadReg(0x379F, &data_H);
1635 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1636 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1637 _MBX_ReadReg(0x119E, &data_L);
1638 _MBX_ReadReg(0x119F, &data_H);
1639 #else
1640 _MBX_ReadReg(0x3B9E, &data_L);
1641 _MBX_ReadReg(0x3B9F, &data_H);
1642 #endif
1643 #else
1644 _MBX_ReadReg(0x229E, &data_L);
1645 _MBX_ReadReg(0x229F, &data_H);
1646 #endif
1647
1648 CR = (data_H >> 4) & 0x03;
1649 IL = (data_H >> 6) & 0x01;
1650 QAM = (data_H >> 2) & 0x03;
1651 SiNR = (data_H >> 1) & 0x01;
1652 CM = (data_H) & 0x01;
1653 }
1654
1655 #if 1//def MSOS_TYPE_LINUX_KERNEL
1656 if (CR == 0)
1657 psDtmbGetModulation->fSiCodeRate = 4;
1658 else if (CR == 1)
1659 psDtmbGetModulation->fSiCodeRate = 6;
1660 else if (CR == 2)
1661 psDtmbGetModulation->fSiCodeRate = 8;
1662 #else
1663 if (CR == 0)
1664 psDtmbGetModulation->fSiCodeRate = 0.4;
1665 else if (CR == 1)
1666 psDtmbGetModulation->fSiCodeRate = 0.6;
1667 else if (CR == 2)
1668 psDtmbGetModulation->fSiCodeRate = 0.8;
1669 #endif
1670
1671 if (IL == 0)
1672 psDtmbGetModulation->u8SiInterLeaver = 240;
1673 else
1674 psDtmbGetModulation->u8SiInterLeaver = 720;
1675
1676 if (QAM == 0)
1677 psDtmbGetModulation->u8SiQamMode = 4;
1678 else if (QAM == 1)
1679 psDtmbGetModulation->u8SiQamMode = 16;
1680 else if (QAM == 2)
1681 psDtmbGetModulation->u8SiQamMode = 32;
1682 else if (QAM == 3)
1683 psDtmbGetModulation->u8SiQamMode = 64;
1684
1685 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1686 psDtmbGetModulation->u8SiNR = SiNR;
1687 }
1688 else
1689 {
1690 }
1691
1692 return TRUE;
1693 }
1694
_HAL_INTERN_DTMB_ReadIFAGC(void)1695 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1696 {
1697 MS_U8 data = 0;
1698 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MOONEY)
1699 _MBX_ReadReg(0x280F, &data);
1700 #else
1701 _MBX_ReadReg(0x28FD, &data);
1702 #endif
1703
1704 return data;
1705 }
1706
1707 #ifdef UTPA2
_HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 * pFftfirstCfo,MS_S8 * pFftSecondCfo,MS_S16 * pSr)1708 static MS_BOOL _HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 *pFftfirstCfo, MS_S8 *pFftSecondCfo, MS_S16 *pSr)
1709 #else
1710 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1711 #endif
1712 {
1713 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1714
1715 MS_U8 u8Data = 0;
1716 MS_S16 fftfirstCfo = 0;
1717 MS_S8 fftSecondCfo = 0;
1718 MS_S16 sr = 0;
1719
1720 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1721 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1722 {
1723 _MBX_ReadReg(0x3C4D, &u8Data);
1724 fftfirstCfo = u8Data;
1725 _MBX_ReadReg(0x3C4C, &u8Data);
1726 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1727
1728 _MBX_ReadReg(0x3C50, &u8Data);
1729 fftSecondCfo = u8Data;
1730 }
1731 else
1732 {
1733 _MBX_ReadReg(0x234D, &u8Data);
1734 fftfirstCfo = u8Data;
1735 _MBX_ReadReg(0x234C, &u8Data);
1736 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1737
1738 _MBX_ReadReg(0x2350, &u8Data);
1739 fftSecondCfo = u8Data;
1740 }
1741 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1742 _MBX_ReadReg(0x384D, &u8Data);
1743 fftfirstCfo = u8Data;
1744 _MBX_ReadReg(0x384C, &u8Data);
1745 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1746
1747 _MBX_ReadReg(0x3850, &u8Data);
1748 fftSecondCfo = u8Data;
1749 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1750 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1751 _MBX_ReadReg(0x124D, &u8Data);
1752 fftfirstCfo = u8Data;
1753 _MBX_ReadReg(0x124C, &u8Data);
1754 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1755 _MBX_ReadReg(0x1250, &u8Data);
1756 fftSecondCfo = u8Data;
1757 #else
1758 _MBX_ReadReg(0x3C4D, &u8Data);
1759 fftfirstCfo = u8Data;
1760 _MBX_ReadReg(0x3C4C, &u8Data);
1761 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1762
1763 _MBX_ReadReg(0x3C50, &u8Data);
1764 fftSecondCfo = u8Data;
1765 #endif
1766 #else
1767 _MBX_ReadReg(0x234D, &u8Data);
1768 fftfirstCfo = u8Data;
1769 _MBX_ReadReg(0x234C, &u8Data);
1770 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1771
1772 _MBX_ReadReg(0x2350, &u8Data);
1773 fftSecondCfo = u8Data;
1774 #endif
1775
1776 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1777 sr = 5670;
1778 else sr = 7560;
1779
1780 #ifdef UTPA2
1781 *pFftfirstCfo = fftfirstCfo;
1782 *pFftSecondCfo = fftSecondCfo;
1783 *pSr = sr;
1784
1785 return TRUE;
1786 #else
1787 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1788 #endif
1789 }
1790
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1791 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1792 {
1793 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1794
1795 MS_U8 data = 0;
1796 MS_U8 level = 0;
1797 MS_U32 snr = 0;
1798
1799 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1800 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1801 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1802 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1803 {
1804 if (!_HAL_INTERN_DTMB_FEC_Lock())
1805 level = 0;
1806 else
1807 {
1808 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1809 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1810 {
1811 _MBX_ReadReg(0x3BDA, &data);
1812 snr = data&0x3F;
1813 _MBX_ReadReg(0x3BD9, &data);
1814 snr = (snr<<8)|data;
1815 _MBX_ReadReg(0x3BD8, &data);
1816 snr = (snr<<8)|data;
1817 }
1818 else
1819 {
1820 _MBX_ReadReg(0x22DA, &data);
1821 snr = data&0x3F;
1822 _MBX_ReadReg(0x22D9, &data);
1823 snr = (snr<<8)|data;
1824 _MBX_ReadReg(0x22D8, &data);
1825 snr = (snr<<8)|data;
1826 }
1827 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1828 _MBX_ReadReg(0x37DA, &data);
1829 snr = data&0x3F;
1830 _MBX_ReadReg(0x37D9, &data);
1831 snr = (snr<<8)|data;
1832 _MBX_ReadReg(0x37D8, &data);
1833 snr = (snr<<8)|data;
1834 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1835 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1836 _MBX_ReadReg(0x11DA, &data);
1837 snr = data&0x3F;
1838 _MBX_ReadReg(0x11D9, &data);
1839 snr = (snr<<8)|data;
1840 _MBX_ReadReg(0x11D8, &data);
1841 snr = (snr<<8)|data;
1842 #else
1843 _MBX_ReadReg(0x3BDA, &data);
1844 snr = data&0x3F;
1845 _MBX_ReadReg(0x3BD9, &data);
1846 snr = (snr<<8)|data;
1847 _MBX_ReadReg(0x3BD8, &data);
1848 snr = (snr<<8)|data;
1849 #endif
1850 #else
1851 _MBX_ReadReg(0x22DA, &data);
1852 snr = data&0x3F;
1853 _MBX_ReadReg(0x22D9, &data);
1854 snr = (snr<<8)|data;
1855 _MBX_ReadReg(0x22D8, &data);
1856 snr = (snr<<8)|data;
1857 #endif
1858
1859 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1860 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1861 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1862 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1863 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1864 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1865 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1866 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1867 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1868 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1869 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1870 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1871 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1872 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1873 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1874 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1875 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1876 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1877 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1878 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1879 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1880 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1881 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1882 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1883 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1884 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1885 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1886 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1887 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1888 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1889 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1890 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1891 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1892 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1893 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1894 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1895 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1896 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1897 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1898 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1899 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1900 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1901 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1902 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1903 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1904 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1905 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1906 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1907 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1908 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1909 }
1910 }
1911 else
1912 {
1913 level = 0;
1914 }
1915
1916 return level*2;
1917 }
1918
1919 #ifdef UTPA2
_HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 * pBitErr,MS_U16 * pError_window)1920 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 *pBitErr, MS_U16 *pError_window)
1921 #else
1922 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1923 #endif
1924 {
1925 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1926 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1927 #endif
1928
1929 MS_U8 u8Data=0;
1930 MS_U32 BitErr;
1931 MS_U16 error_window;
1932
1933 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1934 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1935 {
1936 _MBX_ReadReg(0x3F3B, &u8Data);
1937 BitErr = u8Data;
1938 _MBX_ReadReg(0x3F3A, &u8Data);
1939 BitErr = (BitErr << 8)|u8Data;
1940 _MBX_ReadReg(0x3F39, &u8Data);
1941 BitErr = (BitErr << 8)|u8Data;
1942 _MBX_ReadReg(0x3F38, &u8Data);
1943 BitErr = (BitErr << 8)|u8Data;
1944 }
1945 else
1946 {
1947 _MBX_ReadReg(0x263B, &u8Data);
1948 BitErr = u8Data;
1949 _MBX_ReadReg(0x263A, &u8Data);
1950 BitErr = (BitErr << 8)|u8Data;
1951 _MBX_ReadReg(0x2639, &u8Data);
1952 BitErr = (BitErr << 8)|u8Data;
1953 _MBX_ReadReg(0x2638, &u8Data);
1954 BitErr = (BitErr << 8)|u8Data;
1955 }
1956 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1957 _MBX_ReadReg(0x2D3B, &u8Data);
1958 BitErr = u8Data;
1959 _MBX_ReadReg(0x2D3A, &u8Data);
1960 BitErr = (BitErr << 8)|u8Data;
1961 _MBX_ReadReg(0x2D39, &u8Data);
1962 BitErr = (BitErr << 8)|u8Data;
1963 _MBX_ReadReg(0x2D38, &u8Data);
1964 BitErr = (BitErr << 8)|u8Data;
1965 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1966 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1967 _MBX_ReadReg(0x163B, &u8Data);
1968 BitErr = u8Data;
1969 _MBX_ReadReg(0x163A, &u8Data);
1970 BitErr = (BitErr << 8)|u8Data;
1971 _MBX_ReadReg(0x1639, &u8Data);
1972 BitErr = (BitErr << 8)|u8Data;
1973 _MBX_ReadReg(0x1638, &u8Data);
1974 BitErr = (BitErr << 8)|u8Data;
1975 #else
1976 _MBX_ReadReg(0x3F3B, &u8Data);
1977 BitErr = u8Data;
1978 _MBX_ReadReg(0x3F3A, &u8Data);
1979 BitErr = (BitErr << 8)|u8Data;
1980 _MBX_ReadReg(0x3F39, &u8Data);
1981 BitErr = (BitErr << 8)|u8Data;
1982 _MBX_ReadReg(0x3F38, &u8Data);
1983 BitErr = (BitErr << 8)|u8Data;
1984 #endif
1985 #else
1986 _MBX_ReadReg(0x263B, &u8Data);
1987 BitErr = u8Data;
1988 _MBX_ReadReg(0x263A, &u8Data);
1989 BitErr = (BitErr << 8)|u8Data;
1990 _MBX_ReadReg(0x2639, &u8Data);
1991 BitErr = (BitErr << 8)|u8Data;
1992 _MBX_ReadReg(0x2638, &u8Data);
1993 BitErr = (BitErr << 8)|u8Data;
1994 #endif
1995
1996 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1997 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1998 {
1999 _MBX_ReadReg(0x3F2F, &u8Data);
2000 error_window = u8Data;
2001 _MBX_ReadReg(0x3F2E, &u8Data);
2002 error_window = (error_window << 8)|u8Data;
2003 }
2004 else
2005 {
2006 _MBX_ReadReg(0x262F, &u8Data);
2007 error_window = u8Data;
2008 _MBX_ReadReg(0x262E, &u8Data);
2009 error_window = (error_window << 8)|u8Data;
2010 }
2011 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
2012 _MBX_ReadReg(0x2D2F, &u8Data);
2013 error_window = u8Data;
2014 _MBX_ReadReg(0x2D2E, &u8Data);
2015 error_window = (error_window << 8)|u8Data;
2016 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
2017 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
2018 _MBX_ReadReg(0x162F, &u8Data);
2019 error_window = u8Data;
2020 _MBX_ReadReg(0x162E, &u8Data);
2021 error_window = (error_window << 8)|u8Data;
2022 #else
2023 _MBX_ReadReg(0x3F2F, &u8Data);
2024 error_window = u8Data;
2025 _MBX_ReadReg(0x3F2E, &u8Data);
2026 error_window = (error_window << 8)|u8Data;
2027 #endif
2028 #else
2029 _MBX_ReadReg(0x262F, &u8Data);
2030 error_window = u8Data;
2031 _MBX_ReadReg(0x262E, &u8Data);
2032 error_window = (error_window << 8)|u8Data;
2033 #endif
2034
2035 #ifdef UTPA2
2036 *pBitErr = BitErr;
2037 *pError_window = error_window;
2038 #else
2039 *pber=(float)BitErr/7488.0/(float)error_window;
2040 #endif
2041
2042 return TRUE;
2043 }
2044
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2045 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2046 {
2047 return _MBX_ReadReg(u16Addr, pu8Data);
2048 }
2049
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2050 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2051 {
2052 return _MBX_WriteReg(u16Addr, u8Data);
2053 }
2054
2055 //-------------------------------------------------------------------------------------------------
2056 // Global Functions
2057 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)2058 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
2059 {
2060 MS_BOOL bResult = TRUE;
2061
2062 switch(eCmd)
2063 {
2064 case DMD_DTMB_HAL_CMD_Exit:
2065 bResult = _HAL_INTERN_DTMB_Exit();
2066 break;
2067 case DMD_DTMB_HAL_CMD_InitClk:
2068 _HAL_INTERN_DTMB_InitClk();
2069 break;
2070 case DMD_DTMB_HAL_CMD_Download:
2071 bResult = _HAL_INTERN_DTMB_Download();
2072 break;
2073 case DMD_DTMB_HAL_CMD_FWVERSION:
2074 _HAL_INTERN_DTMB_FWVERSION();
2075 break;
2076 case DMD_DTMB_HAL_CMD_SoftReset:
2077 bResult = _HAL_INTERN_DTMB_SoftReset();
2078 break;
2079 case DMD_DTMB_HAL_CMD_SetACICoef:
2080 bResult = _HAL_INTERN_DTMB_SetACICoef();
2081 break;
2082 case DMD_DTMB_HAL_CMD_SetDTMBMode:
2083 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
2084 break;
2085 case DMD_DTMB_HAL_CMD_SetModeClean:
2086 bResult = _HAL_INTERN_DTMB_SetModeClean();
2087 break;
2088 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
2089 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
2090 break;
2091 case DMD_DTMB_HAL_CMD_Active:
2092 break;
2093 case DMD_DTMB_HAL_CMD_AGCLock:
2094 bResult = _HAL_INTERN_DTMB_AGCLock();
2095 break;
2096 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
2097 bResult = _HAL_INTERN_DTMB_PNP_Lock();
2098 break;
2099 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
2100 bResult = _HAL_INTERN_DTMB_FEC_Lock();
2101 break;
2102 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
2103 break;
2104 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
2105 break;
2106 case DMD_DTMB_HAL_CMD_GetModulation:
2107 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
2108 case DMD_DTMB_HAL_CMD_ReadIFAGC:
2109 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
2110 break;
2111 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
2112 #ifdef UTPA2
2113 bResult = _HAL_INTERN_DTMB_ReadFrequencyOffset(&((*((DMD_DTMB_CFO_DATA *)pArgs)).fftfirstCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).fftSecondCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).sr));
2114 #else
2115 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
2116 #endif
2117 break;
2118 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
2119 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
2120 break;
2121 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
2122 #ifdef UTPA2
2123 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer(&((*((DMD_DTMB_BER_DATA *)pArgs)).BitErr), &((*((DMD_DTMB_BER_DATA *)pArgs)).Error_window));
2124 #else
2125 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
2126 #endif
2127 break;
2128 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
2129 break;
2130 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
2131 break;
2132 // case DMD_DTMB_HAL_CMD_GetSNR:
2133 // break;
2134 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
2135 break;
2136 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
2137 break;
2138 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
2139 break;
2140 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
2141 break;
2142 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
2143 break;
2144 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
2145 break;
2146 // case DMD_DTMB_HAL_CMD_DoIQSwap:
2147 // break;
2148 case DMD_DTMB_HAL_CMD_GET_REG:
2149 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
2150 break;
2151 case DMD_DTMB_HAL_CMD_SET_REG:
2152 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
2153 break;
2154 default:
2155 break;
2156 }
2157
2158 return bResult;
2159 }
2160
MDrv_DMD_DTMB_Initial_Hal_Interface(void)2161 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
2162 {
2163 return TRUE;
2164 }
2165
2166