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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "ULog.h"
108 #include "MsCommon.h"
109 #include "MsIRQ.h"
110 #include "MsOS.h"
111 //#include "apiPWS.h"
112
113 #include "MsTypes.h"
114 #include "drvBDMA.h"
115 //#include "drvIIC.h"
116 //#include "msAPI_Tuner.h"
117 //#include "msAPI_MIU.h"
118 //#include "BinInfo.h"
119 //#include "halVif.h"
120 #include "drvDMD_INTERN_DVBC.h"
121 #include "halDMD_INTERN_DVBC.h"
122 #include "halDMD_INTERN_common.h"
123 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
124 #include "InfoBlock.h"
125 #endif
126 #include "drvMMIO.h"
127 //#include "TDAG4D01A_SSI_DVBT.c"
128 #include "drvDMD_VD_MBX.h"
129 #define TEST_EMBEDED_DEMOD 0
130
131 #define PARA_TBL_LENGTH 110
132
133 //U8 load_data_variable=1;
134 //-----------------------------------------------------------------------
135 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
136
137 #define TDE_REG_BASE 0x2400UL
138 #define INNC_REG_BASE 0x2600UL // P2 = 1, 0x11b00 -> 0x1b00
139 #define EQE_REG_BASE 0x2700UL // P2 = 1, 0x11a00 -> 0x1a00
140 #define EQE2_REG_BASE 0x9c00UL // P2 = 1, 0x11c00 -> 0x1c00
141 #define MBX_REG_BASE 0x2F00UL
142
143 #define MB_DEMOD_A_INTERRUPT_CASE MBRegBase+0x14
144 #define MB_DEMOD_A_TS_DIV MBRegBase+0x15
145 #define MB_DEMOD_A_UNLOCK_ONCE MBRegBase+0x16
146 #define MB_DEMOD_A_FW_CNT MBRegBase+0x17
147 #define MB_DEMOD_A_DRV_CNT MBRegBase+0x18
148
149 #define MB_DEMOD_B_INTERRUPT_CASE MBRegBase+0x1A
150 #define MB_DEMOD_B_TS_DIV MBRegBase+0x1B
151 #define MB_DEMOD_B_UNLOCK_ONCE MBRegBase+0x1D
152 #define MB_DEMOD_B_FW_CNT MBRegBase+0x1E
153 #define MB_DEMOD_B_DRV_CNT MBRegBase+0x1F
154
155
156
157 #ifdef MS_DEBUG
158 #define DBG_INTERN_DVBC(x) x
159 #define DBG_GET_SIGNAL_DVBC(x) x
160 #define DBG_INTERN_DVBC_TIME(x) x
161 #define DBG_INTERN_DVBC_LOCK(x) x
162 #define INTERN_DVBC_INTERNAL_DEBUG 0
163 #define ADAPTIVE_CLOCK_PRINT(x) x
164 #define ADAPTIVE_CLOCK_PRINT2(x) x
165 #define ADAPTIVE_CLOCK_PRINT3(x) x
166 #else
167 #define DBG_INTERN_DVBC(x) //x
168 #define DBG_GET_SIGNAL_DVBC(x) //x
169 #define DBG_INTERN_DVBC_TIME(x) //x
170 #define DBG_INTERN_DVBC_LOCK(x) //x
171 #define INTERN_DVBC_INTERNAL_DEBUG 0
172 #define ADAPTIVE_CLOCK_PRINT(x) //x
173 #define ADAPTIVE_CLOCK_PRINT2(x) //x
174 #define ADAPTIVE_CLOCK_PRINT3(x) //x
175 #endif
176 #define DBG_DUMP_LOAD_DSP_TIME 0
177
178
179 //#define SIGNAL_LEVEL_OFFSET 0.00f
180 //#define TAKEOVERPOINT -60.0f
181 //#define TAKEOVERRANGE 0.5f
182 //#define LOG10_OFFSET -0.21f
183 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
184 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
185
186 #define TUNER_IF 36167
187
188 #define TS_SER_C 0x00 //0: parallel 1:serial
189
190 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
191 #define TS_INV_C 0x01
192 #else
193 #define TS_INV_C 0x00
194 #endif
195
196 #define DVBC_FS 45474 //24000
197 #define CFG_ZIF 0x00 //For ZIF ,FC=0
198 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
199 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
200 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
201 #define FS_L_C (DVBC_FS&0xFF)
202 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
203 #define IQ_SWAP_C 0x00
204 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
205 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
206 // Symbol Rate: 6875 = 0x1ADB
207 // Symbol Rate: 6900 = 0x1AF4
208 // Symbol Rate: 7000 = 0x1B58
209 // Symbol Rate: 4000 = 0x0FA0
210 // Symbol Rate: 6125 = 0x17ED
211 #define SR0_H 0x1A
212 #define SR0_L 0xF4 //6900
213 #define SR1_H 0x1B
214 #define SR1_L 0x58 //7000
215 #define SR2_H 0x17
216 #define SR2_L 0xED //6125
217 #define SR3_H 0x0F
218 #define SR3_L 0xA0 //4000
219 #define SR4_H 0x1B
220 #define SR4_L 0x26 //6950
221 #define SR5_H 0x1A //0xDB
222 #define SR5_L 0xDB //0x1A //6875
223 #define SR6_H 0x1C
224 #define SR6_L 0x20 //7200
225 #define SR7_H 0x1C
226 #define SR7_L 0x52 //7250
227 #define SR8_H 0x0B
228 #define SR8_L 0xB8 //3000
229 #define SR9_H 0x03
230 #define SR9_L 0xE8 //1000
231 #define SR10_H 0x07
232 #define SR10_L 0xD0 //2000
233 #define SR11_H 0x00
234 #define SR11_L 0x00 //0000
235
236
237 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
238
239 // SAR dependent
240 #define NO_SIGNAL_TH_A 0xA3
241 // Tuner dependent
242 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
243 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
244 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
245 #define NO_SIGNAL_TH_C_H 0xff //0x00
246 #define DAGC1_REF 0x70
247 #define DAGC2_REF 0x30
248 #define AGC_REF_L 0x00
249 #define AGC_REF_H 0x06
250
251 #define INTERN_AUTO_SR_C 1
252 #define INTERN_AUTO_QAM_C 1
253
254 #define ATV_DET_EN 1
255
256 // Need to update when:
257 // Case#1: New add DSP parameters
258 // Case#2: Use exist DSP parameters to another applications/functions
259 #define UTOPIA_DRIVER_VERSION 0x01 // Update by user.
260
261 #if 0
262 MS_U8 INTERN_DVBC_DSPREG[] =
263 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
264 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
265 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
266 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
267 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
268 };
269 #else
270 MS_U8 INTERN_DVBC_DSPREG_dmd0[] =
271 {
272 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
273 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
274 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
275 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
276 0x05, 0x40, 0x04, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
277 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
278 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
279 };
280
281 MS_U8 INTERN_DVBC_DSPREG_dmd1[] =
282 {
283 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
284 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0xA0, 0x0F, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
285 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
286 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
287 0x05, 0x40, 0x34, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
288 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
289 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
290 };
291 #endif
292 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
293
294 //-----------------------------------------------------------------------
295 /****************************************************************
296 *Local Variables *
297 ****************************************************************/
298
299 //static MS_BOOL TPSLock = 0;
300 static MS_U32 u32ChkScanTimeStartDVBC = 0;
301 static MS_U8 g_dvbc_lock = 0;
302
303 //Global Variables
304 S_CMDPKTREG gsCmdPacketDVBC;
305 //MS_U8 gCalIdacCh0, gCalIdacCh1;
306 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
307 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
308 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
309 MS_U8 INTERN_DVBC_table[] = {
310 #include "fwDMD_INTERN_DVBC.dat"
311 };
312
313 #endif
314
315 static MS_U8 hal_demod_swtich_status=0xff; //0xff: switch haven't to be assert 0x00 or 0x01 :latest mornitor demod
316 //****************duel demod parameters*******************************
317 //demod 0 parameters
318 //static MS_BOOL TPSLock = 0;
319 static MS_U8 g_dvbc_lock_dmd0 = 0;
320
321 //Global Variables
322 S_CMDPKTREG gsCmdPacketDVBC_dmd0;
323 //MS_U8 gCalIdacCh0, gCalIdacCh1;
324 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower_dmd0 = FALSE;
325 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower_dmd0 = 0;
326
327
328 //static MS_BOOL TPSLock = 0;
329 static MS_U8 g_dvbc_lock_dmd1 = 0;
330
331 //Global Variables
332 S_CMDPKTREG gsCmdPacketDVBC_dmd1;
333 //MS_U8 gCalIdacCh0, gCalIdacCh1;
334 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower_dmd1 = FALSE;
335 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower_dmd1 = 0;
336 //****************end of duel demod parameters*******************************
337
338 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
339 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
340 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
341 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
342 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW);
343 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
344 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
345 //MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
346
347 #if (INTERN_DVBC_INTERNAL_DEBUG)
348 void INTERN_DVBC_info(void);
349 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
350 #endif
351
352
INTERN_DVBC_ActiveDmdSwitch(MS_U8 demod_no)353 MS_BOOL INTERN_DVBC_ActiveDmdSwitch(MS_U8 demod_no)
354 {
355 MS_BOOL status = TRUE;
356 //MS_U8 temp_val;
357
358 if(demod_no==0 && (hal_demod_swtich_status!= 0x00))
359 {
360 //copy parameter
361 //INTERN_DVBC_DSPREG=INTERN_DVBC_DSPREG;
362 //static MS_U32 u32ChkScanTimeStartDVBC = 0;
363 g_dvbc_lock_dmd1 = g_dvbc_lock;
364 //Global Variables
365 gsCmdPacketDVBC_dmd1=gsCmdPacketDVBC;
366 bDMD_DVBC_NoChannelDetectedWithRFPower_dmd1 = bDMD_DVBC_NoChannelDetectedWithRFPower;
367 u32DMD_DVBC_NoChannelTimeAccWithRFPower_dmd1 = u32DMD_DVBC_NoChannelTimeAccWithRFPower;
368
369 g_dvbc_lock = g_dvbc_lock_dmd0;
370 //Global Variables
371 gsCmdPacketDVBC=gsCmdPacketDVBC_dmd0;
372 bDMD_DVBC_NoChannelDetectedWithRFPower = bDMD_DVBC_NoChannelDetectedWithRFPower_dmd0;
373 u32DMD_DVBC_NoChannelTimeAccWithRFPower = u32DMD_DVBC_NoChannelTimeAccWithRFPower_dmd0;
374 //temp_val=HAL_DMD_RIU_ReadByte(0x101e3c); mark
375 //temp_val&=(~0x10); mark
376 //HAL_DMD_RIU_WriteByte(0x101e3c,temp_val);mark
377 }
378 else if(demod_no==1 && (hal_demod_swtich_status!= 0x01))
379 {
380 //copy parameter
381 //INTERN_DVBC_DSPREG=INTERN_DVBC_DSPREG;
382 //static MS_U32 u32ChkScanTimeStartDVBC = 0;
383 g_dvbc_lock_dmd0 = g_dvbc_lock;
384 //Global Variables
385 gsCmdPacketDVBC_dmd0=gsCmdPacketDVBC;
386 bDMD_DVBC_NoChannelDetectedWithRFPower_dmd0 = bDMD_DVBC_NoChannelDetectedWithRFPower;
387 u32DMD_DVBC_NoChannelTimeAccWithRFPower_dmd0 = u32DMD_DVBC_NoChannelTimeAccWithRFPower;
388
389
390 //copy parameter
391 //INTERN_DVBC_DSPREG=INTERN_DVBC_DSPREG;
392 //static MS_U32 u32ChkScanTimeStartDVBC = 0;
393 g_dvbc_lock = g_dvbc_lock_dmd1;
394 //Global Variables
395 gsCmdPacketDVBC=gsCmdPacketDVBC_dmd1;
396 bDMD_DVBC_NoChannelDetectedWithRFPower = bDMD_DVBC_NoChannelDetectedWithRFPower_dmd1;
397 u32DMD_DVBC_NoChannelTimeAccWithRFPower = u32DMD_DVBC_NoChannelTimeAccWithRFPower_dmd1;
398 //temp_val=HAL_DMD_RIU_ReadByte(0x101e3c);mark
399 //temp_val|=(0x10); mark
400 //HAL_DMD_RIU_WriteByte(0x101e3c,temp_val);mark
401 //hal_demod_swtich_status=1;
402 }
403
404 hal_demod_swtich_status=demod_no;
405 return status;
406 }
407
408
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)409 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
410 {
411 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
412 MS_U8 status = TRUE;
413 MS_U16 u16DspAddr = 0;
414
415 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init\n"));
416
417 #if 0//def MS_DEBUG
418 {
419 MS_U8 u8buffer[256];
420 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Reset\n");
421 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
422 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
423
424 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
425 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
426 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
427 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
428 ULOGD("DEMOD","%x ", u8buffer[idx]);
429 ULOGD("DEMOD","\n");
430
431 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init Value\n");
432 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
433 ULOGD("DEMOD","%x ", INTERN_DVBC_DSPREG[idx]);
434 ULOGD("DEMOD","\n");
435 }
436 #endif
437
438 //for k6lite modified
439 /*
440 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
441 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
442 */
443 if(hal_demod_swtich_status==0) //demod no =0
444 {
445 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG_dmd0); idx++)
446 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx+PARA_TBL_LENGTH*hal_demod_swtich_status, INTERN_DVBC_DSPREG_dmd0[idx]);
447 }
448 else if(hal_demod_swtich_status==1) //demod no =1
449 {
450 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG_dmd1); idx++)
451 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx+PARA_TBL_LENGTH*hal_demod_swtich_status, INTERN_DVBC_DSPREG_dmd1[idx]);
452 }
453
454 // readback to confirm.
455 #ifdef MS_DEBUG
456 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
457 {
458 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
459 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
460 {
461 ULOGD("DEMOD","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
462 }
463 }
464 #endif
465
466 //note:k6lite modified
467 if (u8DVBC_DSPReg != NULL)
468 {
469 if (1 == u8DVBC_DSPReg[0])
470 {
471 u8DVBC_DSPReg+=2;
472 for (idx = 0; idx<u8Size; idx++)
473 {
474 u16DspAddr = *u8DVBC_DSPReg;
475 u8DVBC_DSPReg++;
476 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
477 u8DVBC_DSPReg++;
478 u8Mask = *u8DVBC_DSPReg;
479 u8DVBC_DSPReg++;
480 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr+PARA_TBL_LENGTH*hal_demod_swtich_status, &u8RegRead);
481 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
482 u8DVBC_DSPReg++;
483 DBG_INTERN_DVBC(ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
484 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr+PARA_TBL_LENGTH*hal_demod_swtich_status, u8RegWrite);
485 }
486 }
487 else
488 {
489 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
490 }
491 }
492
493 #if 0//def MS_DEBUG
494 {
495 MS_U8 u8buffer[256];
496 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
497 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
498 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadBack\n");
499 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
500 ULOGD("DEMOD","%x ", u8buffer[idx]);
501 ULOGD("DEMOD","\n");
502 }
503 #endif
504
505 #if 0//def MS_DEBUG
506 {
507 MS_U8 u8buffer[256];
508 for (idx = 0; idx<128; idx++)
509 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
510 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
511 for (idx = 0; idx<128; idx++)
512 {
513 ULOGD("DEMOD","%x ", u8buffer[idx]);
514 if ((idx & 0xF) == 0xF) ULOGD("DEMOD","\n");
515 }
516 ULOGD("DEMOD","\n");
517 }
518 #endif
519
520 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_PARAM_VERSION, UTOPIA_DRIVER_VERSION) != TRUE)
521 {
522 printf("INTERN_DVBC_DSPReg_Init NG\n"); return FALSE;
523 }
524 return status;
525 }
526
527 /***********************************************************************************
528 Subject: Command Packet Interface
529 Function: INTERN_DVBC_Cmd_Packet_Send
530 Parmeter:
531 Return: MS_BOOL
532 Remark:
533 ************************************************************************************/
534 //didn't use in k6-lite
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)535 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
536 {
537 MS_U8 status = true, indx;
538 MS_U8 reg_val, timeout = 0;
539 return TRUE;
540 // ==== Command Phase ===================
541 DBG_INTERN_DVBC(ULOGD("DEMOD","--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
542 pCmdPacket->param[0],pCmdPacket->param[1],
543 pCmdPacket->param[2],pCmdPacket->param[3],
544 pCmdPacket->param[4],pCmdPacket->param[5] ));
545
546 // wait _BIT_END clear
547 do
548 {
549 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
550 if((reg_val & _BIT_END) != _BIT_END)
551 {
552 break;
553 }
554 MsOS_DelayTask(5);
555 if (timeout > 200)
556 {
557 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
558 return false;
559 }
560 timeout++;
561 } while (1);
562
563 // set cmd_3:0 and _BIT_START
564 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
565 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
566 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
567
568
569 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
570 // wait _BIT_START clear
571 do
572 {
573 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
574 if((reg_val & _BIT_START) != _BIT_START)
575 {
576 break;
577 }
578 MsOS_DelayTask(10);
579 if (timeout > 200)
580 {
581 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
582 return false;
583 }
584 timeout++;
585 } while (1);
586
587 // ==== Data Phase ======================
588
589 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
590
591 for (indx = 0; indx < param_cnt; indx++)
592 {
593 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
594 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
595
596 // set param[indx] and _BIT_DRQ
597 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
598 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
599 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
600
601 // wait _BIT_DRQ clear
602 do
603 {
604 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
605 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
606 {
607 break;
608 }
609 MsOS_DelayTask(5);
610 if (timeout > 200)
611 {
612 ULOGD("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
613 return false;
614 }
615 timeout++;
616 } while (1);
617 }
618
619 // ==== End Phase =======================
620
621 // set _BIT_END to finish command
622 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
623 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
624 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
625 return status;
626 }
627
628
629 /***********************************************************************************
630 Subject: Command Packet Interface
631 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
632 Parmeter:
633 Return: MS_BOOL
634 Remark:
635 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)636 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
637 {
638 return TRUE;
639 }
640
641 /***********************************************************************************
642 Subject: SoftStop
643 Function: INTERN_DVBC_SoftStop
644 Parmeter:
645 Return: MS_BOOL
646 Remark:
647 ************************************************************************************/
648
INTERN_DVBC_SoftStop(void)649 MS_BOOL INTERN_DVBC_SoftStop ( void )
650 {
651 #if 1
652 MS_U16 u8WaitCnt=0;
653
654 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
655 {
656 ULOGD("DEMOD",">> MB Busy!\n");
657 return FALSE;
658 }
659
660 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
661
662 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
663 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
664
665 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
666 {
667 #if TEST_EMBEDED_DEMOD
668 MsOS_DelayTask(1); // << Ken 20090629
669 #endif
670 if (u8WaitCnt++ >= 0x7FFF)
671 {
672 ULOGD("DEMOD",">> DVBT SoftStop Fail!\n");
673 return FALSE;
674 }
675 }
676
677 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
678 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
679 #endif
680 return TRUE;
681 }
682
683
684 /***********************************************************************************
685 Subject: Reset
686 Function: INTERN_DVBC_Reset
687 Parmeter:
688 Return: MS_BOOL
689 Remark:
690 ************************************************************************************/
691 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
692
693 //in K6 lite, this action is to disable the specified demodulator
INTERN_DVBC_Reset(void)694 MS_BOOL INTERN_DVBC_Reset ( void )
695 {
696 MS_U8 reg_val=0;
697 MS_U8 status=true;
698 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_reset\n"));
699
700 //DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
701
702 /*
703 INTERN_DVBC_SoftStop();
704
705
706 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
707 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
708 MsOS_DelayTask(5);
709 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
710 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
711 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
712 MsOS_DelayTask(5);
713
714 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
715 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
716 */
717
718 //for K6 lite, disable certain demodulator
719 MDrv_SYS_DMD_VD_MBX_ReadReg(DEMOD_ACTIVE_REG,®_val );
720 reg_val&=~(0x01<<hal_demod_swtich_status);
721 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DEMOD_ACTIVE_REG,reg_val);
722
723 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
724 g_dvbc_lock = 0;
725
726 return TRUE;
727 }
728
729 /***********************************************************************************
730 Subject: Exit
731 Function: INTERN_DVBC_Exit
732 Parmeter:
733 Return: MS_BOOL
734 Remark:
735 ************************************************************************************/
INTERN_DVBC_Exit(void)736 MS_BOOL INTERN_DVBC_Exit ( void )
737 {
738
739 INTERN_DVBC_SoftStop();
740
741 //add for SRAM clock power saving mechanism
742
743 // This file is translated by Steven Hung's riu2script.pl
744
745 // ("==============================================================");
746 // ("Start demod top initial setting by HK MCU ......");
747 // ("==============================================================");
748 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
749 // 1'b0->reg_DMDTOP control by HK_MCU.
750 // 1'b1->reg_DMDTOP control by DMD_MCU.
751 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
752 // 1'b0->reg_DMDANA control by HK_MCU.
753 // 1'b1->reg_DMDANA control by DMD_MCU.
754 // ("select HK MCU ......");
755 // `RIU_W((`RIUBASE_CHIPTOP>>1)+7'h1c, 2'b10, 16'h0000);
756 //wriu 0x101e39 0x00
757 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
758
759
760 // ("==============================================================");
761 // ("Start TOP CLKGEN initial setting ......");
762 // ("==============================================================");
763 // CLK_DMDMCU clock setting
764 // reg_ckg_dmdmcu@0x0f[4:0]
765 // [0] : disable clock
766 // [1] : invert clock
767 // [4:2]:
768 // 000:170 MHz(MPLL_DIV_BUF)
769 // 001:160MHz
770 // 010:144MHz
771 // 011:123MHz
772 // 100:108MHz (Kriti:DVBT2)
773 // 101:mem_clcok
774 // 110:mem_clock div 2
775 // 111:select XTAL
776 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h0010);
777 //wriu 0x10331e 0x11
778 HAL_DMD_RIU_WriteByte(0x10331e,0x11);
779
780
781 // set parallel ts clock
782 // [11] : reg_ckg_demod_test_in_en = 0
783 // 0: select internal ADC CLK
784 // 1: select external test-in clock
785 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
786 // 0: select gated clock
787 // 1: select free-run clock
788 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
789 // 0: normal phase to pad
790 // 1: invert phase to pad
791 // [8] : reg_ckg_atsc_dvb_div_sel = 1
792 // 0: select clk_dmplldiv5
793 // 1: select clk_dmplldiv3
794 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
795 // Demod TS output clock phase tuning number
796 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
797 // Demod TS output clock is equal Demod TS internal working clock.
798 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0513);
799 // wriu 0x103301 0x05
800 // wriu 0x103300 0x13
801
802
803 // set parallel ts clock
804 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
805 // Demod TS output clock phase tuning number
806 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
807 // Demod TS output clock is equal Demod TS internal working clock.
808
809 // enable DVBTC ts clock
810 // [11:8]: reg_ckg_dvbtc_ts0
811 // [8] : disable clock
812 // [9] : invert clock
813 // [11:10]: Select clock source
814 // 00:clk_atsc_dvb_div
815 // 01:62 MHz
816 // 10:54 MHz
817 // 11:reserved
818 // [15:12]: reg_ckg_dvbtc_ts1
819 // [12] : disable clock
820 // [13] : invert clock
821 // [15:14]: Select clock source
822 // 00:clk_atsc_dvb_div
823 // 01:62 MHz
824 // 10:54 MHz
825 // 11:reserved
826 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0013);
827 //wriu 0x103309 0x11
828 HAL_DMD_RIU_WriteByte(0x103309,0x11);
829
830
831 // enable dvbc adc clock
832 // [3:0]: reg_ckg_dvbtc_adc
833 // [0] : disable clock
834 // [1] : invert clock
835 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
836 // 00: clk_dmdadc
837 // 01: clk_dmdadc_div2
838 // 10: clk_dmdadc_div4
839 // 11: DFT_CLK
840 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
841 //wriu 0x103314 0x11
842 HAL_DMD_RIU_WriteByte(0x103314,0x11);
843
844
845 // Reset TS divider
846 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
847 // wriu 0x103302 0x01
848
849 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
850 // wriu 0x103302 0x00
851
852 // ("==============================================================");
853 // ("Start demod CLKGEN setting ......");
854 // ("==============================================================");
855 // enable atsc_adcd_sync clock
856 // [3:0] : reg_ckg_atsc_adcd_sync
857 // [0] : disable clock
858 // [1] : invert clock
859 // [3:2]: Select clock source
860 // 00: clk_dmdadc_sync
861 // 01: 1'b0
862 // 10: 1'b0
863 // 11: DFT_CLK
864 // [11:8] : reg_ckg_dmd_dma
865 // [8] : disable clock
866 // [9] : invert clock
867 // [11:10]: Select clock source
868 // 00: clk_dmdadc
869 // 01: clk_dmdadc_div2_buf
870 // 10: 1'b0
871 // 11: DFT_CLK
872 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
873 //wriu 0x10200b 0x11
874 //wriu 0x10200a 0x11
875 HAL_DMD_RIU_WriteByte(0x10200b,0x11);
876 HAL_DMD_RIU_WriteByte(0x10200a,0x11);
877
878
879 // -------------------- symbol rate det -----------------------//
880 // [7:4] : reg_ckg_dvbtm_adc0p5x
881 // [4] : disable clock
882 // [5] : invert clock
883 // [7:6]: Select clock source
884 // 00: adc_clk_div2_buf
885 // 01: mpll_clk9_buf
886 // 10: 1'b0
887 // 11: DFT_CLK
888 // [11:8] reg_ckg_dvbtm_adc1x_eq1x
889 // [8] : disable clock
890 // [9] : invert clock
891 // [11:10]: Select clock source
892 // 00: adc_clk_buf
893 // 01: mpll_clk18_buf
894 // 10: 1'b0
895 // 11: DFT_CLK
896 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
897 //wriu 0x102021 0x11
898 //wriu 0x102020 0x11
899 HAL_DMD_RIU_WriteByte(0x102021,0x11);
900 HAL_DMD_RIU_WriteByte(0x102020,0x11);
901
902
903 // [3:0] : reg_ckg_dvbs2_ldpc_inner_sram
904 // [0] : disable clock
905 // [1] : invert clock
906 // [3:2]: Select clock source
907 // 00: clk_dvbs2_outer_mux8
908 // 01: adc_clk_buf
909 // 10: mpll_clk18_buf
910 // 11: 1'b0
911 // [7:4] : reg_ckg_dvbs_viterbi_sram
912 // [4] : disable clock
913 // [5] : invert clock
914 // [7:6] : Select clock source
915 // 00: clk_dvbs2_outer_mux8
916 // 01: adc_clk_buf
917 // 10: mpll_clk18_buf
918 // 11: DFT_CLK
919 // [12:8] : reg_ckg_dvbs_rs_deint_sram
920 // [8] : disable clock
921 // [9] : invert clock
922 // [12:10] : Select clock source
923 // 000: clk_dvbs2_outer_mux8
924 // 001: clk_dvbs_outer1x_pre_mux4
925 // 010: adc_clk_buf
926 // 011: mpll_clk18_buf
927 // 100: clk_dvbtc_outer2x_c_p
928
929 // @0x3518
930 // [4:0]: reg_ckg_dvbs2_outer_rs_adc
931 // [0] : disable clock
932 // [1] : invert clock
933 // [3:2]: Select clock source
934 // 000: clk_dvbs2_outer_mux8
935 // 001: clk_dvbs_rs_p
936 // 010: adc_clk_buf
937 // 011: mpll_clk18_buf
938 // 100: clk_dvbtc_outer2x_c_p
939
940 // [3:0] reg_ckg_dvbs2_ldpc_inner_sram = 4'h4 (for symbol rate det)
941 // [7:4] reg_ckg_dvbs_viterbi_sram = 4'h4 (for symbol rate det)
942 // [12:8] reg_ckg_dvbs_rs_deint_sram = 4'h4 (only for outer)
943
944 // 0x18
945 // [4:0] reg_ckg_dvbs2_outer_rs_adc = 4'h8 (for symbol rate det)
946 // [11:8] reg_ckg_dvbs2_ldpc_inner_j83b_sram
947 // [15:12] reg_ckg_dvbs_viterbi_j83b_sram
948
949 // 0x19
950 // [4:0] reg_ckg_dvbs2_outer_rs_adc_j83b
951 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0844);
952 // wriu 0x102029 0x11
953 // wriu 0x102028 0x11
954 HAL_DMD_RIU_WriteByte(0x102029,0x11);
955 HAL_DMD_RIU_WriteByte(0x102028,0x11);
956 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h4408);
957 // wriu 0x102031 0x11
958 // wriu 0x102030 0x11
959 HAL_DMD_RIU_WriteByte(0x102031,0x11);
960 HAL_DMD_RIU_WriteByte(0x102030,0x11);
961 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b01, 16'h0008);
962 //wriu 0x102032 0x11
963 HAL_DMD_RIU_WriteByte(0x102032,0x11);
964 // -----------------------------------------------------------//
965
966 // DVBC
967 // 0x17
968 // [3:0] reg_ckg_dvbtc_eq
969 // [7:4] reg_ckg_dvbtc_eq8x
970 // [11:8] reg_ckg_dvbtc_innc
971 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
972 //wriu 0x10202f 0x11
973 //wriu 0x10202e 0x11
974
975 HAL_DMD_RIU_WriteByte(0x10202f,0x11);
976 HAL_DMD_RIU_WriteByte(0x10202e,0x11);
977
978 // @0x3516
979 // [4:0] : reg_ckg_dvbtc_outer2x_c
980 // [0] : disable clock
981 // [1] : invert clock
982 // [4:2]: Select clock source
983 // 000: clk_dmplldiv10_buf
984 // 001: clk_dmplldiv10_div2_buf
985 // 010: clk_dmdadc
986 // 011: clk_dmdadc_div2_buf
987 // 100: clk_dmplldiv2_div8_buf
988 // 101: mpll_clk96_buf
989 // 110: mpll_clk48_buf
990 // 110: 1'b0
991 // [11:8] : reg_ckg_adcd_dvbs_rs
992 // [8] : disable clock
993 // [9] : invert clock
994 // [11:10] : Select clock source
995 // 00: adc_clk_buf
996 // 01: clk_dvbs_rs_p
997 // 10: mpll_clk18_buf
998 // 11:
999 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0400);
1000 //wriu 0x10202d 0x11
1001 //wriu 0x10202c 0x11
1002 HAL_DMD_RIU_WriteByte(0x10202d,0x11);
1003 HAL_DMD_RIU_WriteByte(0x10202c,0x11);
1004
1005 // 0x11
1006 // [3:0] reg_ckg_dvbs2_inner
1007 // [7:4] reg_ckg_dvbs_outer1x <-- clk_dvbtc_outer2x_c_p
1008 // [7:4] : reg_ckg_dvbs_outer1x
1009 // [4] : disable clock
1010 // [5] : invert clock
1011 // [7:6] : Select clock source
1012 // 00: adc_clk_buf
1013 // 01: clk_dvbtc_outer2x_c_p
1014 // 10: 1'b0
1015 // 11: DFT_CLK
1016 // [10:8] reg_ckg_dvbs_outer2x
1017 // [15:12] reg_ckg_dvbs2_oppro
1018 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b01, 16'h0041);
1019 //wriu 0x102022 0x11
1020 HAL_DMD_RIU_WriteByte(0x102022,0x11);
1021
1022
1023
1024 // @0x3512
1025 // [4:0] : reg_ckg_dvbs_rs
1026 // [0] : disable clock
1027 // [1] : invert clock
1028 // [4:2]: Select clock source
1029 // 000: mpll_clk216_buf
1030 // 001: 1'b0
1031 // 010: 1'b0
1032 // 011: 1'b0
1033 // [12:8] : reg_ckg_dvbs2_outer //for dvbs2 outer ldpc sram share reset
1034 // [8] : disable clock
1035 // [9] : invert clock
1036 // [12:10] : Select clock source
1037 // 000: mpll_clk288_buf
1038 // 001: mpll_clk216_buf
1039 // 010: 1'b0
1040 // 011: 1'b0
1041 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0400);
1042 // wriu 0x102025 0x11
1043 // wriu 0x102024 0x11
1044 HAL_DMD_RIU_WriteByte(0x102025,0x11);
1045 HAL_DMD_RIU_WriteByte(0x102024,0x11);
1046
1047
1048 // @0x3513
1049 // [4:0] : reg_ckg_dvbtm_ts_in
1050 // [0] : disable clock
1051 // [1] : invert clock
1052 // [4:2]: Select clock source
1053 // 000: clk_dvbtc_rs_p
1054 // 001: dvb_clk48_buf
1055 // 010: dvb_clk43_buf
1056 // 011: clk_dvbs_outer1x_pre_mux4
1057 // 100: clk_dvbs2_oppro_pre_mux4
1058 // 101: 1'b0
1059 // 110: 1'b0
1060 // 111: 1'b0
1061 // [11:8] : reg_ckg_dvbs2_diseqc
1062 // [8] : disable clock
1063 // [9] : invert clock
1064 // [11:10] : Select clock source
1065 // 00: xtali_clk24_buf
1066 // 01: xtali_clk12_buf
1067 // 10: xtali_clk6_buf
1068 // 11: xtali_clk3
1069 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h13, 2'b01, 16'h0100);
1070 //wriu 0x102026 0x11
1071 HAL_DMD_RIU_WriteByte(0x102026,0x11);
1072
1073 // @0x351a
1074 // [12:8] : reg_ckg_dvbtm_ts_in_adc
1075 // [0] : disable clock
1076 // [1] : invert clock
1077 // [4:2]: Select clock source
1078 // 000: clk_dvbtc_rs_p
1079 // 001: dvb_clk48_buf
1080 // 010: dvb_clk43_buf
1081 // 011: clk_dvbs_outer1x_pre_mux4
1082 // 100: clk_dvbs2_oppro_pre_mux4
1083 // 101: 1'b0
1084 // 110: 1'b0
1085 // 111: 1'b0
1086 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b10, 16'h0000);
1087 // wriu 0x102035 0x11
1088 HAL_DMD_RIU_WriteByte(0x102035,0x11);
1089
1090 // 0 reg_force_allsram_on
1091 // 1 reg_adcdma_sram_sd_en = 1
1092 // 2 reg_dvbs2_inner_sram_sd_en = 1
1093 // 4 reg_dvbs2_outer_sram_sd_en = 1
1094 // 5 reg_dvbs_outer_sram_sd_en = 1
1095 // 6 reg_dvbc_outer_sram_sd_en = 1
1096 // 7 reg_dvbc_inner_0_sram_sd_en = 1
1097 // 8 reg_dvbc_inner_1_sram_sd_en = 1
1098 // 9 reg_dvbt_t2_ts_0_sram_sd_en = 1
1099 // 10 reg_dvbt_t2_ts_1_sram_sd_en = 1
1100 // 11 reg_sram_share_sram_sd_en = 1
1101 // wriu 0x102104 0xf6
1102 // wriu 0x102105 0x0f
1103 HAL_DMD_RIU_WriteByte(0x102104,0xf6);
1104 HAL_DMD_RIU_WriteByte(0x102105,0x0f);
1105
1106 // ("==============================================================");
1107 // ("End demod top initial setting by HK MCU ......");
1108 // ("==============================================================");
1109
1110
1111 return TRUE;
1112 }
1113
1114 /***********************************************************************************
1115 Subject: Load DSP code to chip
1116 Function: INTERN_DVBC_LoadDSPCode
1117 Parmeter:
1118 Return: MS_BOOL
1119 Remark:
1120 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)1121 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
1122 {
1123 MS_U8 udata = 0x00;
1124 MS_U16 i;
1125 MS_U16 fail_cnt=0;
1126
1127 #if (DBG_DUMP_LOAD_DSP_TIME==1)
1128 MS_U32 u32Time;
1129 #endif
1130
1131
1132 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
1133 BININFO BinInfo;
1134 MS_BOOL bResult;
1135 MS_U32 u32GEAddr;
1136 MS_U8 Data;
1137 MS_S8 op;
1138 MS_U32 srcaddr;
1139 MS_U32 len;
1140 MS_U32 SizeBy4K;
1141 MS_U16 u16Counter=0;
1142 MS_U8 *pU8Data;
1143 #endif
1144
1145 #if 0
1146 if(HAL_DMD_RIU_ReadByte(0x101E3E))
1147 {
1148 ULOGD("DEMOD","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
1149 return FALSE;
1150 }
1151 #endif
1152
1153 // MDrv_Sys_DisableWatchDog();
1154
1155
1156 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
1157 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
1158 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
1159 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
1160 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
1161 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
1162
1163 //// Load code thru VDMCU_IF ////
1164 DBG_INTERN_DVBC(ULOGD("DEMOD",">Load Code.....\n"));
1165 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
1166 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
1167 {
1168 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
1169 }
1170 #else
1171 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
1172 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
1173 if ( bResult != PASS )
1174 {
1175 return FALSE;
1176 }
1177 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
1178
1179 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
1180 InfoBlock_Flash_2_Checking_Start(&BinInfo);
1181 #endif
1182
1183 #if OBA2
1184 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
1185 #else
1186 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
1187 #endif
1188
1189 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
1190 InfoBlock_Flash_2_Checking_End(&BinInfo);
1191 #endif
1192
1193 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
1194 SizeBy4K=BinInfo.B_Len/0x1000;
1195 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
1196
1197 #if (DBG_DUMP_LOAD_DSP_TIME==1)
1198 u32Time = msAPI_Timer_GetTime0();
1199 #endif
1200
1201 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
1202
1203 for (i=0;i<=SizeBy4K;i++)
1204 {
1205 if(i==SizeBy4K)
1206 len=BinInfo.B_Len%0x1000;
1207 else
1208 len=0x1000;
1209
1210 srcaddr = u32GEAddr+(0x1000*i);
1211 //ULOGD("DEMOD","\t i = %08X\n", i);
1212 //ULOGD("DEMOD","\t len = %08X\n", len);
1213 op = 1;
1214 u16Counter = 0 ;
1215 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
1216 while(len--)
1217 {
1218 u16Counter ++ ;
1219 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
1220 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
1221 #if OBA2
1222 pU8Data = (MS_U8 *)(srcaddr);
1223 #else
1224 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
1225 #endif
1226 Data = *pU8Data;
1227
1228 #if 0
1229 if(u16Counter < 0x100)
1230 ULOGD("DEMOD","0x%bx,", Data);
1231 #endif
1232 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
1233
1234 srcaddr += op;
1235 }
1236 // ULOGD("DEMOD","\n\n\n");
1237 }
1238
1239 #if (DBG_DUMP_LOAD_DSP_TIME==1)
1240 ULOGD("DEMOD","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
1241 #endif
1242
1243 #endif
1244
1245 //// Content verification ////
1246 DBG_INTERN_DVBC(ULOGD("DEMOD",">Verify Code...\n"));
1247
1248 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
1249 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
1250
1251 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
1252 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
1253 {
1254 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
1255 if (udata != INTERN_DVBC_table[i])
1256 {
1257 ULOGD("DEMOD",">fail add = 0x%x\n", i);
1258 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBC_table[i]);
1259 ULOGD("DEMOD",">data = 0x%x\n", udata);
1260
1261 if (fail_cnt > 10)
1262 {
1263 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
1264 return false;
1265 }
1266 fail_cnt++;
1267 }
1268 }
1269 #else
1270 for (i=0;i<=SizeBy4K;i++)
1271 {
1272 if(i==SizeBy4K)
1273 len=BinInfo.B_Len%0x1000;
1274 else
1275 len=0x1000;
1276
1277 srcaddr = u32GEAddr+(0x1000*i);
1278 //ULOGD("DEMOD","\t i = %08LX\n", i);
1279 //ULOGD("DEMOD","\t len = %08LX\n", len);
1280 op = 1;
1281 u16Counter = 0 ;
1282 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
1283 while(len--)
1284 {
1285 u16Counter ++ ;
1286 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
1287 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
1288 #if OBA2
1289 pU8Data = (MS_U8 *)(srcaddr);
1290 #else
1291 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
1292 #endif
1293 Data = *pU8Data;
1294
1295 #if 0
1296 if(u16Counter < 0x100)
1297 ULOGD("DEMOD","0x%bx,", Data);
1298 #endif
1299 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
1300 if (udata != Data)
1301 {
1302 ULOGD("DEMOD",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
1303 ULOGD("DEMOD",">code = 0x%x\n", Data);
1304 ULOGD("DEMOD",">data = 0x%x\n", udata);
1305
1306 if (fail_cnt++ > 10)
1307 {
1308 ULOGD("DEMOD",">DVB-C DSP Loadcode fail!");
1309 return false;
1310 }
1311 }
1312
1313 srcaddr += op;
1314 }
1315 // ULOGD("DEMOD","\n\n\n");
1316 }
1317 #endif
1318
1319 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
1320 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
1321 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
1322 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
1323
1324 DBG_INTERN_DVBC(ULOGD("DEMOD",">DSP Loadcode done."));
1325 //while(load_data_variable);
1326 #if 0
1327 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
1328 INTERN_DVBC_Active(ENABLE);
1329 while(1);
1330 #endif
1331 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
1332
1333 return TRUE;
1334 }
1335
1336 /***********************************************************************************
1337 Subject: DVB-T CLKGEN initialized function
1338 Function: INTERN_DVBC_Power_On_Initialization
1339 Parmeter:
1340 Return: MS_BOOL
1341 Remark:
1342 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)1343 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
1344 {
1345
1346
1347 #if 0 //original init setting mark for SRAM clock power saving mechanism
1348 // MS_U8 temp_val;
1349
1350 HAL_DMD_RIU_WriteByte(0x103c0e, 0x00); //mux from DMD MCU to HK.
1351 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
1352
1353 //start of HK init script
1354 // This file is translated by Steven Hung's riu2script.pl
1355
1356 // ("==============================================================");
1357 // ("Start demod top initial setting by HK MCU ......");
1358 // ("==============================================================");
1359 // ("==============================================================");
1360 // ("Start TOP CLKGEN initial setting ......");
1361 // ("==============================================================");
1362 // CLK_DMDMCU clock setting
1363 // reg_ckg_dmdmcu@0x0f[4:0]
1364 // [0] : disable clock
1365 // [1] : invert clock
1366 // [4:2]:
1367 // 000:170 MHz(MPLL_DIV_BUF)
1368 // 001:160MHz
1369 // 010:144MHz
1370 // 011:123MHz
1371 // 100:108MHz (Kriti:DVBT2)
1372 // 101:mem_clcok
1373 // 110:mem_clock div 2
1374 // 111:select XTAL
1375 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h0010);
1376 //wriu 0x10331f 0x00
1377 //wriu 0x10331e 0x30
1378 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1379 HAL_DMD_RIU_WriteByte(0x10331e, 0x30);
1380
1381 // set parallet ts clock
1382 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1383 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1384 // wriu 0x103301 0x06
1385 // wriu 0x103300 0x19
1386 //clock rate setting
1387 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1388 HAL_DMD_RIU_WriteByte(0x103300, 0x0a);
1389
1390 // set parallel ts clock
1391 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1392 // Demod TS output clock phase tuning number
1393 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1394 // Demod TS output clock is equal Demod TS internal working clock.
1395
1396 // enable DVBTC ts clock
1397 // [11:8]: reg_ckg_dvbtc_ts0
1398 // [8] : disable clock
1399 // [9] : invert clock
1400 // [11:10]: Select clock source
1401 // 00:clk_atsc_dvb_div
1402 // 01:62 MHz
1403 // 10:54 MHz
1404 // 11:reserved
1405 // [15:12]: reg_ckg_dvbtc_ts1
1406 // [12] : disable clock
1407 // [13] : invert clock
1408 // [15:14]: Select clock source
1409 // 00:clk_atsc_dvb_div
1410 // 01:62 MHz
1411 // 10:54 MHz
1412 // 11:reserved
1413 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0013);
1414 //wriu 0x103309 0x00
1415 //wriu 0x103308 0x13
1416 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1417 HAL_DMD_RIU_WriteByte(0x103308, 0x0a);
1418
1419
1420 // enable dvbc adc clock
1421 // [3:0]: reg_ckg_dvbtc_adc
1422 // [0] : disable clock
1423 // [1] : invert clock
1424 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1425 // 00: clk_dmdadc
1426 // 01: clk_dmdadc_div2
1427 // 10: clk_dmdadc_div4
1428 // 11: DFT_CLK
1429 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1430 //wriu 0x103315 0x00
1431 //wriu 0x103314 0x00
1432 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1433 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1434
1435
1436 // Reset TS divider
1437 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
1438 //wriu 0x103302 0x01
1439 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1440
1441 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
1442 //wriu 0x103302 0x00
1443 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1444
1445 // ("==============================================================");
1446 // ("Start demod CLKGEN setting ......");
1447 // ("==============================================================");
1448 // enable atsc_adcd_sync clock
1449 // [3:0] : reg_ckg_atsc_adcd_sync
1450 // [0] : disable clock
1451 // [1] : invert clock
1452 // [3:2]: Select clock source
1453 // 00: clk_dmdadc_sync
1454 // 01: 1'b0
1455 // 10: 1'b0
1456 // 11: DFT_CLK
1457 // [11:8] : reg_ckg_dmd_dma
1458 // [8] : disable clock
1459 // [9] : invert clock
1460 // [11:10]: Select clock source
1461 // 00: clk_dmdadc
1462 // 01: clk_dmdadc_div2_buf
1463 // 10: 1'b0
1464 // 11: DFT_CLK
1465 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1466 //wriu 0x10200b 0x00
1467 //wriu 0x10200a 0x00
1468 HAL_DMD_RIU_WriteByte(0x10200b, 0x00);
1469 HAL_DMD_RIU_WriteByte(0x10200a, 0x00);
1470
1471
1472 // -------------------- symbol rate det -----------------------//
1473 // [7:4] : reg_ckg_dvbtm_adc0p5x
1474 // [4] : disable clock
1475 // [5] : invert clock
1476 // [7:6]: Select clock source
1477 // 00: adc_clk_div2_buf
1478 // 01: mpll_clk9_buf
1479 // 10: 1'b0
1480 // 11: DFT_CLK
1481 // [11:8] reg_ckg_dvbtm_adc1x_eq1x
1482 // [8] : disable clock
1483 // [9] : invert clock
1484 // [11:10]: Select clock source
1485 // 00: adc_clk_buf
1486 // 01: mpll_clk18_buf
1487 // 10: 1'b0
1488 // 11: DFT_CLK
1489 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1490 //wriu 0x102021 0x00
1491 //wriu 0x102020 0x00
1492 HAL_DMD_RIU_WriteByte(0x102021, 0x00);
1493 HAL_DMD_RIU_WriteByte(0x102020, 0x00);
1494
1495
1496 // [3:0] : reg_ckg_dvbs2_ldpc_inner_sram
1497 // [0] : disable clock
1498 // [1] : invert clock
1499 // [3:2]: Select clock source
1500 // 00: clk_dvbs2_outer_mux8
1501 // 01: adc_clk_buf
1502 // 10: mpll_clk18_buf
1503 // 11: 1'b0
1504 // [7:4] : reg_ckg_dvbs_viterbi_sram
1505 // [4] : disable clock
1506 // [5] : invert clock
1507 // [7:6] : Select clock source
1508 // 00: clk_dvbs2_outer_mux8
1509 // 01: adc_clk_buf
1510 // 10: mpll_clk18_buf
1511 // 11: DFT_CLK
1512 // [12:8] : reg_ckg_dvbs_rs_deint_sram
1513 // [8] : disable clock
1514 // [9] : invert clock
1515 // [12:10] : Select clock source
1516 // 000: clk_dvbs2_outer_mux8
1517 // 001: clk_dvbs_outer1x_pre_mux4
1518 // 010: adc_clk_buf
1519 // 011: mpll_clk18_buf
1520 // 100: clk_dvbtc_outer2x_c_p
1521
1522 // @0x3518
1523 // [4:0]: reg_ckg_dvbs2_outer_rs_adc
1524 // [0] : disable clock
1525 // [1] : invert clock
1526 // [3:2]: Select clock source
1527 // 000: clk_dvbs2_outer_mux8
1528 // 001: clk_dvbs_rs_p
1529 // 010: adc_clk_buf
1530 // 011: mpll_clk18_buf
1531 // 100: clk_dvbtc_outer2x_c_p
1532
1533 // [3:0] reg_ckg_dvbs2_ldpc_inner_sram = 4'h4 (for symbol rate det)
1534 // [7:4] reg_ckg_dvbs_viterbi_sram = 4'h4 (for symbol rate det)
1535 // [12:8] reg_ckg_dvbs_rs_deint_sram = 4'h4 (only for outer)
1536
1537 // 0x18
1538 // [4:0] reg_ckg_dvbs2_outer_rs_adc = 4'h8 (for symbol rate det)
1539 // [11:8] reg_ckg_dvbs2_ldpc_inner_j83b_sram
1540 // [15:12] reg_ckg_dvbs_viterbi_j83b_sram
1541
1542 // 0x19
1543 // [4:0] reg_ckg_dvbs2_outer_rs_adc_j83b
1544 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0844);
1545 //wriu 0x102029 0x08
1546 //wriu 0x102028 0x44
1547 HAL_DMD_RIU_WriteByte(0x102029, 0x08);
1548 HAL_DMD_RIU_WriteByte(0x102028, 0x44);
1549 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h4408);
1550 //wriu 0x102031 0x44
1551 //wriu 0x102030 0x08
1552 HAL_DMD_RIU_WriteByte(0x102031, 0x44);
1553 HAL_DMD_RIU_WriteByte(0x102030, 0x08);
1554 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b01, 16'h0008);
1555 //wriu 0x102032 0x08
1556 HAL_DMD_RIU_WriteByte(0x102032, 0x08);
1557 // -----------------------------------------------------------//
1558
1559 // DVBC
1560 // 0x17
1561 // [3:0] reg_ckg_dvbtc_eq
1562 // [7:4] reg_ckg_dvbtc_eq8x
1563 // [11:8] reg_ckg_dvbtc_innc
1564 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1565 //wriu 0x10202f 0x00
1566 //wriu 0x10202e 0x00
1567 HAL_DMD_RIU_WriteByte(0x10202f, 0x00);
1568 HAL_DMD_RIU_WriteByte(0x10202e, 0x00);
1569
1570 // @0x3516
1571 // [4:0] : reg_ckg_dvbtc_outer2x_c
1572 // [0] : disable clock
1573 // [1] : invert clock
1574 // [4:2]: Select clock source
1575 // 000: clk_dmplldiv10_buf
1576 // 001: clk_dmplldiv10_div2_buf
1577 // 010: clk_dmdadc
1578 // 011: clk_dmdadc_div2_buf
1579 // 100: clk_dmplldiv2_div8_buf
1580 // 101: mpll_clk96_buf
1581 // 110: mpll_clk48_buf
1582 // 110: 1'b0
1583 // [11:8] : reg_ckg_adcd_dvbs_rs
1584 // [8] : disable clock
1585 // [9] : invert clock
1586 // [11:10] : Select clock source
1587 // 00: adc_clk_buf
1588 // 01: clk_dvbs_rs_p
1589 // 10: mpll_clk18_buf
1590 // 11:
1591 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0400);
1592 //wriu 0x10202d 0x04
1593 //wriu 0x10202c 0x00
1594 HAL_DMD_RIU_WriteByte(0x10202d, 0x04);
1595 HAL_DMD_RIU_WriteByte(0x10202C, 0x00);
1596
1597 // 0x11
1598 // [3:0] reg_ckg_dvbs2_inner
1599 // [7:4] reg_ckg_dvbs_outer1x <-- clk_dvbtc_outer2x_c_p
1600 // [7:4] : reg_ckg_dvbs_outer1x
1601 // [4] : disable clock
1602 // [5] : invert clock
1603 // [7:6] : Select clock source
1604 // 00: adc_clk_buf
1605 // 01: clk_dvbtc_outer2x_c_p
1606 // 10: 1'b0
1607 // 11: DFT_CLK
1608 // [10:8] reg_ckg_dvbs_outer2x
1609 // [15:12] reg_ckg_dvbs2_oppro
1610 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b01, 16'h0041);
1611 //wriu 0x102022 0x41
1612 HAL_DMD_RIU_WriteByte(0x102022, 0x41);
1613
1614 // @0x3512
1615 // [4:0] : reg_ckg_dvbs_rs
1616 // [0] : disable clock
1617 // [1] : invert clock
1618 // [4:2]: Select clock source
1619 // 000: mpll_clk216_buf
1620 // 001: 1'b0
1621 // 010: 1'b0
1622 // 011: 1'b0
1623 // [12:8] : reg_ckg_dvbs2_outer //for dvbs2 outer ldpc sram share reset
1624 // [8] : disable clock
1625 // [9] : invert clock
1626 // [12:10] : Select clock source
1627 // 000: mpll_clk288_buf
1628 // 001: mpll_clk216_buf
1629 // 010: 1'b0
1630 // 011: 1'b0
1631 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0400);
1632 //wriu 0x102025 0x04
1633 //wriu 0x102024 0x00
1634 HAL_DMD_RIU_WriteByte(0x102025, 0x04);
1635 HAL_DMD_RIU_WriteByte(0x102024, 0x00);
1636
1637
1638 // @0x3513
1639 // [4:0] : reg_ckg_dvbtm_ts_in
1640 // [0] : disable clock
1641 // [1] : invert clock
1642 // [4:2]: Select clock source
1643 // 000: clk_dvbtc_rs_p
1644 // 001: dvb_clk48_buf
1645 // 010: dvb_clk43_buf
1646 // 011: clk_dvbs_outer1x_pre_mux4
1647 // 100: clk_dvbs2_oppro_pre_mux4
1648 // 101: 1'b0
1649 // 110: 1'b0
1650 // 111: 1'b0
1651 // [11:8] : reg_ckg_dvbs2_diseqc
1652 // [8] : disable clock
1653 // [9] : invert clock
1654 // [11:10] : Select clock source
1655 // 00: xtali_clk24_buf
1656 // 01: xtali_clk12_buf
1657 // 10: xtali_clk6_buf
1658 // 11: xtali_clk3
1659 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h13, 2'b01, 16'h0100);
1660 //wriu 0x102026 0x00
1661 HAL_DMD_RIU_WriteByte(0x102026, 0x00);
1662
1663
1664 // @0x351a
1665 // [12:8] : reg_ckg_dvbtm_ts_in_adc
1666 // [0] : disable clock
1667 // [1] : invert clock
1668 // [4:2]: Select clock source
1669 // 000: clk_dvbtc_rs_p
1670 // 001: dvb_clk48_buf
1671 // 010: dvb_clk43_buf
1672 // 011: clk_dvbs_outer1x_pre_mux4
1673 // 100: clk_dvbs2_oppro_pre_mux4
1674 // 101: 1'b0
1675 // 110: 1'b0
1676 // 111: 1'b0
1677 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b10, 16'h0000);
1678 //wriu 0x102035 0x00
1679 HAL_DMD_RIU_WriteByte(0x102035, 0x00);
1680 #else //add for SRAM clock power saving mechanism
1681 HAL_DMD_RIU_WriteByte(0x103c0e, 0x00); //mux from DMD MCU to HK.
1682 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
1683 // ("==============================================================");
1684 // ("Start TOP CLKGEN initial setting ......");
1685 // ("==============================================================");
1686 // CLK_DMDMCU clock setting
1687 // reg_ckg_dmdmcu@0x0f[4:0]
1688 // [0] : disable clock
1689 // [1] : invert clock
1690 // [4:2]:
1691 // 000:170 MHz(MPLL_DIV_BUF)
1692 // 001:160MHz
1693 // 010:144MHz
1694 // 011:123MHz
1695 // 100:108MHz (Kriti:DVBT2)
1696 // 101:mem_clcok
1697 // 110:mem_clock div 2
1698 // 111:select XTAL
1699 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h0010);
1700 //wriu 0x10331f 0x00
1701 //wriu 0x10331e 0x30
1702 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1703 HAL_DMD_RIU_WriteByte(0x10331e, 0x30);
1704
1705
1706 // set parallel ts clock
1707 // [11] : reg_ckg_demod_test_in_en = 0
1708 // 0: select internal ADC CLK
1709 // 1: select external test-in clock
1710 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1711 // 0: select gated clock
1712 // 1: select free-run clock
1713 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1714 // 0: normal phase to pad
1715 // 1: invert phase to pad
1716 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1717 // 0: select clk_dmplldiv5
1718 // 1: select clk_dmplldiv3
1719 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1720 // Demod TS output clock phase tuning number
1721 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1722 // Demod TS output clock is equal Demod TS internal working clock.
1723 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0513);
1724 //wriu 0x103301 0x05
1725 //wriu 0x103300 0x13
1726 HAL_DMD_RIU_WriteByte(0x103301, 0x14);
1727 HAL_DMD_RIU_WriteByte(0x103300, 0x13);
1728
1729
1730 // set parallel ts clock
1731 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
1732 // Demod TS output clock phase tuning number
1733 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
1734 // Demod TS output clock is equal Demod TS internal working clock.
1735
1736 // enable DVBTC ts clock
1737 // [11:8]: reg_ckg_dvbtc_ts0
1738 // [8] : disable clock
1739 // [9] : invert clock
1740 // [11:10]: Select clock source
1741 // 00:clk_atsc_dvb_div
1742 // 01:62 MHz
1743 // 10:54 MHz
1744 // 11:reserved
1745 // [15:12]: reg_ckg_dvbtc_ts1
1746 // [12] : disable clock
1747 // [13] : invert clock
1748 // [15:14]: Select clock source
1749 // 00:clk_atsc_dvb_div
1750 // 01:62 MHz
1751 // 10:54 MHz
1752 // 11:reserved
1753 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0013);
1754 //wriu 0x103309 0x00
1755 //wriu 0x103308 0x13
1756 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1757 HAL_DMD_RIU_WriteByte(0x103308, 0x13);
1758
1759
1760 // enable dvbc adc clock
1761 // [3:0]: reg_ckg_dvbtc_adc
1762 // [0] : disable clock
1763 // [1] : invert clock
1764 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
1765 // 00: clk_dmdadc
1766 // 01: clk_dmdadc_div2
1767 // 10: clk_dmdadc_div4
1768 // 11: DFT_CLK
1769 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
1770 //wriu 0x103315 0x00
1771 //wriu 0x103314 0x00
1772 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1773 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1774
1775 // Reset TS divider
1776 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0001);
1777 //wriu 0x103302 0x01
1778 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1779
1780 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h01, 2'b01, 16'h0000);
1781 //wriu 0x103302 0x00
1782 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1783
1784 // ("==============================================================");
1785 // ("Start demod CLKGEN setting ......");
1786 // ("==============================================================");
1787 // enable atsc_adcd_sync clock
1788 // [3:0] : reg_ckg_atsc_adcd_sync
1789 // [0] : disable clock
1790 // [1] : invert clock
1791 // [3:2]: Select clock source
1792 // 00: clk_dmdadc_sync
1793 // 01: 1'b0
1794 // 10: 1'b0
1795 // 11: DFT_CLK
1796 // [11:8] : reg_ckg_dmd_dma
1797 // [8] : disable clock
1798 // [9] : invert clock
1799 // [11:10]: Select clock source
1800 // 00: clk_dmdadc
1801 // 01: clk_dmdadc_div2_buf
1802 // 10: 1'b0
1803 // 11: DFT_CLK
1804 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1805 //wriu 0x10200b 0x00
1806 //wriu 0x10200a 0x00
1807 HAL_DMD_RIU_WriteByte(0x10200b, 0x00);
1808 HAL_DMD_RIU_WriteByte(0x10200a, 0x00);
1809
1810
1811 // -------------------- symbol rate det -----------------------//
1812 // [7:4] : reg_ckg_dvbtm_adc0p5x
1813 // [4] : disable clock
1814 // [5] : invert clock
1815 // [7:6]: Select clock source
1816 // 00: adc_clk_div2_buf
1817 // 01: mpll_clk9_buf
1818 // 10: 1'b0
1819 // 11: DFT_CLK
1820 // [11:8] reg_ckg_dvbtm_adc1x_eq1x
1821 // [8] : disable clock
1822 // [9] : invert clock
1823 // [11:10]: Select clock source
1824 // 00: adc_clk_buf
1825 // 01: mpll_clk18_buf
1826 // 10: 1'b0
1827 // 11: DFT_CLK
1828 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1829 //wriu 0x102021 0x00
1830 //wriu 0x102020 0x00
1831 HAL_DMD_RIU_WriteByte(0x102021, 0x00);
1832 HAL_DMD_RIU_WriteByte(0x102020, 0x00);
1833
1834
1835 // [3:0] : reg_ckg_dvbs2_ldpc_inner_sram
1836 // [0] : disable clock
1837 // [1] : invert clock
1838 // [3:2]: Select clock source
1839 // 00: clk_dvbs2_outer_mux8
1840 // 01: adc_clk_buf
1841 // 10: mpll_clk18_buf
1842 // 11: 1'b0
1843 // [7:4] : reg_ckg_dvbs_viterbi_sram
1844 // [4] : disable clock
1845 // [5] : invert clock
1846 // [7:6] : Select clock source
1847 // 00: clk_dvbs2_outer_mux8
1848 // 01: adc_clk_buf
1849 // 10: mpll_clk18_buf
1850 // 11: DFT_CLK
1851 // [12:8] : reg_ckg_dvbs_rs_deint_sram
1852 // [8] : disable clock
1853 // [9] : invert clock
1854 // [12:10] : Select clock source
1855 // 000: clk_dvbs2_outer_mux8
1856 // 001: clk_dvbs_outer1x_pre_mux4
1857 // 010: adc_clk_buf
1858 // 011: mpll_clk18_buf
1859 // 100: clk_dvbtc_outer2x_c_p
1860
1861 // @0x3518
1862 // [4:0]: reg_ckg_dvbs2_outer_rs_adc
1863 // [0] : disable clock
1864 // [1] : invert clock
1865 // [3:2]: Select clock source
1866 // 000: clk_dvbs2_outer_mux8
1867 // 001: clk_dvbs_rs_p
1868 // 010: adc_clk_buf
1869 // 011: mpll_clk18_buf
1870 // 100: clk_dvbtc_outer2x_c_p
1871
1872 // [3:0] reg_ckg_dvbs2_ldpc_inner_sram = 4'h4 (for symbol rate det)
1873 // [7:4] reg_ckg_dvbs_viterbi_sram = 4'h4 (for symbol rate det)
1874 // [12:8] reg_ckg_dvbs_rs_deint_sram = 4'h4 (only for outer)
1875
1876 // 0x18
1877 // [4:0] reg_ckg_dvbs2_outer_rs_adc = 4'h8 (for symbol rate det)
1878 // [11:8] reg_ckg_dvbs2_ldpc_inner_j83b_sram
1879 // [15:12] reg_ckg_dvbs_viterbi_j83b_sram
1880
1881 // 0x19
1882 // [4:0] reg_ckg_dvbs2_outer_rs_adc_j83b
1883 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0844);
1884 //wriu 0x102029 0x08
1885 //wriu 0x102028 0x44
1886 HAL_DMD_RIU_WriteByte(0x102029, 0x08);
1887 HAL_DMD_RIU_WriteByte(0x102028, 0x44);
1888
1889
1890 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h4408);
1891 //wriu 0x102031 0x44
1892 //wriu 0x102030 0x08
1893
1894 HAL_DMD_RIU_WriteByte(0x102031, 0x44);
1895 HAL_DMD_RIU_WriteByte(0x102030, 0x08);
1896
1897 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b01, 16'h0008);
1898 //wriu 0x102032 0x08
1899 HAL_DMD_RIU_WriteByte(0x102032, 0x08);
1900 // -----------------------------------------------------------//
1901
1902 // DVBC
1903 // 0x17
1904 // [3:0] reg_ckg_dvbtc_eq
1905 // [7:4] reg_ckg_dvbtc_eq8x
1906 // [11:8] reg_ckg_dvbtc_innc
1907 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1908 //wriu 0x10202f 0x00
1909 //wriu 0x10202e 0x00
1910 HAL_DMD_RIU_WriteByte(0x10202f, 0x00);
1911 HAL_DMD_RIU_WriteByte(0x10202e, 0x00);
1912
1913 // @0x3516
1914 // [4:0] : reg_ckg_dvbtc_outer2x_c
1915 // [0] : disable clock
1916 // [1] : invert clock
1917 // [4:2]: Select clock source
1918 // 000: clk_dmplldiv10_buf
1919 // 001: clk_dmplldiv10_div2_buf
1920 // 010: clk_dmdadc
1921 // 011: clk_dmdadc_div2_buf
1922 // 100: clk_dmplldiv2_div8_buf
1923 // 101: mpll_clk96_buf
1924 // 110: mpll_clk48_buf
1925 // 110: 1'b0
1926 // [11:8] : reg_ckg_adcd_dvbs_rs
1927 // [8] : disable clock
1928 // [9] : invert clock
1929 // [11:10] : Select clock source
1930 // 00: adc_clk_buf
1931 // 01: clk_dvbs_rs_p
1932 // 10: mpll_clk18_buf
1933 // 11:
1934 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0400);
1935 //wriu 0x10202d 0x04
1936 //wriu 0x10202c 0x00
1937 HAL_DMD_RIU_WriteByte(0x10202d, 0x04);
1938 HAL_DMD_RIU_WriteByte(0x10202c, 0x00);
1939
1940 // 0x11
1941 // [3:0] reg_ckg_dvbs2_inner
1942 // [7:4] reg_ckg_dvbs_outer1x <-- clk_dvbtc_outer2x_c_p
1943 // [7:4] : reg_ckg_dvbs_outer1x
1944 // [4] : disable clock
1945 // [5] : invert clock
1946 // [7:6] : Select clock source
1947 // 00: adc_clk_buf
1948 // 01: clk_dvbtc_outer2x_c_p
1949 // 10: 1'b0
1950 // 11: DFT_CLK
1951 // [10:8] reg_ckg_dvbs_outer2x
1952 // [15:12] reg_ckg_dvbs2_oppro
1953 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b01, 16'h0041);
1954 //wriu 0x102022 0x41
1955 HAL_DMD_RIU_WriteByte(0x102022, 0x41);
1956
1957 // @0x3512
1958 // [4:0] : reg_ckg_dvbs_rs
1959 // [0] : disable clock
1960 // [1] : invert clock
1961 // [4:2]: Select clock source
1962 // 000: mpll_clk216_buf
1963 // 001: 1'b0
1964 // 010: 1'b0
1965 // 011: 1'b0
1966 // [12:8] : reg_ckg_dvbs2_outer //for dvbs2 outer ldpc sram share reset
1967 // [8] : disable clock
1968 // [9] : invert clock
1969 // [12:10] : Select clock source
1970 // 000: mpll_clk288_buf
1971 // 001: mpll_clk216_buf
1972 // 010: 1'b0
1973 // 011: 1'b0
1974 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b11, 16'h0400);
1975 //wriu 0x102025 0x04
1976 //wriu 0x102024 0x00
1977 HAL_DMD_RIU_WriteByte(0x102025, 0x04);
1978 HAL_DMD_RIU_WriteByte(0x102024, 0x00);
1979
1980
1981 // @0x3513
1982 // [4:0] : reg_ckg_dvbtm_ts_in
1983 // [0] : disable clock
1984 // [1] : invert clock
1985 // [4:2]: Select clock source
1986 // 000: clk_dvbtc_rs_p
1987 // 001: dvb_clk48_buf
1988 // 010: dvb_clk43_buf
1989 // 011: clk_dvbs_outer1x_pre_mux4
1990 // 100: clk_dvbs2_oppro_pre_mux4
1991 // 101: 1'b0
1992 // 110: 1'b0
1993 // 111: 1'b0
1994 // [11:8] : reg_ckg_dvbs2_diseqc
1995 // [8] : disable clock
1996 // [9] : invert clock
1997 // [11:10] : Select clock source
1998 // 00: xtali_clk24_buf
1999 // 01: xtali_clk12_buf
2000 // 10: xtali_clk6_buf
2001 // 11: xtali_clk3
2002 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h13, 2'b01, 16'h0100);
2003 //wriu 0x102026 0x00
2004 HAL_DMD_RIU_WriteByte(0x102026, 0x00);
2005
2006
2007 // @0x351a
2008 // [12:8] : reg_ckg_dvbtm_ts_in_adc
2009 // [0] : disable clock
2010 // [1] : invert clock
2011 // [4:2]: Select clock source
2012 // 000: clk_dvbtc_rs_p
2013 // 001: dvb_clk48_buf
2014 // 010: dvb_clk43_buf
2015 // 011: clk_dvbs_outer1x_pre_mux4
2016 // 100: clk_dvbs2_oppro_pre_mux4
2017 // 101: 1'b0
2018 // 110: 1'b0
2019 // 111: 1'b0
2020 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b10, 16'h0000);
2021 // wriu 0x102035 0x00
2022 HAL_DMD_RIU_WriteByte(0x102035, 0x00);
2023
2024 // for DVBC0
2025 // 0 reg_force_allsram_on
2026 // 1 reg_adcdma_sram_sd_en = 1
2027 // 2 reg_dvbs2_inner_sram_sd_en = 1
2028 // 4 reg_dvbs2_outer_sram_sd_en
2029 // 5 reg_dvbs_outer_sram_sd_en
2030 // 6 reg_dvbc_outer_sram_sd_en
2031 // 7 reg_dvbc_inner_0_sram_sd_en
2032 // 8 reg_dvbc_inner_1_sram_sd_en = 1
2033 // 9 reg_dvbt_t2_ts_0_sram_sd_en
2034 // 10 reg_dvbt_t2_ts_1_sram_sd_en = 1
2035 // 11 reg_sram_share_sram_sd_en = 1
2036 //wriu 0x102104 0x06
2037 //wriu 0x102105 0x05
2038 HAL_DMD_RIU_WriteByte(0x102104, 0x06);
2039 HAL_DMD_RIU_WriteByte(0x102105, 0x05);
2040
2041 // for DVBC1
2042 // 0 reg_force_allsram_on
2043 // 1 reg_adcdma_sram_sd_en = 1
2044 // 2 reg_dvbs2_inner_sram_sd_en = 1
2045 // 4 reg_dvbs2_outer_sram_sd_en
2046 // 5 reg_dvbs_outer_sram_sd_en
2047 // 6 reg_dvbc_outer_sram_sd_en
2048 // 7 reg_dvbc_inner_0_sram_sd_en = 1
2049 // 8 reg_dvbc_inner_1_sram_sd_en
2050 // 9 reg_dvbt_t2_ts_0_sram_sd_en = 1
2051 // 10 reg_dvbt_t2_ts_1_sram_sd_en
2052 // 11 reg_sram_share_sram_sd_en = 1
2053 // wriu 0x102104 0x86
2054 // wriu 0x102105 0x02
2055 HAL_DMD_RIU_WriteByte(0x102104, 0x86);
2056 HAL_DMD_RIU_WriteByte(0x102105, 0x02);
2057
2058
2059 // for DVBC0&1
2060 // 0 reg_force_allsram_on
2061 // 1 reg_adcdma_sram_sd_en = 1
2062 // 2 reg_dvbs2_inner_sram_sd_en = 1
2063 // 4 reg_dvbs2_outer_sram_sd_en
2064 // 5 reg_dvbs_outer_sram_sd_en
2065 // 6 reg_dvbc_outer_sram_sd_en
2066 // 7 reg_dvbc_inner_0_sram_sd_en
2067 // 8 reg_dvbc_inner_1_sram_sd_en = 1
2068 // 9 reg_dvbt_t2_ts_0_sram_sd_en
2069 // 10 reg_dvbt_t2_ts_1_sram_sd_en = 1
2070 // 11 reg_sram_share_sram_sd_en = 1
2071 // wriu 0x102104 0x06
2072 // wriu 0x102105 0x08
2073 HAL_DMD_RIU_WriteByte(0x102104, 0x06);
2074 HAL_DMD_RIU_WriteByte(0x102105, 0x00);
2075
2076 #endif
2077
2078
2079 //end of HK init script
2080
2081 //set the SRAM setting to 34(program)+2K(Xdata)
2082 //wriu 0x1634e0 0x21
2083 //wriu 0x1634e1 0x21
2084 HAL_DMD_RIU_WriteByte(0x1634E0,0x21);
2085 HAL_DMD_RIU_WriteByte(0x1634E1,0x21);
2086
2087 //wriu 0x1634e4 0x22
2088 //wriu 0x1634e6 0x01
2089 HAL_DMD_RIU_WriteByte(0x1634E4,0x22);
2090 HAL_DMD_RIU_WriteByte(0x1634E6,0x01);
2091 //end of set the SRAM setting to 34(program)+2K(Xdata)
2092
2093
2094
2095 HAL_DMD_RIU_WriteByte(0x101E39, 0x03); //mux from DMD MCU to HK.
2096 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
2097
2098
2099 //for K6 lite: load code once since the multiple demod share the one MCU
2100 if (INTERN_DVBC_LoadDSPCode() == FALSE)
2101 {
2102 printf("DVB-C Load DSP Code Fail\n");
2103 return ;//FALSE;
2104 }
2105 else
2106 {
2107 DBG_INTERN_DVBC(printf("DVB-C Load DSP Code OK\n"));
2108 }
2109
2110 //for K6 lite: rst demod MCU flow
2111 INTERN_DVBC_SoftStop();
2112 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
2113 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
2114 MsOS_DelayTask(5);
2115 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
2116 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
2117 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
2118 MsOS_DelayTask(5);
2119
2120 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
2121 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
2122
2123 }
2124
2125
2126 //individual initialization
INTERN_DVBC_DMD51_Individual_Initialization(const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)2127 MS_BOOL INTERN_DVBC_DMD51_Individual_Initialization(const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
2128 {
2129 MS_U8 status = true;
2130
2131 DBG_INTERN_DVBC(printf("INTERN_DVBC_DMD51_Individual_Initialization\n"));
2132
2133 #if defined(PWS_ENABLE)
2134 Mapi_PWS_Stop_VDMCU();
2135 #endif
2136
2137 DBG_INTERN_DVBC(printf("INTERN_DVBC Load DSP...\n"));
2138 //MsOS_DelayTask(100);
2139
2140
2141 /* K6 lite move the load code to initClkgen
2142 if (INTERN_DVBC_LoadDSPCode() == FALSE)
2143 {
2144 printf("DVB-C Load DSP Code Fail\n");
2145 return FALSE;
2146 }
2147 else
2148 {
2149 DBG_INTERN_DVBC(printf("DVB-C Load DSP Code OK\n"));
2150 }
2151 */
2152
2153 status &= INTERN_DVBC_Reset();
2154
2155 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
2156
2157
2158
2159 return status;
2160 }
2161
2162
2163
2164 /***********************************************************************************
2165 Subject: Power on initialized function
2166 Function: INTERN_DVBC_Power_On_Initialization
2167 Parmeter:
2168 Return: MS_BOOL
2169 Remark:
2170 ************************************************************************************/
2171
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)2172 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
2173 {
2174 MS_U8 status = true;
2175 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_Power_On_Initialization\n"));
2176
2177 #if defined(PWS_ENABLE)
2178 Mapi_PWS_Stop_VDMCU();
2179 #endif
2180
2181 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
2182 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
2183 //// Firmware download //////////
2184 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC Load DSP...\n"));
2185 //MsOS_DelayTask(100);
2186
2187 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
2188 {
2189 if (INTERN_DVBC_LoadDSPCode() == FALSE)
2190 {
2191 ULOGD("DEMOD","DVB-C Load DSP Code Fail\n");
2192 return FALSE;
2193 }
2194 else
2195 {
2196 DBG_INTERN_DVBC(ULOGD("DEMOD","DVB-C Load DSP Code OK\n"));
2197 }
2198 }
2199
2200 status &= INTERN_DVBC_Reset();
2201
2202 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
2203
2204 return status;
2205 }
2206 /************************************************************************************************
2207 Subject: Driving control
2208 Function: INTERN_DVBC_Driving_Control
2209 Parmeter: bInversionEnable : TRUE For High
2210 Return: void
2211 Remark:
2212 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)2213 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
2214 {
2215 MS_U8 u8Temp;
2216
2217 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
2218
2219 if (bEnable)
2220 {
2221 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
2222 }
2223 else
2224 {
2225 u8Temp = u8Temp & (~0x01);
2226 }
2227
2228 DBG_INTERN_DVBC(ULOGD("DEMOD","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp));
2229 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
2230 }
2231 /************************************************************************************************
2232 Subject: Clk Inversion control
2233 Function: INTERN_DVBC_Clk_Inversion_Control
2234 Parmeter: bInversionEnable : TRUE For Inversion Action
2235 Return: void
2236 Remark:
2237 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)2238 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
2239 {
2240 MS_U8 u8Temp;
2241
2242 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
2243
2244 if (bInversionEnable)
2245 {
2246 u8Temp = u8Temp | 0x02; //bit 9: clk inv
2247 }
2248 else
2249 {
2250 u8Temp = u8Temp & (~0x02);
2251 }
2252
2253 DBG_INTERN_DVBC(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
2254 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
2255 }
2256 /************************************************************************************************
2257 Subject: Transport stream serial/parallel control
2258 Function: INTERN_DVBC_Serial_Control
2259 Parmeter: bEnable : TRUE For serial
2260 Return: MS_BOOL :
2261 Remark:
2262 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)2263 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
2264 {
2265 MS_U8 status = true;
2266 return status;
2267
2268
2269 }
2270
2271 /************************************************************************************************
2272 Subject: TS1 output control
2273 Function: INTERN_DVBC_PAD_TS1_Enable
2274 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2275 Return: void
2276 Remark:
2277 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)2278 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
2279 {
2280 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_TS1_Enable... \n"));
2281
2282 if(flag) // PAD_TS1 Enable TS CLK PAD
2283 {
2284 //ULOGD("DEMOD","=== TS1_Enable ===\n");
2285 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2286 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2287 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2288 }
2289 else // PAD_TS1 Disable TS CLK PAD
2290 {
2291 //ULOGD("DEMOD","=== TS1_Disable ===\n");
2292 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2293 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2294 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2295 }
2296 }
2297
2298 /************************************************************************************************
2299 Subject: channel change config
2300 Function: INTERN_DVBC_Config
2301 Parmeter: BW: bandwidth
2302 Return: MS_BOOL :
2303 Remark:
2304 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2305 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2306 {
2307
2308 MS_U8 status = true;
2309 MS_U8 reg_symrate_l, reg_symrate_h;
2310 //MS_U16 u16Fc = 0;
2311 // force
2312 // u16SymbolRate = 0;
2313 // eQamMode = DMD_DVBC_QAMAUTO;
2314
2315 pu16_symbol_rate_list = pu16_symbol_rate_list;
2316 u8_symbol_rate_list_num = u8_symbol_rate_list_num;
2317
2318 //DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
2319 //DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
2320
2321 if (u8TSClk == 0xFF) u8TSClk=0x13;
2322
2323 /*
2324 switch(u32IFFreq)
2325 {
2326 case 36125:
2327 case 36167:
2328 case 36000:
2329 case 6000:
2330 case 4560:
2331 //u16Fc = DVBC_FS - u32IFFreq;
2332 DBG_INTERN_DVBC(ULOGD("DEMOD","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
2333 break;
2334 case 44000:
2335 default:
2336 ULOGD("DEMOD","IF frequency not supported\n");
2337 status = false;
2338 break;
2339 }
2340 */
2341
2342 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
2343 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
2344
2345 status &= INTERN_DVBC_Reset();
2346
2347 if (eQamMode == DMD_DVBC_QAMAUTO)
2348 {
2349 DBG_INTERN_DVBC(ULOGD("DEMOD","DMD_DVBC_QAMAUTO\n"));
2350 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM+PARA_TBL_LENGTH*hal_demod_swtich_status, 0x01);
2351 // give default value.
2352 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM+PARA_TBL_LENGTH*hal_demod_swtich_status, QAM);
2353 }
2354 else
2355 {
2356 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM+PARA_TBL_LENGTH*hal_demod_swtich_status, 0x00);
2357 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM+PARA_TBL_LENGTH*hal_demod_swtich_status, eQamMode);
2358 }
2359 // auto symbol rate enable/disable
2360 if (u16SymbolRate == 0)
2361 {
2362 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE+PARA_TBL_LENGTH*hal_demod_swtich_status, 0x01);
2363 }
2364 else
2365 {
2366 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE+PARA_TBL_LENGTH*hal_demod_swtich_status, 0x00);
2367 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L+PARA_TBL_LENGTH*hal_demod_swtich_status, reg_symrate_l);
2368 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H+PARA_TBL_LENGTH*hal_demod_swtich_status, reg_symrate_h);
2369 }
2370 // TS mode
2371 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL+PARA_TBL_LENGTH*hal_demod_swtich_status, bSerialTS? 0x01:0x00);
2372
2373 // IQ Swap
2374 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP+PARA_TBL_LENGTH*hal_demod_swtich_status, bSpecInv? 0x01:0x00);
2375
2376 // Fc
2377 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L+PARA_TBL_LENGTH*hal_demod_swtich_status, (abs(DVBC_FS-u32IFFreq))&0xff);
2378 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H+PARA_TBL_LENGTH*hal_demod_swtich_status, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
2379 // Lif
2380 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN+PARA_TBL_LENGTH*hal_demod_swtich_status, (u32IFFreq < 10000) ? 1 : 0);
2381 // Fif
2382 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L+PARA_TBL_LENGTH*hal_demod_swtich_status, (u32IFFreq)&0xff);
2383 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H+PARA_TBL_LENGTH*hal_demod_swtich_status, (u32IFFreq>>8)&0xff);
2384
2385
2386 //// INTERN_DVBC system init: DVB-C //////////
2387 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
2388
2389 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
2390 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
2391
2392 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
2393 INTERN_DVBC_Show_Demod_Version();
2394 #endif
2395
2396 #ifdef UFO_DEMOD_DVBC_SUPPORT_DMD_INT
2397 MsOS_EnableInterrupt(E_INT_FIQ_DMDMCU2HK);
2398 #endif
2399
2400 return status;
2401 }
2402 /************************************************************************************************
2403 Subject: enable hw to lock channel
2404 Function: INTERN_DVBC_Active
2405 Parmeter: bEnable
2406 Return: MS_BOOL
2407 Remark:
2408 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)2409 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
2410 {
2411 MS_U8 status = true;
2412 MS_U8 reg_val=0;
2413 MS_U8 reg_frz = 0, reg_frza = 0;
2414 MS_U16 i;
2415
2416 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_active\n"));
2417
2418 //// INTERN_DVBC Finite State Machine on/off //////////
2419 #if 0 //for k6-lite
2420
2421 #if 0
2422 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2423
2424 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
2425 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
2426 #else
2427 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
2428 #endif
2429
2430 #endif
2431
2432 #if (1)//vesion check here
2433 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_PARAM_VERSION, ®_frz);
2434 DBG_INTERN_DVBC(ULOGD("DEMOD","##########DVBC------>(Driver) = 0x%x #########\n", reg_frz));
2435 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_OP_RFAGC_EN, ®_frza);
2436 DBG_INTERN_DVBC(ULOGD("DEMOD","##########DVBC------>(FW) = 0x%x #########\n", reg_frza));
2437 if (reg_frz < reg_frza)
2438 {
2439 for(i=0;i<=100;i++)
2440 printf("##########--------->Abnormal case, please update demod utopia driver version!!! #########\n");
2441
2442 }
2443 else{
2444 DBG_INTERN_DVBC(ULOGD("DEMOD","##########--------->Normal case! #########\n"));
2445 }
2446 #endif
2447
2448 //modified for k6-lite
2449 HAL_DMD_RIU_WriteByte(0x102300 + (0x0e)*2, 0x01); // the mailbox bank in K6-lite is 0x1023 FSM_EN
2450
2451 MDrv_SYS_DMD_VD_MBX_ReadReg(DEMOD_ACTIVE_REG,®_val );
2452 reg_val|=(0x01<<hal_demod_swtich_status);
2453 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DEMOD_ACTIVE_REG,reg_val);
2454
2455 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
2456 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
2457 return status;
2458 }
2459
2460 #ifdef SUPPORT_ADAPTIVE_TS_CLK
INTERN_DVBC_Adaptive_TS_CLK(MS_U8 demod_index)2461 MS_BOOL INTERN_DVBC_Adaptive_TS_CLK(MS_U8 demod_index)
2462 {
2463 MS_U8 u8_MB_div_num=0x00;
2464 MS_U8 u8_clk_source=0x00;
2465 MS_U8 TS_Clock_Temp;
2466 MS_U8 TS_DIV_NUMBER_Temp;
2467
2468
2469 //===== for multi demods ==================
2470 MS_U32 REG_MB_div_number=0x00;
2471 MS_U32 REG_CLK_bank_TS_div_num=0x00;
2472 //=======================================
2473
2474 switch(demod_index)
2475 {
2476 case 0x00://demod A
2477 REG_MB_div_number=MB_DEMOD_A_TS_DIV;
2478 REG_CLK_bank_TS_div_num=DMD_CLK_GEN+0x00;
2479 break;
2480
2481 case 0x01://demod B
2482 REG_MB_div_number=MB_DEMOD_B_TS_DIV; //checked
2483 REG_CLK_bank_TS_div_num=DMD_CLK_GEN+0x04*2; //checked
2484 break;
2485 default:
2486 break;
2487 }
2488
2489 // u8_MB_div_num=[3'b clock source, 5'b divider number]
2490 u8_MB_div_num = HAL_DMD_RIU_ReadByte(REG_MB_div_number);
2491 ADAPTIVE_CLOCK_PRINT(printf(" The TS clock: %x\n",u8_MB_div_num));
2492 ADAPTIVE_CLOCK_PRINT3(printf("CODE FLOW=> INTERN_DVBC_Adaptive_TS_CLK() \n"));
2493
2494 // read the clock source from FW
2495 u8_clk_source=u8_MB_div_num>>5;
2496
2497 // read the divider number from FW
2498 u8_MB_div_num=u8_MB_div_num&0x1F;
2499 ADAPTIVE_CLOCK_PRINT3(printf("FW divider number: %x \n",u8_MB_div_num));
2500
2501 // the divider number of the original TS clock bank
2502 TS_DIV_NUMBER_Temp=HAL_DMD_RIU_ReadByte(REG_CLK_bank_TS_div_num);
2503 TS_DIV_NUMBER_Temp=(TS_DIV_NUMBER_Temp&0x1F);
2504 ADAPTIVE_CLOCK_PRINT3(printf("register DIV number: %x \n",TS_DIV_NUMBER_Temp));
2505
2506 if (TS_DIV_NUMBER_Temp != u8_MB_div_num )
2507 {
2508 //reg_atsc_dvb_div_reset =1 ; CLKGEN1
2509 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); //clock reset [bit 0]
2510 TS_Clock_Temp=TS_Clock_Temp|0x01;
2511 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
2512
2513 //set TS clock source div 5 (CLK_source=0) //bit4,5,6
2514 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01); //clock reset [bit 0]
2515 TS_Clock_Temp &=0x8F;
2516 TS_Clock_Temp |= (u8_clk_source<<4);
2517 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp);
2518
2519 //set ts clk, REG_BASE[TOP_CKG_DVBTM_TS + 1] = TS_Clock_Set;
2520 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(REG_CLK_bank_TS_div_num);
2521 TS_Clock_Temp=(TS_Clock_Temp&0xE0) |u8_MB_div_num ;
2522 HAL_DMD_RIU_WriteByte(REG_CLK_bank_TS_div_num,TS_Clock_Temp);
2523
2524 //reg_atsc_dvb_div_reset =0
2525 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); //release the reset [bit 0]
2526 TS_Clock_Temp=(TS_Clock_Temp&0xFE);
2527 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp);
2528
2529 // set ts FIFO
2530 // reg_RS_BACKEND
2531 // 0x16 *2 [15:8] reg_dvbt_ts_packet_storage_num=0x15 (extend FIFO)
2532 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE +(BANK_BASE_OFFSET*demod_index)+ (0x16*2+1), 0x15) ;
2533
2534 // enable ts
2535 // for Kyoto setting
2536 MDrv_SYS_DMD_VD_MBX_ReadReg(DVBTM_REG_BASE +(0x20*2*demod_index)+ (0x20*2), &TS_Clock_Temp) ;
2537 TS_Clock_Temp=TS_Clock_Temp|0x04;
2538 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBTM_REG_BASE+(0x20*2*demod_index)+(0x20*2), TS_Clock_Temp) ;
2539
2540
2541 //debug: re-check ts clock
2542 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(REG_CLK_bank_TS_div_num);
2543 TS_Clock_Temp=(TS_Clock_Temp&0x1F) ;
2544
2545 ADAPTIVE_CLOCK_PRINT3(printf("-------------------------------------------------------\n"));
2546 ADAPTIVE_CLOCK_PRINT3(printf("(TS) System report: %x\n",TS_Clock_Temp));
2547
2548 }
2549 return TRUE;
2550 }
2551
2552
INTERN_DVBC_Locked_Task(MS_U8 u8_demod_index)2553 MS_BOOL INTERN_DVBC_Locked_Task(MS_U8 u8_demod_index)
2554 {
2555 INTERN_DVBC_Adaptive_TS_CLK(u8_demod_index);
2556
2557 //extension task
2558 {
2559
2560 }
2561
2562 return TRUE;
2563
2564 }
2565 #endif
2566
2567 #ifdef UFO_DEMOD_DVBC_SUPPORT_DMD_INT
INTERN_DVBC_DEMOD_INTERRUPT_MONITOR(MS_U8 * pu8IntType)2568 MS_BOOL INTERN_DVBC_DEMOD_INTERRUPT_MONITOR(MS_U8* pu8IntType)
2569 {
2570 MS_U8 u8_interrupt_type=0x00;
2571 // for multi-demods architecture
2572 MS_U8 u8_demod_index=0x00;
2573 MS_U8 u8_int_COUNTER_FW_A;
2574 MS_U8 u8_int_COUNTER_FW_B;
2575 MS_U8 u8_int_COUNTER_DRIVER_A;
2576 MS_U8 u8_int_COUNTER_DRIVER_B;
2577
2578 MS_U8 u8_update_A;
2579 MS_U8 u8_update_B;
2580
2581 ADAPTIVE_CLOCK_PRINT3(printf("====================================================== \n"));
2582 ADAPTIVE_CLOCK_PRINT3(printf("Function: INTERN_DVBC_DEMOD_INTERRUPT_MONITOR() \n"));
2583 ADAPTIVE_CLOCK_PRINT3(printf("======================================================\n"));
2584
2585 u8_int_COUNTER_FW_A= HAL_DMD_RIU_ReadByte(MB_DEMOD_A_FW_CNT); //interrupt_counter of demod A in FW
2586 u8_int_COUNTER_FW_B= HAL_DMD_RIU_ReadByte(MB_DEMOD_B_FW_CNT); //interrupt_counter of demod B in FW
2587 u8_int_COUNTER_DRIVER_A= HAL_DMD_RIU_ReadByte(MB_DEMOD_A_DRV_CNT); //interrupt_counter of demod A in driver
2588 u8_int_COUNTER_DRIVER_B= HAL_DMD_RIU_ReadByte(MB_DEMOD_B_DRV_CNT); //interrupt_counter of demod B in driver
2589 ADAPTIVE_CLOCK_PRINT3(printf("Demod counter of A=%d \n",u8_int_COUNTER_FW_A));
2590 ADAPTIVE_CLOCK_PRINT3(printf("Demod counter of B=%d \n",u8_int_COUNTER_FW_B));
2591 ADAPTIVE_CLOCK_PRINT3(printf("Driver counter A=%d \n",u8_int_COUNTER_DRIVER_A));
2592 ADAPTIVE_CLOCK_PRINT3(printf("Driver counter B=%d \n",u8_int_COUNTER_DRIVER_B));
2593
2594 if( (u8_int_COUNTER_DRIVER_A != u8_int_COUNTER_FW_A))
2595 {
2596 u8_update_A=1;
2597 }
2598 else
2599 {
2600 u8_update_A=0;
2601 }
2602
2603 if (u8_int_COUNTER_DRIVER_B != u8_int_COUNTER_FW_B)
2604 {
2605 u8_update_B=1;
2606 }
2607 else
2608 {
2609 u8_update_B=0;
2610 }
2611
2612 if ((u8_update_A==1 && u8_update_B==0) ||
2613 (u8_update_A==1 && u8_update_B==1 && (u8_int_COUNTER_FW_A <= u8_int_COUNTER_FW_B)))
2614 {
2615 u8_demod_index=0x00;
2616 u8_interrupt_type = HAL_DMD_RIU_ReadByte(MB_DEMOD_A_INTERRUPT_CASE) &0x0F;
2617 ADAPTIVE_CLOCK_PRINT3(printf("DEMOD A: u8_interrupt_type=%d \n",u8_interrupt_type));
2618
2619 if (u8_interrupt_type==0x00) //lock case
2620 {
2621 #ifdef SUPPORT_ADAPTIVE_TS_CLK
2622 INTERN_DVBC_Locked_Task(u8_demod_index);
2623 #endif
2624 }
2625
2626 if (u8_interrupt_type==0x01) //unlock case
2627 {
2628
2629 }
2630 u8_int_COUNTER_DRIVER_A=u8_int_COUNTER_FW_A;
2631 HAL_DMD_RIU_WriteByte(MB_DEMOD_A_DRV_CNT,u8_int_COUNTER_DRIVER_A);
2632 }
2633 else if( (u8_update_B==1 && u8_update_A==0) ||
2634 (u8_update_A==1 && u8_update_B==1 && (u8_int_COUNTER_FW_A > u8_int_COUNTER_FW_B)))
2635 {
2636 u8_demod_index=0x01;
2637 u8_interrupt_type = HAL_DMD_RIU_ReadByte(MB_DEMOD_B_INTERRUPT_CASE)&0x0F;
2638 ADAPTIVE_CLOCK_PRINT3(printf("DEMOD B: u8_interrupt_type=%d \n",u8_interrupt_type));
2639
2640 if (u8_interrupt_type==0x00) //lock case
2641 {
2642 #ifdef SUPPORT_ADAPTIVE_TS_CLK
2643 INTERN_DVBC_Locked_Task(u8_demod_index);
2644 #endif
2645 }
2646
2647 if (u8_interrupt_type==0x01) //unlock case
2648 {
2649
2650 }
2651 u8_int_COUNTER_DRIVER_B=u8_int_COUNTER_FW_B;
2652 HAL_DMD_RIU_WriteByte(MB_DEMOD_B_DRV_CNT,u8_int_COUNTER_DRIVER_B);
2653 }
2654 else // case 0 E_DEMOD_UNCHANGED
2655 {
2656
2657 }
2658
2659 *pu8IntType = ((u8_demod_index & 0x0F) << 4) + ((u8_interrupt_type + 1) & 0x0F);
2660
2661 ADAPTIVE_CLOCK_PRINT3(printf("======================================================\n"));
2662 ADAPTIVE_CLOCK_PRINT3(printf("DEMOD: %x \n",u8_demod_index));
2663 ADAPTIVE_CLOCK_PRINT3(printf("interrupt_type: %d (0: unknown, 1: locked, 2: unlocked) \n",(u8_interrupt_type + 1) ));
2664 ADAPTIVE_CLOCK_PRINT3(printf("======================================================\n"));
2665
2666 return TRUE;
2667 }
2668 #endif
2669
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,MS_U32 u32CurrRFPowerDbm,MS_U32 u32NoChannelRFPowerDbm,MS_U32 u32TimeInterval)2670 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2671 {
2672 MS_U16 u16Address = 0;
2673 MS_U8 cData = 0;
2674 MS_U8 cBitMask = 0;
2675 #ifdef SUPPORT_ADAPTIVE_TS_CLK
2676 MS_U8 unlock_indicator=0;
2677 #endif
2678
2679 if (u32CurrRFPowerDbm < 1000)
2680 {
2681 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
2682 {
2683 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE6+BANK_BASE_OFFSET*hal_demod_swtich_status, &cData);
2684 if (cData > 5)
2685 {
2686 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
2687 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
2688 }
2689 else
2690 {
2691 if ((u32CurrRFPowerDbm<u32NoChannelRFPowerDbm) && u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000)
2692 {
2693 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
2694 }
2695 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
2696 {
2697 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
2698 #ifdef MS_DEBUG
2699 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
2700 #endif
2701 return TRUE;
2702 }
2703 }
2704 #ifdef MS_DEBUG
2705 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%d Threshold:%d Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, u32CurrRFPowerDbm, u32NoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
2706 #endif
2707 }
2708 }
2709
2710 {
2711 switch( eType )
2712 {
2713 case DMD_DVBC_GETLOCK_FEC_LOCK:
2714 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE6+BANK_BASE_OFFSET*hal_demod_swtich_status, &cData);
2715 #if (INTERN_DVBC_INTERNAL_DEBUG)
2716 INTERN_DVBC_info();
2717 #endif
2718 DBG_INTERN_DVBC(ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData));
2719
2720 #ifdef SUPPORT_ADAPTIVE_TS_CLK
2721 if (hal_demod_swtich_status==0x00)
2722 MDrv_SYS_DMD_VD_MBX_ReadReg(MB_DEMOD_A_UNLOCK_ONCE, &unlock_indicator);
2723 else
2724 MDrv_SYS_DMD_VD_MBX_ReadReg(MB_DEMOD_B_UNLOCK_ONCE, &unlock_indicator);
2725 #endif
2726
2727
2728 if (cData == 0x0C)
2729 {
2730 #ifdef SUPPORT_ADAPTIVE_TS_CLK
2731 if(g_dvbc_lock == 0 || unlock_indicator==0x01)
2732 #else
2733 if(g_dvbc_lock == 0)
2734 #endif
2735 {
2736 g_dvbc_lock = 1;
2737 DBG_INTERN_DVBC(ULOGD("DEMOD","[T12][DVBC]lock++++\n"));
2738 #ifdef SUPPORT_ADAPTIVE_TS_CLK
2739 ADAPTIVE_CLOCK_PRINT3(printf("===================================================================\n"));
2740 ADAPTIVE_CLOCK_PRINT3(printf("Support adaptive TS CLK in polling mode! \n"));
2741 ADAPTIVE_CLOCK_PRINT3(printf("===================================================================\n"));
2742 INTERN_DVBC_Locked_Task(hal_demod_swtich_status);
2743 if(unlock_indicator==0x01)
2744 {
2745 if (hal_demod_swtich_status==0x00)
2746 MDrv_SYS_DMD_VD_MBX_WriteReg(MB_DEMOD_A_UNLOCK_ONCE, 0x00);
2747 else
2748 MDrv_SYS_DMD_VD_MBX_WriteReg(MB_DEMOD_B_UNLOCK_ONCE, 0x00);
2749
2750 }
2751 #endif
2752 }
2753 return TRUE;
2754 }
2755 else
2756 {
2757 if(g_dvbc_lock == 1)
2758 {
2759 g_dvbc_lock = 0;
2760 DBG_INTERN_DVBC(ULOGD("DEMOD","[T12][DVBC]unlock----\n"));
2761 }
2762 return FALSE;
2763 }
2764 break;
2765
2766 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
2767 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
2768 cBitMask = BIT(1);
2769 break;
2770
2771 case DMD_DVBC_GETLOCK_DCR_LOCK:
2772 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
2773 cBitMask = BIT(0);
2774 break;
2775
2776 case DMD_DVBC_GETLOCK_AGC_LOCK:
2777 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
2778 cBitMask = BIT(0);
2779 break;
2780
2781 case DMD_DVBC_GETLOCK_NO_CHANNEL:
2782 u16Address = TOP_REG_BASE + 0xC3; //no channel,
2783 cBitMask = BIT(2)|BIT(3)|BIT(4);
2784 #ifdef MS_DEBUG
2785 {
2786 MS_U8 reg_frz=0, FSM=0;
2787 MS_U16 u16Timer=0;
2788 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
2789 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
2790 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
2791 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
2792 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
2793 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
2794 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
2795 u16Timer=(u16Timer<<8)+reg_frz;
2796 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
2797 u16Timer=(u16Timer<<8)+reg_frz;
2798 ULOGD("DEMOD","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
2799 }
2800 #endif
2801 break;
2802
2803 case DMD_DVBC_GETLOCK_ATV_DETECT:
2804 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
2805 cBitMask = BIT(1); // check atv
2806 break;
2807
2808 case DMD_DVBC_GETLOCK_TR_LOCK:
2809 #if 0 // 20111108 temporarily solution
2810 u16Address = INNC_REG_BASE + 0x0A*2 + 1; //TR lock indicator,
2811 cBitMask = BIT(4);
2812 break;
2813 #endif
2814 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
2815 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
2816 cBitMask = BIT(4);
2817 break;
2818
2819 default:
2820 return FALSE;
2821 }
2822
2823 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+BANK_BASE_OFFSET*hal_demod_swtich_status, &cData) == FALSE)
2824 return FALSE;
2825
2826 if ((cData & cBitMask) != 0)
2827 {
2828 return TRUE;
2829 }
2830
2831 return FALSE;
2832 }
2833
2834 return FALSE;
2835 }
2836
2837 /****************************************************************************
2838 Subject: To get the Post viterbi BER
2839 Function: INTERN_DVBC_GetPostViterbiBer
2840 Parmeter: Quility
2841 Return: E_RESULT_SUCCESS
2842 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
2843 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
2844 We will not read the Period, and have the "/256/8"
2845 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg)2846 MS_BOOL INTERN_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg)
2847 {
2848 MS_BOOL status = true;
2849 MS_U8 reg = 0, reg_frz = 0;
2850 //MS_U16 BitErrPeriod;
2851 //MS_U32 BitErr;
2852 //MS_U16 PktErr;
2853
2854 /////////// Post-Viterbi BER /////////////
2855
2856 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2857 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x32+BANK_BASE_OFFSET*hal_demod_swtich_status, ®_frz);
2858 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32+BANK_BASE_OFFSET*hal_demod_swtich_status, reg_frz|0x80);
2859
2860 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
2861 // 0x47 [15:8] reg_bit_err_sblprd_15_8
2862 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x31+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2863 *BitErrPeriod_reg = reg;
2864
2865 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x30+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2866 *BitErrPeriod_reg = ((*BitErrPeriod_reg) << 8)|reg;
2867
2868 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
2869 // 0x6b [15:8] reg_bit_err_num_15_8
2870 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
2871 // 0x6d [15:8] reg_bit_err_num_31_24
2872 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2873 *BitErr_reg = reg;
2874
2875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3c+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2876 *BitErr_reg = ((*BitErr_reg) << 8)|reg;
2877
2878 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3b+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2879 *BitErr_reg = ((*BitErr_reg) << 8)|reg;
2880
2881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3a+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2882 *BitErr_reg = ((*BitErr_reg) << 8)|reg;
2883
2884
2885 //INTERN_DVBC_GetPacketErr(&PktErr);
2886
2887 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2888 reg_frz=reg_frz&(~0x80);
2889 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32+BANK_BASE_OFFSET*hal_demod_swtich_status, reg_frz);
2890 /*
2891 if (BitErrPeriod == 0 ) //protect 0
2892 BitErrPeriod = 1;
2893
2894 if (BitErr <=0 )
2895 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
2896 else
2897 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
2898
2899 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
2900 */
2901 return status;
2902 }
2903
2904 /****************************************************************************
2905 Subject: To get the Packet error
2906 Function: INTERN_DVBC_GetPacketErr
2907 Parmeter: pktErr
2908 Return: E_RESULT_SUCCESS
2909 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
2910 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
2911 We will not read the Period, and have the "/256/8"
2912 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)2913 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
2914 {
2915 MS_BOOL status = true;
2916 MS_U8 reg = 0, reg_frz = 0;
2917 MS_U16 PktErr;
2918
2919 // bank 28 0x19 [7] reg_bit_err_num_freeze
2920 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x32+BANK_BASE_OFFSET*hal_demod_swtich_status, ®_frz);
2921 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32+BANK_BASE_OFFSET*hal_demod_swtich_status, reg_frz|0x80);
2922
2923 // bank 28 0x1f [7:0] reg_uncrt_pkt_num_7_0
2924 // 0x1f [15:8] reg_uncrt_pkt_num_15_8
2925 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3f +BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
2926 PktErr = reg;
2927
2928 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE+0x3E +(BANK_BASE_OFFSET*hal_demod_swtich_status), ®);
2929 PktErr = (PktErr << 8)|reg;
2930
2931 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2932 reg_frz=reg_frz&(~0x80);
2933 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE+0x32+BANK_BASE_OFFSET*hal_demod_swtich_status, reg_frz);
2934
2935 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PktErr = %d \n ", (int)PktErr));
2936
2937 *pktErr = PktErr;
2938
2939 return status;
2940 }
2941
2942
2943 /****************************************************************************
2944 Subject: Read the signal to noise ratio (SNR)
2945 Function: INTERN_DVBC_GetSNR
2946 Parmeter: None
2947 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2948 Remark:
2949 *****************************************************************************/
INTERN_DVBC_GetSNR(MS_U16 * snr_reg)2950 MS_BOOL INTERN_DVBC_GetSNR(MS_U16 *snr_reg)
2951 {
2952 MS_BOOL status = true;
2953 MS_U8 u8Data = 0; //reg_frz = 0;
2954 // MS_U8 freeze = 0;
2955 //MS_U16 noisepower = 0;
2956
2957 //if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
2958 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200*10, -200*10, 0) )
2959 {
2960 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2961 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x20);
2962 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x80);
2963 // read vk
2964 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45+BANK_BASE_OFFSET*hal_demod_swtich_status, &u8Data);
2965 *snr_reg = u8Data;
2966 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44+BANK_BASE_OFFSET*hal_demod_swtich_status, &u8Data);
2967 *snr_reg = ((*snr_reg)<<8)|u8Data;
2968 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2969 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x00);
2970 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x00);
2971 //if(noisepower == 0x0000)
2972 // noisepower = 0x0001;
2973 if(*snr_reg == 0x0000)
2974 *snr_reg = 0x0001;
2975 /*
2976 #ifdef MSOS_TYPE_LINUX
2977 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
2978 #else
2979 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
2980 #endif
2981 */
2982 }
2983 else
2984 {
2985 *snr_reg = 0;
2986 }
2987 return status;
2988
2989
2990 }
2991
INTERN_DVBC_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)2992 MS_BOOL INTERN_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
2993 {
2994 MS_BOOL status = true;
2995
2996 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0;
2997 // bank 5 0x24 [15:0] reg_agc_gain2_out
2998 // use only high byte value
2999
3000 // select IF gain to read
3001 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x22, 0x03);
3002 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status +0x05, ®_frz);
3003 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status +0x05, reg_frz | 0x80);
3004 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status+ 0x25, ®_tmp);
3005 *ifagc_reg = reg_tmp;
3006 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + BANK_BASE_OFFSET*hal_demod_swtich_status+0x24, ®_tmp);
3007 *ifagc_reg_lsb = reg_tmp;
3008 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x05, reg_frz);
3009
3010 #ifdef MS_DEBUG
3011 ULOGD("DEMOD","SSI_IFAGC_H = 0x%x 0x%x\n", *ifagc_reg,*ifagc_reg_lsb);
3012 #endif
3013
3014
3015
3016 *ifagc_err = 0;
3017 if(*ifagc_reg == 0xff)
3018 {
3019 // bank 5 0x04 [15] reg_tdp_lat
3020 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x22, 0x00);
3021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x05, ®_frz);
3022 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x05, reg_frz | 0x80);
3023
3024 // bank 5 0x2c [9:0] reg_agc_error
3025 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status+ 0x25, ®_tmp);
3026 // if_agc_err = reg_tmp & 0x03;
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + BANK_BASE_OFFSET*hal_demod_swtich_status+0x24, ®_tmp2);
3028 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
3029
3030 if(reg_tmp&0x2)
3031 {
3032 *ifagc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
3033 }
3034 else
3035 {
3036 *ifagc_err = reg_tmp<<8|reg_tmp2;
3037 }
3038
3039
3040 // release latch
3041 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x05, reg_frz);
3042 }
3043
3044 return status;
3045 }
3046
3047 //waiting mark
3048 #if(0)
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue)3049 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
3050 {
3051 MS_BOOL status = true;
3052 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3053 DMD_DVBC_MODULATION_TYPE Qam_mode;
3054
3055 DBG_INTERN_DVBC_TIME(ULOGD("DEMOD","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi)));
3056
3057 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3058 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3059 /* Actually, it's more reasonable, that signal level depended on cable input power level
3060 * thougth the signal isn't dvb-t signal.
3061 */
3062 // use pointer of IFAGC table to identify
3063 // case 1: RFAGC from SAR, IFAGC controlled by demod
3064 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3065 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3066 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
3067 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3068 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3069 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
3070 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
3071
3072 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
3073
3074 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
3075 {
3076 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
3077 }
3078 else
3079 {
3080 ch_power_db_rel = -100.0f;
3081 }
3082
3083 if(ch_power_db_rel <= -85.0f)
3084 {*strength = 0;}
3085 else if (ch_power_db_rel <= -80.0f)
3086 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
3087 else if (ch_power_db_rel <= -75.0f)
3088 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
3089 else if (ch_power_db_rel <= -70.0f)
3090 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
3091 else if (ch_power_db_rel <= -65.0f)
3092 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
3093 else if (ch_power_db_rel <= -55.0f)
3094 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
3095 else if (ch_power_db_rel <= -45.0f)
3096 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
3097 else
3098 {*strength = 100;}
3099
3100 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
3101 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength));
3102
3103 return status;
3104 }
3105 #endif
3106
3107 /****************************************************************************
3108 Subject: To get the DVT Signal quility
3109 Function: INTERN_DVBC_GetSignalQuality
3110 Parmeter: Quility
3111 Return: E_RESULT_SUCCESS
3112 E_RESULT_FAILURE
3113 Remark: Here we have 4 level range
3114 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3115 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3116 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3117 <4>.4th Range => Quality <10
3118 *****************************************************************************/
3119 //waiting mark
3120 /*
3121 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue)
3122 {
3123
3124 float fber;
3125 float log_ber;
3126 MS_BOOL status = true;
3127 DMD_DVBC_MODULATION_TYPE Qam_mode;
3128 float f_snr;
3129
3130 fRFPowerDbm = fRFPowerDbm;
3131 status &= INTERN_DVBC_GetSNR(&f_snr);
3132 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
3133 {
3134 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
3135 {
3136 DBG_INTERN_DVBC(ULOGD("DEMOD","\nGetPostViterbiBer Fail!"));
3137 return FALSE;
3138 }
3139
3140 // log_ber = log10(fber)
3141 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
3142
3143 DBG_INTERN_DVBC(ULOGD("DEMOD","\nLog(BER) = %f",log_ber));
3144 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
3145 if (Qam_mode == DMD_DVBC_QAM16)
3146 {
3147 if(log_ber <= (-5.5f))
3148 *quality = 100;
3149 else if(log_ber <= (-5.1f))
3150 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
3151 else if(log_ber <= (-4.9f))
3152 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
3153 else if(log_ber <= (-4.5f))
3154 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
3155 else if(log_ber <= (-3.7f))
3156 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
3157 else if(log_ber <= (-3.2f))
3158 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
3159 else if(log_ber <= (-2.9f))
3160 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
3161 else if(log_ber <= (-2.5f))
3162 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
3163 else if(log_ber <= (-2.2f))
3164 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
3165 else if(log_ber <= (-2.0f))
3166 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
3167 else
3168 *quality = 0;
3169 }
3170 else if (Qam_mode == DMD_DVBC_QAM32)
3171 {
3172 if(log_ber <= (-5.0f))
3173 *quality = 100;
3174 else if(log_ber <= (-4.7f))
3175 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
3176 else if(log_ber <= (-4.5f))
3177 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
3178 else if(log_ber <= (-3.8f))
3179 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
3180 else if(log_ber <= (-3.5f))
3181 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
3182 else if(log_ber <= (-3.0f))
3183 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
3184 else if(log_ber <= (-2.7f))
3185 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
3186 else if(log_ber <= (-2.4f))
3187 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
3188 else if(log_ber <= (-2.2f))
3189 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
3190 else if(log_ber <= (-2.0f))
3191 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
3192 else
3193 *quality = 0;
3194 }
3195 else if (Qam_mode == DMD_DVBC_QAM64)
3196 {
3197 if(log_ber <= (-5.4f))
3198 *quality = 100;
3199 else if(log_ber <= (-5.1f))
3200 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
3201 else if(log_ber <= (-4.9f))
3202 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
3203 else if(log_ber <= (-4.3f))
3204 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
3205 else if(log_ber <= (-3.7f))
3206 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
3207 else if(log_ber <= (-3.2f))
3208 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
3209 else if(log_ber <= (-2.9f))
3210 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
3211 else if(log_ber <= (-2.4f))
3212 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
3213 else if(log_ber <= (-2.2f))
3214 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
3215 else if(log_ber <= (-2.05f))
3216 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
3217 else
3218 *quality = 0;
3219 }
3220 else if (Qam_mode == DMD_DVBC_QAM128)
3221 {
3222 if(log_ber <= (-5.1f))
3223 *quality = 100;
3224 else if(log_ber <= (-4.9f))
3225 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
3226 else if(log_ber <= (-4.7f))
3227 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
3228 else if(log_ber <= (-4.1f))
3229 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
3230 else if(log_ber <= (-3.5f))
3231 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
3232 else if(log_ber <= (-3.1f))
3233 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
3234 else if(log_ber <= (-2.7f))
3235 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
3236 else if(log_ber <= (-2.5f))
3237 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
3238 else if(log_ber <= (-2.06f))
3239 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
3240 //else if(log_ber <= (-2.05))
3241 else
3242 {
3243 if (f_snr >= 27.2f)
3244 *quality = 20;
3245 else if (f_snr >= 25.1f)
3246 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
3247 else
3248 *quality = 0;
3249 }
3250 }
3251 else //256QAM
3252 {
3253 if(log_ber <= (-4.8f))
3254 *quality = 100;
3255 else if(log_ber <= (-4.6f))
3256 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
3257 else if(log_ber <= (-4.4f))
3258 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
3259 else if(log_ber <= (-4.0f))
3260 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
3261 else if(log_ber <= (-3.5f))
3262 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
3263 else if(log_ber <= (-3.1f))
3264 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
3265 else if(log_ber <= (-2.7f))
3266 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
3267 else if(log_ber <= (-2.4f))
3268 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
3269 else if(log_ber <= (-2.06f))
3270 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
3271 //else if(log_ber <= (-2.05))
3272 else
3273 {
3274 if (f_snr >= 29.6f)
3275 *quality = 20;
3276 else if (f_snr >= 27.3f)
3277 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
3278 else
3279 *quality = 0;
3280 }
3281 }
3282 }
3283 else
3284 {
3285 *quality = 0;
3286 }
3287
3288 //DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
3289 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","BER = %8.3e\n", fber));
3290 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","Signal Quility = %d\n", *quality));
3291 return TRUE;
3292 }
3293 #endif
3294 */
3295
3296 /****************************************************************************
3297 Subject: To get the Cell ID
3298 Function: INTERN_DVBC_Get_CELL_ID
3299 Parmeter: point to return parameter cell_id
3300
3301 Return: TRUE
3302 FALSE
3303 Remark:
3304 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)3305 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
3306 {
3307 MS_BOOL status = true;
3308 MS_U8 value1 = 0;
3309 MS_U8 value2 = 0;
3310
3311 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3312 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3313
3314 *cell_id = ((MS_U16)value1<<8)|value2;
3315 return status;
3316 }
3317
3318 /****************************************************************************
3319 Subject: To get the DVBC Carrier Freq Offset
3320 Function: INTERN_DVBC_Get_FreqOffset
3321 Parmeter: Frequency offset (in KHz), bandwidth
3322 Return: E_RESULT_SUCCESS
3323 E_RESULT_FAILURE
3324 Remark:
3325 *****************************************************************************/
3326 #if(1)
INTERN_DVBC_Get_FreqOffset(MS_U32 * config_Fc_reg,MS_U32 * Fc_over_Fs_reg,MS_U16 * Cfo_offset_reg,MS_U8 u8BW)3327 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW)
3328 {
3329 MS_U8 reg_frz = 0, reg = 0;
3330 MS_BOOL status = TRUE;
3331
3332 // no use.
3333 u8BW = u8BW;
3334
3335 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_Get_FreqOffset\n"));
3336
3337 // bank 2c 0x3d [0] reg_bit_err_num_freeze
3338 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status, ®_frz);
3339 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status, reg_frz|0x01);
3340
3341 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x75+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3342 *config_Fc_reg = reg;
3343 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x74+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3344 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
3345 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x73+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3346 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
3347 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE2_REG_BASE + 0x72+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3348 *config_Fc_reg = (*config_Fc_reg<<8)|reg;
3349
3350 // bank 2c 0x3d [0] reg_bit_err_num_freeze
3351 reg_frz=reg_frz&(~0x01);
3352 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3d+BANK_BASE_OFFSET*hal_demod_swtich_status, reg_frz);
3353
3354 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3355 *Fc_over_Fs_reg = reg;
3356 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3357 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
3358 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3359 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
3360 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58+BANK_BASE_OFFSET*hal_demod_swtich_status, ®);
3361 *Fc_over_Fs_reg = (*Fc_over_Fs_reg<<8)|reg;
3362
3363 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H+PARA_TBL_LENGTH*hal_demod_swtich_status, ®);
3364 *Cfo_offset_reg = reg;
3365 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L+PARA_TBL_LENGTH*hal_demod_swtich_status, ®);
3366 *Cfo_offset_reg = (*Cfo_offset_reg<<8)|reg;
3367
3368 //waiting mark
3369 /*
3370 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
3371
3372 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
3373
3374 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
3375
3376 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
3377
3378 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
3379 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
3380 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
3381
3382 *pFreqOff = FreqCfo_offset;
3383 */
3384 return status;
3385 }
3386 #endif
3387
3388
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)3389 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
3390 {
3391
3392 bPowerOn = bPowerOn;
3393 }
3394
INTERN_DVBC_Power_Save(void)3395 MS_BOOL INTERN_DVBC_Power_Save(void)
3396 {
3397
3398 return TRUE;
3399 }
3400
3401 /****************************************************************************
3402 Subject: To get the current modulation type at the DVB-C Demod
3403 Function: INTERN_DVBC_GetCurrentModulationType
3404 Parmeter: pointer for return QAM type
3405
3406 Return: TRUE
3407 FALSE
3408 Remark:
3409 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)3410 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
3411 {
3412 MS_U8 u8Data=0;
3413
3414 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_GetCurrentModulationType\n"));
3415
3416
3417 MDrv_SYS_DMD_VD_MBX_ReadReg(0x9cc4, &u8Data);
3418
3419
3420
3421 //ULOGD("DEMOD","@@@@@@ 0x9cc4 pQAMMode = %d \n",u8Data&0x07);
3422
3423 switch(u8Data&0x07)
3424 {
3425 case 0:
3426 *pQAMMode = DMD_DVBC_QAM16;
3427 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=16\n"));
3428 return TRUE;
3429 break;
3430 case 1:
3431 *pQAMMode = DMD_DVBC_QAM32;
3432 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=32\n"));
3433 return TRUE;
3434 break;
3435 case 2:
3436 *pQAMMode = DMD_DVBC_QAM64;
3437 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=64\n"));
3438 return TRUE;
3439 break;
3440 case 3:
3441 *pQAMMode = DMD_DVBC_QAM128;
3442 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=128\n"));
3443 return TRUE;
3444 break;
3445 case 4:
3446 *pQAMMode = DMD_DVBC_QAM256;
3447 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=256\n"));
3448 return TRUE;
3449 break;
3450 default:
3451 *pQAMMode = DMD_DVBC_QAMAUTO;
3452 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]QAM=invalid\n"));
3453 return FALSE;
3454 }
3455 }
3456
3457 /****************************************************************************
3458 Subject: To get the current symbol rate at the DVB-C Demod
3459 Function: INTERN_DVBC_GetCurrentSymbolRate
3460 Parmeter: pointer pData for return Symbolrate
3461
3462 Return: TRUE
3463 FALSE
3464 Remark:
3465 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)3466 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
3467 {
3468 MS_U8 tmp = 0;
3469 MS_U16 u16SymbolRateTmp = 0;
3470
3471 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_GetCurrentSymbolRate\n"));
3472
3473
3474 // intp
3475 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d2+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3476 u16SymbolRateTmp = tmp;
3477 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20d1+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3478 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
3479
3480 if (abs(u16SymbolRateTmp-6900)<2)
3481 {
3482 u16SymbolRateTmp=6900;
3483 }
3484
3485 if (abs(u16SymbolRateTmp-6875)<2)
3486 {
3487 u16SymbolRateTmp=6875;
3488 }
3489
3490 *u16SymbolRate = u16SymbolRateTmp;
3491
3492 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]SR=%d\n",*u16SymbolRate));
3493
3494
3495 return TRUE;
3496 }
3497
3498
3499 /****************************************************************************
3500 Subject: To get the current symbol rate offset at the DVB-C Demod
3501 Function: INTERN_DVBC_GetCurrentSymbolRate
3502 Parmeter: pointer pData for return Symbolrate offset
3503
3504 Return: TRUE
3505 FALSE
3506 Remark:
3507 *****************************************************************************/
3508 //waiting mark
3509 /*
3510 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
3511 {
3512 MS_U8 u8Data = 0, reg_frz = 0;
3513 MS_U32 u32Data = 0;
3514 // MS_S32 s32Data = 0;
3515 MS_BOOL status = TRUE;
3516 MS_U16 u16SymbolRate = 0;
3517 float f_symb_offset = 0.0f;
3518
3519
3520
3521 // bank 26 0x03 [7] reg_bit_err_num_freeze
3522 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x03, ®_frz);
3523 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz|0x80);
3524
3525 // sel, SFO debug output.
3526 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2F, &u8Data);
3527 u32Data = u8Data;
3528 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2E, &u8Data);
3529 u32Data = (u32Data<<8)|u8Data;
3530 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2D, &u8Data);
3531 u32Data = (u32Data<<8)|u8Data;
3532 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x2C, &u8Data);
3533 u32Data = (u32Data<<8)|u8Data;
3534
3535 // bank 26 0x03 [7] reg_bit_err_num_freeze
3536 reg_frz=reg_frz&(~0x80);
3537 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x03, reg_frz);
3538 // s32Data = (MS_S32)(u32Data<<8);
3539
3540 ULOGD("DEMOD","[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
3541
3542 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
3543
3544 // sfo = Reg*2^(-37)*FB/FS*1000000 (2^-28 * 1000000 = 0.003725)
3545 // f_symb_offset = (float)((MS_S32)u32Data) * (1000000.0f/powf(2.0f, 37.0f)) * (float)u16SymbolRate/(float)DVBC_FS;
3546 f_symb_offset = (float)((MS_S32)u32Data) * (0.000007276f) * (float)u16SymbolRate/(float)DVBC_FS;
3547
3548 *pData = (MS_U16)(f_symb_offset + 0.5f);
3549
3550 DBG_INTERN_DVBC_LOCK(ULOGD("DEMOD","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
3551
3552 return status;
3553 }
3554 #endif
3555 */
3556
3557
3558 //not related to demod No. No need to add the bank offset
INTERN_DVBC_Version(MS_U16 * ver)3559 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
3560 {
3561
3562 MS_U8 status = true;
3563 MS_U8 tmp = 0;
3564 MS_U16 u16_INTERN_DVBC_Version;
3565
3566 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
3567 u16_INTERN_DVBC_Version = tmp;
3568 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
3569 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
3570 *ver = u16_INTERN_DVBC_Version;
3571
3572 return status;
3573 }
3574
3575
INTERN_DVBC_Show_Demod_Version(void)3576 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
3577 {
3578
3579 MS_BOOL status = true;
3580 MS_U16 u16_INTERN_DVBC_Version;
3581
3582 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
3583
3584 ULOGD("DEMOD","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
3585
3586 return status;
3587 }
3588
3589 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO //add for backend reading AGC related info
INTERN_DVBC_AGC_Info(MS_U8 u8dbg_mode,MS_U16 * pu16Data)3590 MS_BOOL INTERN_DVBC_AGC_Info(MS_U8 u8dbg_mode, MS_U16* pu16Data)
3591 {
3592 MS_BOOL status = true;
3593 MS_U8 u8Data;
3594 MS_U16 u16Data;
3595
3596 if(u8dbg_mode>10 ||((u8dbg_mode!=0x03)&&(u8dbg_mode!=0x05)&&(u8dbg_mode!=0x0a)))
3597 {
3598 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_AGC_Info parameter Error!!! \n"));
3599 *pu16Data=0xff;
3600 return false;
3601 }
3602
3603 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2122,&u8Data);
3604 u8Data = (u8Data & 0xf0) | u8dbg_mode;
3605 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(0x2122,u8Data);
3606
3607 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2105,&u8Data);
3608 u8Data = u8Data | 0x80;
3609 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(0x2105,u8Data);
3610
3611 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2125,&u8Data);
3612 u16Data = u8Data;
3613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2124,&u8Data);
3614 u16Data = (u16Data<<8) | u8Data;
3615
3616 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2105,&u8Data);
3617 u8Data = u8Data & 0x7f;
3618 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(0x2105,u8Data);
3619
3620 *pu16Data=u16Data;
3621
3622 if (status==FALSE)
3623 {
3624 DBG_INTERN_DVBC(ULOGD("DEMOD","INTERN_DVBC_AGC_Info Error!!! \n"));
3625 }
3626
3627 return status;
3628 }
3629 #endif
3630
3631 #if (INTERN_DVBC_INTERNAL_DEBUG)
3632
INTERN_DVBC_Show_AGC_Info(void)3633 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
3634 {
3635 MS_U8 tmp = 0;
3636 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3637 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3638 MS_U16 if_agc_err = 0;
3639 MS_BOOL status = TRUE;
3640
3641 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
3642 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
3643 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
3644 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
3645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
3646 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
3647
3648
3649 // select IF gain to read
3650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
3651 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
3652
3653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
3654 if_agc_gain = tmp;
3655 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
3656 if_agc_gain = (if_agc_gain<<8)|tmp;
3657
3658
3659 // select d1 gain to read.
3660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
3661 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
3662
3663 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
3664 d1_gain = tmp;
3665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
3666 d1_gain = (d1_gain<<8)|tmp;
3667
3668 // select d2 gain to read.
3669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
3670 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
3671
3672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
3673 d2_gain = tmp;
3674 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
3675 d2_gain = (d2_gain<<8)|tmp;
3676
3677 // select IF gain err to read
3678 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
3679 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
3680
3681 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
3682 if_agc_err = tmp;
3683 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
3684 if_agc_err = (if_agc_err<<8)|tmp;
3685
3686 ULOGD("DEMOD","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3687 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3688
3689 ULOGD("DEMOD","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3690
3691 return status;
3692 }
3693
INTERN_DVBC_info(void)3694 void INTERN_DVBC_info(void)
3695 {
3696 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
3697 MS_U8 qam,tmp = 0;
3698 MS_U8 fft_u8 = 0;
3699 MS_U16 fft_u16bw = 0;
3700 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
3701 //float f_snr = 0,f_freq = 0;
3702 //DMD_DVBC_MODULATION_TYPE QAMMode = 0;
3703 MS_U16 f_start = 0,f_end = 0;
3704 MS_U8 s0_count = 0;
3705 MS_U8 sc4 = 0,sc3 = 0;
3706 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
3707 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
3708 MS_U16 count = 0;
3709 MS_U16 fb_i_1,fb_q_1;
3710 MS_U8 e0,e1,e2,e3;
3711 MS_S16 reg_freq;
3712 //float freq,mag;
3713
3714
3715
3716 INTERN_DVBC_Version(&version);
3717
3718 // fb_fs
3719 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3720 fb_fs = tmp;
3721 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3722 fb_fs = (fb_fs<<8)|tmp;
3723 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3724 fb_fs = (fb_fs<<8)|tmp;
3725 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3726 fb_fs = (fb_fs<<8)|tmp;
3727 // fc_fs
3728 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3729 fc_fs = tmp;
3730 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3731 fc_fs = (fc_fs<<8)|tmp;
3732 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3733 fc_fs = (fc_fs<<8)|tmp;
3734 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3735 fc_fs = (fc_fs<<8)|tmp;
3736 // crv
3737 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3738 crv = tmp;
3739 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3740 crv = (crv<<8)|tmp;
3741 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3742 crv = (crv<<8)|tmp;
3743 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3744 crv = (crv<<8)|tmp;
3745 // tr_error
3746 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3747 tr_error = tmp;
3748 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3749 tr_error = (tr_error<<8)|tmp;
3750 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3751 tr_error = (tr_error<<8)|tmp;
3752
3753 // intp
3754 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3755 intp = tmp;
3756 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3757 intp = (intp<<8)|tmp;
3758 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3759 intp = (intp<<8)|tmp;
3760 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3761 intp = (intp<<8)|tmp;
3762
3763 //waiting mark
3764 // fft info
3765 // intp
3766 /*
3767 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
3768 fft_u16bw = tmp;
3769 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
3770 fft_u16bw = (fft_u16bw<<8)|tmp;
3771 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
3772 fft_u8 = tmp;
3773 */
3774
3775 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3776 qam = tmp;
3777
3778 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3779 f_start = tmp;
3780 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3781 f_start = (f_start<<8)|tmp;
3782 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3783 f_end = tmp;
3784 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3785 f_end = (f_end<<8)|tmp;
3786 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3787 s0_count = tmp;
3788
3789 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3+BANK_BASE_OFFSET*hal_demod_swtich_status, &sc3);
3790 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4+BANK_BASE_OFFSET*hal_demod_swtich_status, &sc4);
3791
3792 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04+BANK_BASE_OFFSET*hal_demod_swtich_status, &kp0);
3793 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05+BANK_BASE_OFFSET*hal_demod_swtich_status, &kp1);
3794 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06+BANK_BASE_OFFSET*hal_demod_swtich_status, &kp2);
3795 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07+BANK_BASE_OFFSET*hal_demod_swtich_status, &kp3);
3796 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08+BANK_BASE_OFFSET*hal_demod_swtich_status, &kp4);
3797 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B+BANK_BASE_OFFSET*hal_demod_swtich_status, &fmax);
3798 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49+BANK_BASE_OFFSET*hal_demod_swtich_status, &era_th);
3799
3800
3801 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x00);
3802
3803 count = 0x400;
3804 while(count--);
3805
3806 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3807 aci_e0 = tmp&0x0f;
3808 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3809 aci_e0 = aci_e0<<8|tmp;
3810
3811 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x01);
3812
3813 count = 0x400;
3814 while(count--);
3815
3816
3817 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3818 aci_e1 = tmp&0x0f;
3819 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3820 aci_e1 = aci_e1<<8|tmp;
3821
3822 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x02);
3823
3824 count = 0x400;
3825 while(count--);
3826
3827 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3828 aci_e2 = tmp&0x0f;
3829 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3830 aci_e2 = aci_e2<<8|tmp;
3831
3832 // read aci coef
3833 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81+BANK_BASE_OFFSET*hal_demod_swtich_status, 0x03);
3834
3835 count = 0x400;
3836 while(count--);
3837
3838 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3839 aci_e3 = tmp&0x0f;
3840 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84+BANK_BASE_OFFSET*hal_demod_swtich_status, &tmp);
3841 aci_e3 = aci_e3<<8|tmp;
3842
3843 //waiting mark
3844 /*
3845 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
3846 fb_i_1 = tmp;
3847 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
3848 fb_i_1 = fb_i_1<<8|tmp;
3849
3850 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
3851 fb_q_1 = tmp;
3852 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
3853 fb_q_1 = fb_q_1<<8|tmp;
3854 */
3855
3856 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0+BANK_BASE_OFFSET*hal_demod_swtich_status, &e0);
3857 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1+BANK_BASE_OFFSET*hal_demod_swtich_status, &e1);
3858 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2+BANK_BASE_OFFSET*hal_demod_swtich_status, &e2);
3859 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3+BANK_BASE_OFFSET*hal_demod_swtich_status, &e3);
3860
3861 //reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
3862 //freq = (float)reg_freq*45473.0/65536.0;
3863 //mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
3864
3865
3866 INTERN_DVBC_GetPacketErr(&packetErr);
3867 //INTERN_DVBC_GetSNR(&f_snr);
3868 INTERN_DVBC_Show_AGC_Info();
3869 //INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
3870 //INTERN_DVBC_Get_FreqOffset(&f_freq,8); //GetStatus
3871 //INTERN_DVBC_GetCurrentSymbolRate(&symb_rate); //GetStatus
3872 //INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
3873 //INTERN_DVBC_GetCurrentModulationType(&QAMMode); //GetStatus
3874 /*
3875 ULOGD("DEMOD","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
3876 //ULOGD("DEMOD","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
3877 ULOGD("DEMOD","[MStar_2][2]0x%lx\n",intp);
3878 ULOGD("DEMOD","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
3879 ULOGD("DEMOD","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
3880 ULOGD("DEMOD","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
3881 //ULOGD("DEMOD","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
3882 ULOGD("DEMOD","[Mstar_6][3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
3883 */
3884 return;
3885
3886 }
3887
3888
3889 #endif
3890
3891 /***********************************************************************************
3892 Subject: read register
3893 Function: MDrv_1210_IIC_Bypass_Mode
3894 Parmeter:
3895 Return:
3896 Remark:
3897 ************************************************************************************/
3898 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
3899 //{
3900 // UNUSED(enable);
3901 // if (enable)
3902 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
3903 // else
3904 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
3905 //}
3906