1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #include <stdio.h>
101 #include <math.h>
102
103 #include "drvDMD_DTMB.h"
104
105 #include "MsTypes.h"
106 #if DMD_DTMB_UTOPIA_EN || DMD_DTMB_UTOPIA2_EN
107 #include "drvDMD_common.h"
108 #include "halDMD_INTERN_common.h"
109 #endif
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114
115 #define DMD_DTMB_CHIP_NIKON 0x00
116 #define DMD_DTMB_CHIP_NASA 0x01
117 #define DMD_DTMB_CHIP_MADISON 0x02
118 #define DMD_DTMB_CHIP_MONACO 0x03
119 #define DMD_DTMB_CHIP_MUJI 0x04
120 #define DMD_DTMB_CHIP_MONET 0x05
121 #define DMD_DTMB_CHIP_MANHATTAN 0x06
122 #define DMD_DTMB_CHIP_MESSI 0x07
123 #define DMD_DTMB_CHIP_MAINZ 0x08
124
125 #if defined(nikon)
126 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
127 #elif defined(nasa)
128 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
129 #elif defined(madison)
130 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
131 #elif defined(monaco)
132 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
133 #elif defined(muji)
134 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
135 #elif defined(monet)
136 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
137 #elif defined(manhattan)
138 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
139 #elif defined(messi)
140 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
141 #elif defined(mainz)
142 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MAINZ
143 #else
144 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
145 #endif
146
147 //-------------------------------------------------------------------------------------------------
148 // Local Defines
149 //-------------------------------------------------------------------------------------------------
150
151 #define HAL_INTERN_DTMB_DBINFO(y) //y
152
153 //#define MBRegBase 0x112600
154 //#define DMDMcuBase 0x103480
155
156 #define DTMB_REG_BASE 0x2600
157
158 #define DTMB_ACI_COEF_SIZE 112
159
160 //-------------------------------------------------------------------------------------------------
161 // Local Variables
162 //-------------------------------------------------------------------------------------------------
163
164 const MS_U8 INTERN_DTMB_table[] = {
165 #include "DMD_INTERN_DTMB.dat"
166 };
167
168 const MS_U8 INTERN_DTMB_6M_table[] = {
169 #include "DMD_INTERN_DTMB_6M.dat"
170 };
171
172 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
173 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
174 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
175 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
176 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
177
178 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
179 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
180 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
181 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
182 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
183
184 //-------------------------------------------------------------------------------------------------
185 // Global Variables
186 //-------------------------------------------------------------------------------------------------
187
188 extern MS_U8 u8DMD_DTMB_DMD_ID;
189
190 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
191
192 //-------------------------------------------------------------------------------------------------
193 // Local Functions
194 //-------------------------------------------------------------------------------------------------
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)195 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
196 {
197 MS_U8 u8CheckCount;
198 MS_U8 u8CheckFlag;
199
200 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
201 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
202 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
203 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
204
205 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
206 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
207
208 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
209 {
210 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
211 if ((u8CheckFlag&0x01)==0)
212 break;
213 MsOS_DelayTask(1);
214 }
215
216 if (u8CheckFlag&0x01)
217 {
218 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
219 return FALSE;
220 }
221
222 return TRUE;
223 }
224
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)225 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
226 {
227 MS_U8 u8CheckCount;
228 MS_U8 u8CheckFlag;
229
230 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
231 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
232 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
233
234 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
235 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
236
237 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
238 {
239 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
240 if ((u8CheckFlag&0x02)==0)
241 {
242 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
243 break;
244 }
245 MsOS_DelayTask(1);
246 }
247
248 if (u8CheckFlag&0x02)
249 {
250 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
251 return FALSE;
252 }
253
254 return TRUE;
255 }
256
257 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)258 static void _HAL_INTERN_DTMB_InitClk(void)
259 {
260 MS_U8 u8Val = 0;
261
262 printf("--------------DMD_DTMB_CHIP_NIKON--------------\n");
263
264 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
265 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
266
267 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
268 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
269 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
270 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
271 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
272 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
273 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
274 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
275
276 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
277 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
278 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
279 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
280 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
281 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
282 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
283 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
284 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
285 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
286 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
287 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
288 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
289 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
290 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
291 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
292 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
293 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
294 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
295 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
296 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
297 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
298 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
299 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
300 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
301 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
302 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
303 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
304 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
305
306 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
307 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
308 }
309 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)310 static void _HAL_INTERN_DTMB_InitClk(void)
311 {
312 MS_U8 u8Val = 0;
313
314 printf("--------------DMD_DTMB_CHIP_NASA--------------\n");
315
316 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
317 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
318
319 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
320 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
321 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
322 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
323 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
324 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
325 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
326 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
327
328 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
329 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
330 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
331 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
332 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
333 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
334 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
335 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
336 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
337 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
338 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
339 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
340 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
341 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
342 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
343 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
344 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
345 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
346 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
347 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
348 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
349 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
350 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
351 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
352 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
353 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
354 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
355 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
356 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
357
358 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
359 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
360 }
361 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)362 static void _HAL_INTERN_DTMB_InitClk(void)
363 {
364 MS_U8 u8Val = 0;
365
366 printf("--------------DMD_DTMB_CHIP_MADISON--------------\n");
367
368 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
369 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
370
371 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
372 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
373 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
374 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
375 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
376 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
377 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
378 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
379
380 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
381 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
382
383 //carl
384 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
385 HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
386 HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
387 HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
388
389 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
390 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
391 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
392 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
393 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
394 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
395 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
396 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
397
398 //carl
399 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
400 HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
401
402 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
403 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
404 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
405 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
406 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
407 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
408 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
409 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
410 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
411 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
412 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
413 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
414 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
415 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
416 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
417 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
418 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
419 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
420 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
421
422 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
423 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
424 }
425 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)426 static void _HAL_INTERN_DTMB_InitClk(void)
427 {
428 MS_U8 u8Val = 0;
429
430 printf("--------------DMD_DTMB_CHIP_MONACO--------------\n");
431
432 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
433 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
434
435 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
436 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
437
438 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
439 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
440
441 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
442 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
443 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
444 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
445
446 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
447 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
448
449 //carl
450 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
451 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
452
453 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
454 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
455 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
456 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
457 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
458 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
459 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
460 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
461 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
462 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
463
464 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
465 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
466 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
467 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
468
469 //carl
470 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
471 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
472 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
473 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
474
475 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
476 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
477
478 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
479
480 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
481 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
482 }
483 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)484 static void _HAL_INTERN_DTMB_InitClk(void)
485 {
486 MS_U8 u8Val = 0;
487
488 printf("--------------DMD_DTMB_CHIP_MUJI--------------\n");
489
490 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
491 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
492
493 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
494 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
495
496 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
497 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
498
499 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
500 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
501 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
502 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
503 HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
504 HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
505
506 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
507 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
508
509 //carl
510 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
511 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
512
513 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
514 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
515 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
516 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
517 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
518 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
519 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
520 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
521 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
522 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
523
524 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
525 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
526 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
527 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
528
529 //carl
530 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
531 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
532 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
533 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
534
535 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
536 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
537
538 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
539
540 HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
541 HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
542
543 HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
544 HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
545
546 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
547 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
548 }
549 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)550 static void _HAL_INTERN_DTMB_InitClk(void)
551 {
552 MS_U8 u8Val = 0;
553
554 printf("--------------DMD_DTMB_CHIP_MONET--------------\n");
555
556 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
557 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
558
559 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
560 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
561
562 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
563 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
564
565 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
566 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
567 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
568 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
569 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
570 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
571
572 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
573 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
574
575 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
576 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
577
578 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
579 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
580 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
581 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
582
583 HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
584 HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
585
586 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
587 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
588 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
589 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
590 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
591 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
592
593 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
594 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
595 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
596 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
597
598 //carl
599 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
600 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
601
602 HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
603 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
604
605
606 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
607 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
608
609 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
610 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
611
612 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
613 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
614
615 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
616 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
617
618 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
619 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
620
621 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
622 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
623 }
624 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)625 static void _HAL_INTERN_DTMB_InitClk(void)
626 {
627 MS_U8 u8Val = 0;
628
629 printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n");
630
631 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
632 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
633
634 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
635 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
636
637 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
638 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
639
640 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
641 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
642 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
643 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
644 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
645 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
646
647 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
648 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
649
650 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
651 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
652
653 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
654 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
655 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
656 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
657
658 // HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
659 // HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
660
661 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
662 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
663 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
664 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
665 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
666 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
667
668 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
669 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
670 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
671 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
672
673 //carl
674 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
675 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
676
677 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
678 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
679
680
681 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
682 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
683
684 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
685 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
686
687 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
688 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
689
690 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
691 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
692
693 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
694 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
695
696 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
697 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
698
699 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
700 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
701
702 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
703 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
704
705 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
706 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
707
708 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
709 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
710
711
712 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
713 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
714
715 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
716 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
717 }
718 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MAINZ)
_HAL_INTERN_DTMB_InitClk(void)719 static void _HAL_INTERN_DTMB_InitClk(void)
720 {
721 MS_U8 u8Val = 0;
722
723 printf("--------------DMD_DTMB_CHIP_MESSI/MAINZ--------------\n");
724
725 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
726 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
727
728 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
729 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
730
731 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
732 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
733
734 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
735 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
736 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
737 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
738 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
739 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
740
741 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
742 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
743
744 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
745 //HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
746 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
747
748 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
749 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
750 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
751 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
752
753 // HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
754 // HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
755
756 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
757 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
758 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
759 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
760 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
761 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
762
763 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
764 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
765 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
766 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
767
768 //carl
769 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
770 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
771
772 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
773 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
774
775
776 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
777 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
778
779 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
780 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
781
782 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
783 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
784
785 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
786 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
787
788 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
789 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
790
791 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
792 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
793
794 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
795 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
796
797 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
798 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
799
800 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
801 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
802
803 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
804 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
805
806
807 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
808 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
809
810 u8Val = HAL_DMD_RIU_ReadByte(0x112758); //Get efuse value
811 HAL_DMD_RIU_WriteByte(0x11261A, u8Val); //Write efuse value to mailbox reg for fw
812
813 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
814 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
815 }
816 #else
_HAL_INTERN_DTMB_InitClk(void)817 static void _HAL_INTERN_DTMB_InitClk(void)
818 {
819 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
820 }
821 #endif
822
_HAL_INTERN_DTMB_Ready(void)823 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
824 {
825 MS_U8 udata = 0x00;
826
827 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
828
829 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
830 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
831
832 MsOS_DelayTask(1);
833
834 udata = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
835
836 if (udata) return FALSE;
837
838 return TRUE;
839 }
840
_HAL_INTERN_DTMB_Download(void)841 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
842 {
843 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
844
845 MS_U8 udata = 0x00;
846 MS_U16 i = 0;
847 MS_U16 fail_cnt = 0;
848 MS_U8 u8TmpData;
849 MS_U16 u16AddressOffset;
850 const MS_U8 *DTMB_table;
851 MS_U16 u16Lib_size;
852
853 if (pRes->sDMD_DTMB_PriData.bDownloaded)
854 {
855 if (_HAL_INTERN_DTMB_Ready())
856 {
857 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
858 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
859 MsOS_DelayTask(20);
860 return TRUE;
861 }
862 }
863
864 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
865 {
866 DTMB_table = &INTERN_DTMB_6M_table[0];
867 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
868 }
869 else
870 {
871 DTMB_table = &INTERN_DTMB_table[0];
872 u16Lib_size = sizeof(INTERN_DTMB_table);
873 }
874
875 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
876 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
877
878 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
879
880 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
881 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
882 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
883 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
884
885 //// Load code thru VDMCU_IF ////
886 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
887
888 for (i = 0; i < u16Lib_size; i++)
889 {
890 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
891 }
892
893 //// Content verification ////
894 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
895
896 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
897 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
898
899 for (i = 0; i < u16Lib_size; i++)
900 {
901 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
902
903 if (udata != DTMB_table[i])
904 {
905 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
906 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
907 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
908
909 if (fail_cnt++ > 10)
910 {
911 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
912 return FALSE;
913 }
914 }
915 }
916
917 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
918
919 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
920 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
921
922 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
923 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
924 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
925 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
926 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
927 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
928 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
929 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
930 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
931 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
932 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
933 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
934 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
935 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
936 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
937 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
938 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
939 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
940 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
941 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
942
943 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
944 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
945
946 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
947
948 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
949 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
950
951 pRes->sDMD_DTMB_PriData.bDownloaded = true;
952
953 MsOS_DelayTask(20);
954
955 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
956
957 return TRUE;
958 }
959
_HAL_INTERN_DTMB_FWVERSION(void)960 static void _HAL_INTERN_DTMB_FWVERSION(void)
961 {
962 MS_U8 data1,data2,data3;
963
964 _MBX_ReadReg(0x20C4, &data1);
965 _MBX_ReadReg(0x20C5, &data2);
966 _MBX_ReadReg(0x20C6, &data3);
967
968 HAL_INTERN_DTMB_DBINFO(printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
969 }
970
_HAL_INTERN_DTMB_Exit(void)971 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
972 {
973 MS_U8 u8CheckCount = 0;
974
975 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
976
977 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
978 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
979
980 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
981 {
982 MsOS_DelayTaskUs(10);
983
984 if (u8CheckCount++ == 0xFF)
985 {
986 printf(">> DTMB Exit Fail!\n");
987 return FALSE;
988 }
989 }
990
991 printf(">> DTMB Exit Ok!\n");
992
993 return TRUE;
994 }
995
_HAL_INTERN_DTMB_SoftReset(void)996 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
997 {
998 MS_U8 u8Data = 0;
999
1000 //Reset FSM
1001 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1002
1003 while (u8Data!=0x02)
1004 {
1005 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1006 }
1007
1008 return TRUE;
1009 }
1010
_HAL_INTERN_DTMB_SetACICoef(void)1011 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1012 {
1013 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1014
1015 MS_U8 *ACI_table;
1016 MS_U8 i;
1017 MS_U16 u16AddressOffset;
1018
1019 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1020 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1021 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1022 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1023 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1024 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1025 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1026 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1027 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1028
1029 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1030 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1031
1032 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1033
1034 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1035 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1036 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1037 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1038
1039 //SET SR value
1040 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1041 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1042 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1043 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1044
1045 //set ACI coefficient
1046 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1047 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1048 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1049 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1050 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1051 {
1052 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1053 }
1054
1055 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1056 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1057
1058 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1059
1060 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1061 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1062
1063 MsOS_DelayTask(20);
1064
1065 return TRUE;
1066 }
1067
_HAL_INTERN_DTMB_SetDtmbMode(void)1068 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1069 {
1070 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1071 return _MBX_WriteReg(0x20C0, 0x04);
1072 }
1073
_HAL_INTERN_DTMB_SetModeClean(void)1074 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1075 {
1076 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1077 return _MBX_WriteReg(0x20C0, 0x00);
1078 }
1079
_HAL_INTERN_DTMB_Set_QAM_SR(void)1080 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1081 {
1082 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1083 return _MBX_WriteReg(0x20C0, 0x04);
1084 }
1085
_HAL_INTERN_DTMB_AGCLock(void)1086 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1087 {
1088 MS_U8 data = 0;
1089
1090 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1091
1092 if (data&0x01)
1093 {
1094 return TRUE;
1095 }
1096 else
1097 {
1098 return FALSE;
1099 }
1100 }
1101
_HAL_INTERN_DTMB_PNP_Lock(void)1102 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1103 {
1104 MS_U8 data = 0;
1105 MS_U8 data1 = 0;
1106
1107 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1108 _MBX_ReadReg(0x37BA, &data);
1109 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1110 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1111 _MBX_ReadReg(0x3BBA, &data);
1112 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1113 #else
1114 _MBX_ReadReg(0x22BA, &data);
1115 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1116 #endif
1117
1118 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1119 {
1120 return TRUE;
1121 }
1122 else
1123 {
1124 return FALSE;
1125 }
1126 }
1127
_HAL_INTERN_DTMB_FEC_Lock(void)1128 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1129 {
1130 MS_U8 u8state=0;
1131
1132
1133 _MBX_ReadReg(0x20C1, &u8state);
1134
1135 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1136 {
1137 return TRUE;
1138 }
1139 else
1140 {
1141 return FALSE;
1142 }
1143 }
1144
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1145 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1146 {
1147 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1148
1149 MS_U8 CM, QAM, IL, CR, SiNR;
1150 MS_U8 data_L = 0;
1151 MS_U8 data_H = 0;
1152
1153 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1154 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1155 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1156 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1157 {
1158 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1159 _MBX_ReadReg(0x3790, &data_L);
1160 _MBX_ReadReg(0x3791, &data_H);
1161 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1162 _MBX_ReadReg(0x3B90, &data_L);
1163 _MBX_ReadReg(0x3B91, &data_H);
1164 #else
1165 _MBX_ReadReg(0x2290, &data_L);
1166 _MBX_ReadReg(0x2291, &data_H);
1167 #endif
1168
1169 if (data_L & 0x1)
1170 {
1171 CR = (data_L >> 6) & 0x03;
1172 IL = (data_L >> 3) & 0x01;
1173 QAM = (data_L >> 4) & 0x03;
1174 SiNR = (data_L >> 2) & 0x01;
1175 CM = (data_L >> 1) & 0x01;
1176 }
1177 else
1178 {
1179 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1180 _MBX_ReadReg(0x379E, &data_L);
1181 _MBX_ReadReg(0x379F, &data_H);
1182 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1183 _MBX_ReadReg(0x3B9E, &data_L);
1184 _MBX_ReadReg(0x3B9F, &data_H);
1185 #else
1186 _MBX_ReadReg(0x229E, &data_L);
1187 _MBX_ReadReg(0x229F, &data_H);
1188 #endif
1189
1190 CR = (data_H >> 4) & 0x03;
1191 IL = (data_H >> 6) & 0x01;
1192 QAM = (data_H >> 2) & 0x03;
1193 SiNR = (data_H >> 1) & 0x01;
1194 CM = (data_H) & 0x01;
1195 }
1196
1197 if (CR == 0)
1198 psDtmbGetModulation->fSiCodeRate = 0.4;
1199 else if (CR == 1)
1200 psDtmbGetModulation->fSiCodeRate = 0.6;
1201 else if (CR == 2)
1202 psDtmbGetModulation->fSiCodeRate = 0.8;
1203
1204 if (IL == 0)
1205 psDtmbGetModulation->u8SiInterLeaver = 240;
1206 else
1207 psDtmbGetModulation->u8SiInterLeaver = 720;
1208
1209 if (QAM == 0)
1210 psDtmbGetModulation->u8SiQamMode = 4;
1211 else if (QAM == 1)
1212 psDtmbGetModulation->u8SiQamMode = 16;
1213 else if (QAM == 2)
1214 psDtmbGetModulation->u8SiQamMode = 32;
1215 else if (QAM == 3)
1216 psDtmbGetModulation->u8SiQamMode = 64;
1217
1218 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1219 psDtmbGetModulation->u8SiNR = SiNR;
1220 }
1221 else
1222 {
1223 }
1224
1225 return TRUE;
1226 }
1227
_HAL_INTERN_DTMB_ReadIFAGC(void)1228 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1229 {
1230 MS_U8 data = 0;
1231
1232 _MBX_ReadReg(0x28FD, &data);
1233
1234 return data;
1235 }
1236
_HAL_INTERN_DTMB_ReadFrequencyOffset(void)1237 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1238 {
1239 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1240
1241 MS_U8 u8Data = 0;
1242 MS_S16 fftfirstCfo = 0;
1243 MS_S8 fftSecondCfo = 0;
1244 MS_S16 sr = 0;
1245
1246 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1247 _MBX_ReadReg(0x384D, &u8Data);
1248 fftfirstCfo = u8Data;
1249 _MBX_ReadReg(0x384C, &u8Data);
1250 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1251
1252 _MBX_ReadReg(0x3850, &u8Data);
1253 fftSecondCfo = u8Data;
1254 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1255 _MBX_ReadReg(0x3C4D, &u8Data);
1256 fftfirstCfo = u8Data;
1257 _MBX_ReadReg(0x3C4C, &u8Data);
1258 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1259
1260 _MBX_ReadReg(0x3C50, &u8Data);
1261 fftSecondCfo = u8Data;
1262 #else
1263 _MBX_ReadReg(0x234D, &u8Data);
1264 fftfirstCfo = u8Data;
1265 _MBX_ReadReg(0x234C, &u8Data);
1266 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1267
1268 _MBX_ReadReg(0x2350, &u8Data);
1269 fftSecondCfo = u8Data;
1270 #endif
1271
1272 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1273 sr = 5670;
1274 else sr = 7560;
1275
1276 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1277 }
1278
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1279 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1280 {
1281 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1282
1283 MS_U8 data = 0;
1284 MS_U8 level = 0;
1285 MS_U32 snr = 0;
1286
1287 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1288 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1289 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1290 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1291 {
1292 if (!_HAL_INTERN_DTMB_FEC_Lock())
1293 level = 0;
1294 else
1295 {
1296 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1297 _MBX_ReadReg(0x37DA, &data);
1298 snr = data&0x3F;
1299 _MBX_ReadReg(0x37D9, &data);
1300 snr = (snr<<8)|data;
1301 _MBX_ReadReg(0x37D8, &data);
1302 snr = (snr<<8)|data;
1303 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1304 _MBX_ReadReg(0x3BDA, &data);
1305 snr = data&0x3F;
1306 _MBX_ReadReg(0x3BD9, &data);
1307 snr = (snr<<8)|data;
1308 _MBX_ReadReg(0x3BD8, &data);
1309 snr = (snr<<8)|data;
1310 #else
1311 _MBX_ReadReg(0x22DA, &data);
1312 snr = data&0x3F;
1313 _MBX_ReadReg(0x22D9, &data);
1314 snr = (snr<<8)|data;
1315 _MBX_ReadReg(0x22D8, &data);
1316 snr = (snr<<8)|data;
1317 #endif
1318
1319 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1320 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1321 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1322 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1323 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1324 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1325 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1326 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1327 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1328 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1329 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1330 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1331 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1332 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1333 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1334 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1335 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1336 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1337 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1338 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1339 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1340 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1341 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1342 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1343 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1344 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1345 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1346 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1347 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1348 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1349 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1350 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1351 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1352 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1353 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1354 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1355 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1356 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1357 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1358 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1359 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1360 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1361 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1362 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1363 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1364 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1365 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1366 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1367 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1368 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1369 }
1370 }
1371 else
1372 {
1373 level = 0;
1374 }
1375
1376 return level*2;
1377 }
1378
_HAL_INTERN_DTMB_GetPreLdpcBer(float * pber)1379 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1380 {
1381 MS_U8 u8Data=0;
1382 MS_U32 BitErr;
1383 MS_U16 error_window;
1384
1385 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1386 _MBX_ReadReg(0x2D3B, &u8Data);
1387 BitErr = u8Data;
1388 _MBX_ReadReg(0x2D3A, &u8Data);
1389 BitErr = (BitErr << 8)|u8Data;
1390 _MBX_ReadReg(0x2D39, &u8Data);
1391 BitErr = (BitErr << 8)|u8Data;
1392 _MBX_ReadReg(0x2D38, &u8Data);
1393 BitErr = (BitErr << 8)|u8Data;
1394 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1395 _MBX_ReadReg(0x3F3B, &u8Data);
1396 BitErr = u8Data;
1397 _MBX_ReadReg(0x3F3A, &u8Data);
1398 BitErr = (BitErr << 8)|u8Data;
1399 _MBX_ReadReg(0x3F39, &u8Data);
1400 BitErr = (BitErr << 8)|u8Data;
1401 _MBX_ReadReg(0x3F38, &u8Data);
1402 BitErr = (BitErr << 8)|u8Data;
1403 #else
1404 _MBX_ReadReg(0x263B, &u8Data);
1405 BitErr = u8Data;
1406 _MBX_ReadReg(0x263A, &u8Data);
1407 BitErr = (BitErr << 8)|u8Data;
1408 _MBX_ReadReg(0x2639, &u8Data);
1409 BitErr = (BitErr << 8)|u8Data;
1410 _MBX_ReadReg(0x2638, &u8Data);
1411 BitErr = (BitErr << 8)|u8Data;
1412 #endif
1413
1414 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1415 _MBX_ReadReg(0x2D2F, &u8Data);
1416 error_window = u8Data;
1417 _MBX_ReadReg(0x2D2E, &u8Data);
1418 error_window = (error_window << 8)|u8Data;
1419 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1420 _MBX_ReadReg(0x3F2F, &u8Data);
1421 error_window = u8Data;
1422 _MBX_ReadReg(0x3F2E, &u8Data);
1423 error_window = (error_window << 8)|u8Data;
1424 #else
1425 _MBX_ReadReg(0x262F, &u8Data);
1426 error_window = u8Data;
1427 _MBX_ReadReg(0x262E, &u8Data);
1428 error_window = (error_window << 8)|u8Data;
1429 #endif
1430
1431 *pber=(float)BitErr/7488.0/(float)error_window;
1432
1433 return TRUE;
1434 }
1435
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)1436 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
1437 {
1438 return _MBX_ReadReg(u16Addr, pu8Data);
1439 }
1440
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)1441 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
1442 {
1443 return _MBX_WriteReg(u16Addr, u8Data);
1444 }
1445
1446 //-------------------------------------------------------------------------------------------------
1447 // Global Functions
1448 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)1449 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
1450 {
1451 MS_BOOL bResult = TRUE;
1452
1453 switch(eCmd)
1454 {
1455 case DMD_DTMB_HAL_CMD_Exit:
1456 bResult = _HAL_INTERN_DTMB_Exit();
1457 break;
1458 case DMD_DTMB_HAL_CMD_InitClk:
1459 _HAL_INTERN_DTMB_InitClk();
1460 break;
1461 case DMD_DTMB_HAL_CMD_Download:
1462 bResult = _HAL_INTERN_DTMB_Download();
1463 break;
1464 case DMD_DTMB_HAL_CMD_FWVERSION:
1465 _HAL_INTERN_DTMB_FWVERSION();
1466 break;
1467 case DMD_DTMB_HAL_CMD_SoftReset:
1468 bResult = _HAL_INTERN_DTMB_SoftReset();
1469 break;
1470 case DMD_DTMB_HAL_CMD_SetACICoef:
1471 bResult = _HAL_INTERN_DTMB_SetACICoef();
1472 break;
1473 case DMD_DTMB_HAL_CMD_SetDTMBMode:
1474 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
1475 break;
1476 case DMD_DTMB_HAL_CMD_SetModeClean:
1477 bResult = _HAL_INTERN_DTMB_SetModeClean();
1478 break;
1479 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
1480 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
1481 break;
1482 case DMD_DTMB_HAL_CMD_Active:
1483 break;
1484 case DMD_DTMB_HAL_CMD_AGCLock:
1485 bResult = _HAL_INTERN_DTMB_AGCLock();
1486 break;
1487 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
1488 bResult = _HAL_INTERN_DTMB_PNP_Lock();
1489 break;
1490 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
1491 bResult = _HAL_INTERN_DTMB_FEC_Lock();
1492 break;
1493 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
1494 break;
1495 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
1496 break;
1497 case DMD_DTMB_HAL_CMD_GetModulation:
1498 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
1499 case DMD_DTMB_HAL_CMD_ReadIFAGC:
1500 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
1501 break;
1502 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
1503 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
1504 break;
1505 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
1506 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
1507 break;
1508 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
1509 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
1510 break;
1511 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
1512 break;
1513 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
1514 break;
1515 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
1516 break;
1517 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
1518 break;
1519 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
1520 break;
1521 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
1522 break;
1523 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
1524 break;
1525 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
1526 break;
1527 case DMD_DTMB_HAL_CMD_GET_REG:
1528 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
1529 break;
1530 case DMD_DTMB_HAL_CMD_SET_REG:
1531 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
1532 break;
1533 default:
1534 break;
1535 }
1536
1537 return bResult;
1538 }
1539
MDrv_DMD_DTMB_Initial_Hal_Interface(void)1540 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
1541 {
1542 return TRUE;
1543 }
1544
1545