1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #include <stdio.h>
101 #include <math.h>
102
103 #include "drvDMD_ATSC.h"
104
105 #include "MsTypes.h"
106 #if DMD_ATSC_UTOPIA_EN || DMD_ATSC_UTOPIA2_EN
107 #include "drvDMD_common.h"
108 #include "halDMD_INTERN_common.h"
109 #endif
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114
115 #define DMD_ATSC_CHIP_T3_T10 0x01
116 #define DMD_ATSC_CHIP_T7 0x02
117 #define DMD_ATSC_CHIP_T8_T9 0x03
118 #define DMD_ATSC_CHIP_A1 0x04
119 #define DMD_ATSC_CHIP_A3 0x05
120 #define DMD_ATSC_CHIP_A5 0x06
121 #define DMD_ATSC_CHIP_A7 0x07
122 #define DMD_ATSC_CHIP_A7P 0x08
123 #define DMD_ATSC_CHIP_AGATE 0x09
124 #define DMD_ATSC_CHIP_EDISON 0x0A
125 #define DMD_ATSC_CHIP_EINSTEIN 0x0B
126 #define DMD_ATSC_CHIP_EMERALD 0x0C
127 #define DMD_ATSC_CHIP_EIFFEL 0x0D
128 #define DMD_ATSC_CHIP_EDEN 0x0E
129 #define DMD_ATSC_CHIP_EINSTEIN3 0x0F
130 #define DMD_ATSC_CHIP_MONACO 0x10
131 #define DMD_ATSC_CHIP_MIAMI 0x11
132 #define DMD_ATSC_CHIP_MUJI 0x12
133
134 #define DMD_ATSC_CHIP_K3 0x80 //UTOF start from 0x80
135 #define DMD_ATSC_CHIP_KELTIC 0x81
136 #define DMD_ATSC_CHIP_KERES 0x82
137
138 #if defined(a1)
139 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A1
140 #elif defined(a3)
141 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A3
142 #elif defined(a5)
143 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A5
144 #elif defined(a7)
145 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7
146 #elif defined(amethyst)
147 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7P
148 #elif defined(agate)
149 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_AGATE
150 #elif defined(edison)
151 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDISON
152 #elif defined(einstein)
153 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN
154 #elif defined(einstein3)
155 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN3
156 #elif defined(monaco)
157 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MONACO
158 #elif defined(emerald)
159 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EMERALD
160 #elif defined(eiffel)
161 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EIFFEL
162 #elif defined(kaiser)
163 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_K3
164 #elif defined(keltic)
165 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KELTIC
166 #elif defined(eden)
167 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDEN
168 #elif defined(miami)
169 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MIAMI
170 #elif defined(keres)
171 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KERES
172 #elif defined(muji)
173 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUJI
174 #else
175 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EMERALD
176 #endif
177
178 //-------------------------------------------------------------------------------------------------
179 // Local Defines
180 //-------------------------------------------------------------------------------------------------
181
182 #define HAL_INTERN_ATSC_DBINFO(y) //y
183
184 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
185 #ifndef MBRegBase
186 #define MBRegBase 0x112600UL
187 #endif
188 #ifndef MBRegBase_DMD1
189 #define MBRegBase_DMD1 0x112400UL
190 #endif
191 #else
192 #define MBRegBase 0x110500UL
193 #endif
194
195 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
196 #define DMDMcuBase 0x103460UL
197 #else
198 //#define DMDMcuBase 0x103480UL
199 #endif
200
201 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
202 #define INTERN_ATSC_OUTER_STATE 0xF0
203 #else
204 #define INTERN_ATSC_OUTER_STATE 0x80
205 #endif
206 #define INTERN_ATSC_VSB_TRAIN_SNR_LIMIT 0x05//0xBE//14.5dB
207 #define INTERN_ATSC_FEC_ENABLE 0x1F
208
209 #define VSB_ATSC 0x04
210 #define QAM256_ATSC 0x02
211
212 #define QAM16_J83ABC 0x00
213 #define QAM32_J83ABC 0x01
214 #define QAM64_J83ABC 0x02
215 #define QAM128_J83ABC 0x03
216 #define QAM256_J83ABC 0x04
217
218 //-------------------------------------------------------------------------------------------------
219 // Local Variables
220 //-------------------------------------------------------------------------------------------------
221
222 const MS_U8 INTERN_ATSC_table[] = {
223 #include "DMD_INTERN_ATSC.dat"
224 };
225
226 static MS_U16 u16Lib_size = sizeof(INTERN_ATSC_table);
227
228 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
229
230 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
231 static MS_U8 Demod_Flow_register[17] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
232 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x08, 0x70, 0x68};
233 #else
234 static MS_U8 Demod_Flow_register[21] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
235 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x00, 0x00, 0x00, 0x00,
236 0x00, 0x00, 0x00};
237 #endif
238
239 #endif
240
241 //-------------------------------------------------------------------------------------------------
242 // Global Variables
243 //-------------------------------------------------------------------------------------------------
244
245 extern MS_U8 u8DMD_ATSC_DMD_ID;
246
247 extern DMD_ATSC_ResData *psDMD_ATSC_ResData;
248
249 //-------------------------------------------------------------------------------------------------
250 // Local Functions
251 //-------------------------------------------------------------------------------------------------
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)252 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
253 {
254 MS_U8 u8CheckCount;
255 MS_U8 u8CheckFlag = 0xFF;
256
257 if (u8DMD_ATSC_DMD_ID == 0)
258 {
259 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
260 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
261 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
262 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
263 }
264 else if (u8DMD_ATSC_DMD_ID == 1)
265 {
266 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff));
267 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8));
268 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x10, u8Data);
269 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x01);
270 }
271
272 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
273 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
274
275 if (u8DMD_ATSC_DMD_ID == 0)
276 {
277 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
278 {
279 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
280 if ((u8CheckFlag&0x01)==0)
281 break;
282 MsOS_DelayTask(1);
283 }
284 }
285 else if (u8DMD_ATSC_DMD_ID == 1)
286 {
287 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
288 {
289 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase_DMD1 + 0x1E);
290 if ((u8CheckFlag&0x01)==0)
291 break;
292 MsOS_DelayTask(1);
293 }
294 }
295
296
297 if (u8CheckFlag&0x01)
298 {
299 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
300 return FALSE;
301 }
302
303 return TRUE;
304 }
305
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)306 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
307 {
308 MS_U8 u8CheckCount;
309 MS_U8 u8CheckFlag = 0xFF;
310
311 if (u8DMD_ATSC_DMD_ID == 0)
312 {
313 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
314 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
315 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
316 }
317 else if (u8DMD_ATSC_DMD_ID == 1)
318 {
319 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x00, (u16Addr&0xff));
320 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x01, (u16Addr>>8));
321 HAL_DMD_RIU_WriteByte(MBRegBase_DMD1 + 0x1E, 0x02);
322 }
323
324
325 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
326 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
327
328 if (u8DMD_ATSC_DMD_ID == 0)
329 {
330 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
331 {
332 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
333 if ((u8CheckFlag&0x02)==0)
334 {
335 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
336 }
337 MsOS_DelayTask(1);
338 }
339 }
340 else if (u8DMD_ATSC_DMD_ID == 1)
341 {
342 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
343 {
344 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase_DMD1 + 0x1E);
345 if ((u8CheckFlag&0x02)==0)
346 {
347 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase_DMD1 + 0x10);
348 }
349 MsOS_DelayTask(1);
350 }
351 }
352
353 if (u8CheckFlag&0x02)
354 {
355 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
356 return FALSE;
357 }
358
359 return TRUE;
360 }
361
362 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_SEL_DMD(void)363 static MS_BOOL _SEL_DMD(void)
364 {
365 MS_U8 u8data = 0;
366
367 u8data = HAL_DMD_RIU_ReadByte(0x101e3c);
368
369 if (u8DMD_ATSC_DMD_ID == 0) //select DMD0
370 u8data &= (~0x10);
371 else if (u8DMD_ATSC_DMD_ID == 1) //sel DMD1
372 u8data |= 0x10;
373
374 HAL_DMD_RIU_WriteByte(0x101e3c, u8data);
375
376 return TRUE;
377 }
378 #endif
379
380 #if ((DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1) && (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3))
_initTable(void)381 static void _initTable(void)
382 {
383 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
384
385 if (pRes->sDMD_ATSC_InitData.bTunerGainInvert)
386 Demod_Flow_register[12]=1;
387 else Demod_Flow_register[12]=0;
388
389 if (pRes->sDMD_ATSC_InitData.bIQSwap)
390 Demod_Flow_register[14] = 1;
391 else Demod_Flow_register[14] = 0;
392
393 Demod_Flow_register[15] = pRes->sDMD_ATSC_InitData.u16IF_KHZ&0xFF;
394 Demod_Flow_register[16] = (pRes->sDMD_ATSC_InitData.u16IF_KHZ)>>8;
395
396 printf("\n#### IF_KHz = [%d]\n", pRes->sDMD_ATSC_InitData.u16IF_KHZ);
397 printf("\n#### IQ_SWAP = [%d]\n", pRes->sDMD_ATSC_InitData.bIQSwap);
398 printf("\n#### Tuner Gain Invert = [%d]\n", pRes->sDMD_ATSC_InitData.bTunerGainInvert);
399 }
400 #endif
401
402 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)403 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
404 {
405 printf("--------------DMD_ATSC_CHIP_T3_T10--------------\n");
406
407 // MailBox
408 HAL_DMD_RIU_WriteByte(0x100b44, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 0--> aeon
409 HAL_DMD_RIU_WriteByte(0x100b45, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 1--> aeon
410
411 // Enable DMD MCU clock (108MHz)
412 if (HAL_DMD_RIU_ReadByte(0x001ecf) == 0x00)
413 HAL_DMD_RIU_WriteByte(0x100b42, 0x10);
414 else //after t3_u02
415 HAL_DMD_RIU_WriteByte(0x100b42, 0x0D);
416
417 HAL_DMD_RIU_WriteByte(0x100b43, 0x01); // Disable VD200 clock
418
419 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
420
421 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
422
423 // Enable ATSC clock
424 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
425 HAL_DMD_RIU_WriteByte(0x103303, 0x00);
426 HAL_DMD_RIU_WriteByte(0x103304, 0x00);
427 HAL_DMD_RIU_WriteByte(0x103305, 0x00);
428 HAL_DMD_RIU_WriteByte(0x103306, 0x00);
429 HAL_DMD_RIU_WriteByte(0x103307, 0x00);
430 HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
431
432 // Enable DVB INNERx1&2 clock
433 HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
434 HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
435
436 // Enable DVB SRAM0~SRAM3 clock
437 HAL_DMD_RIU_WriteByte(0x103318, 0x00);
438 HAL_DMD_RIU_WriteByte(0x103319, 0x00);
439
440 HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
441 HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
442
443 HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
444 HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
445
446 MsOS_DelayTaskUs(1);
447
448 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
449
450 HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
451 HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
452
453 HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
454 HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
455
456 if (bRFAGCTristateEnable)
457 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
458 else
459 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
460 }
461 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)462 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
463 {
464 printf("--------------DMD_ATSC_CHIP_T7--------------\n");
465
466 HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Enable DMD MCU clock (108MHz)
467
468 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
469
470 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
471
472 // Enable ATSC clock
473 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
474 HAL_DMD_RIU_WriteByte(0x103303, 0x00);
475 HAL_DMD_RIU_WriteByte(0x103304, 0x00);
476 HAL_DMD_RIU_WriteByte(0x103305, 0x00);
477 HAL_DMD_RIU_WriteByte(0x103306, 0x00);
478 HAL_DMD_RIU_WriteByte(0x103307, 0x00);
479 HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
480
481 // Enable DVB INNERx1&2&4 clock
482 HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
483 HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
484 HAL_DMD_RIU_WriteByte(0x10330e, 0x00);
485
486 // Enable DVB OUTERx1&2&2_c clock
487 HAL_DMD_RIU_WriteByte(0x103310, 0x00);
488 HAL_DMD_RIU_WriteByte(0x103311, 0x00);
489 HAL_DMD_RIU_WriteByte(0x103312, 0x00);
490
491 // Enable DVB EQx1&8c clock
492 HAL_DMD_RIU_WriteByte(0x103316, 0x00);
493 HAL_DMD_RIU_WriteByte(0x103317, 0x00);
494
495 // Enable DVB SRAM0~SRAM3 clock
496 HAL_DMD_RIU_WriteByte(0x103318, 0x00);
497 HAL_DMD_RIU_WriteByte(0x103319, 0x00);
498
499 HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
500 HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
501
502 HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
503 HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
504
505 MsOS_DelayTaskUs(1);
506
507 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
508
509 HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
510 HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
511
512 HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
513 HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
514
515 HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
516
517 if (bRFAGCTristateEnable)
518 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
519 else
520 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
521
522 HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
523
524 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x01);
525 HAL_DMD_RIU_WriteByteMask(0x112003, 0x20, 0x20); // Release Ana misc resest
526 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x01, 0x01);
527
528 // Set DMD ANA
529 HAL_DMD_RIU_WriteByte(0x112864, 0x00); // Set VCO first and second div
530 HAL_DMD_RIU_WriteByte(0x112865, 0x00);
531
532 HAL_DMD_RIU_WriteByte(0x11286C, 0x20); // Disable T&RF-AGC
533 HAL_DMD_RIU_WriteByte(0x11286D, 0x00);
534
535 HAL_DMD_RIU_WriteByte(0x112868, 0x00);
536 HAL_DMD_RIU_WriteByte(0x112869, 0x80);
537
538 HAL_DMD_RIU_WriteByte(0x112862, 0x00); // Set PLL first and second div
539 HAL_DMD_RIU_WriteByte(0x112863, 0x00);
540
541 HAL_DMD_RIU_WriteByte(0x112818, 0x03); // ADC I&Q pown down
542 HAL_DMD_RIU_WriteByte(0x112819, 0x00);
543
544 MsOS_DelayTaskUs(2);
545
546 HAL_DMD_RIU_WriteByte(0x11286A, 0x86); // Initial MPLL procedure
547 HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
548 MsOS_DelayTaskUs(2);
549 HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
550 HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
551 MsOS_DelayTaskUs(2);
552 HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
553 HAL_DMD_RIU_WriteByte(0x11286B, 0x06);
554
555 MsOS_DelayTaskUs(2);
556
557 HAL_DMD_RIU_WriteByte(0x112866, 0x01); // Set MPLL first and second div
558 HAL_DMD_RIU_WriteByte(0x112867, 0x1d);
559
560 HAL_DMD_RIU_WriteByte(0x112860, 0x00); // MPLL power up
561 HAL_DMD_RIU_WriteByte(0x112861, 0x1c); // Set ADC output div
562
563 HAL_DMD_RIU_WriteByte(0x112802, 0x40); // Set ADC I&Q
564 HAL_DMD_RIU_WriteByte(0x112803, 0x04);
565
566 HAL_DMD_RIU_WriteByte(0x112816, 0x05); // set PGA gain
567 HAL_DMD_RIU_WriteByte(0x112817, 0x05);
568
569 HAL_DMD_RIU_WriteByte(0x112818, 0x00); // ADC I&Q pown up
570 HAL_DMD_RIU_WriteByte(0x112819, 0x00);
571
572 HAL_DMD_RIU_WriteByte(0x112840, 0x00); // Disable SIF&VIF
573 HAL_DMD_RIU_WriteByte(0x112841, 0x00);
574 }
575 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)576 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
577 {
578 printf("--------------DMD_ATSC_CHIP_T8_T9--------------\n");
579
580 HAL_DMD_RIU_WriteByte(0x10331E, 0x10); // Enable DMD MCU clock (108MHz)
581
582 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
583
584 // Enable ATSC clock
585 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
586 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
587 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
588 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
589 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
590 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
591 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
592 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
593
594 // Disable DVB INNERx1&2&4 clock
595 HAL_DMD_RIU_WriteByte(0x111f0c, 0x01);
596 HAL_DMD_RIU_WriteByte(0x111f0d, 0x01);
597 HAL_DMD_RIU_WriteByte(0x111f0e, 0x01);
598
599 // Disable DVB OUTERx1&2&2_c clock
600 HAL_DMD_RIU_WriteByte(0x111f10, 0x01);
601 HAL_DMD_RIU_WriteByte(0x111f11, 0x01);
602 HAL_DMD_RIU_WriteByte(0x111f12, 0x01);
603
604 // Disable DVB INNER clock
605 HAL_DMD_RIU_WriteByte(0x111f15, 0x01);
606
607 // Disable DVB EQx1&8c clock
608 HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
609 HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
610
611 // Enable DVB SRAM0~SRAM3 clock
612 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
613 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
614
615 HAL_DMD_RIU_WriteByte(0x103300, 0x11); // Set DMD clock div
616 HAL_DMD_RIU_WriteByte(0x103301, 0x05); // Enable DMD clock
617
618 HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
619 HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
620
621 // Disable VIF clock
622 HAL_DMD_RIU_WriteByte(0x111f1c, 0x01);
623 HAL_DMD_RIU_WriteByte(0x111f1d, 0x01);
624 HAL_DMD_RIU_WriteByte(0x10331a, 0x01);
625 HAL_DMD_RIU_WriteByte(0x10331b, 0x01);
626
627 MsOS_DelayTaskUs(1);
628
629 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
630
631 HAL_DMD_RIU_WriteByteMask(0x101eaf, 0x10, 0x18); // Set TS PAD
632
633 if (bRFAGCTristateEnable)
634 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
635 else
636 HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
637
638 HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
639
640 HAL_DMD_RIU_WriteByteMask(0x101ea0, 0x00, 0x03); // PWM2 uses PAD_PWM2 and PWM3 uses PAD_PWM3
641 HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
642
643 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
644 }
645 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A1)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)646 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
647 {
648 printf("--------------DMD_ATSC_CHIP_A1--------------\n");
649
650 //Set register at CLKGEN1
651 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
652 HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Denny: change 0x10!! 108M
653
654 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
655
656 // set parallet ts clock
657 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
658 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
659
660 // enable atsc, DVBTC ts clock
661 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
662 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
663
664 // enable dvbc adc clock
665 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
666
667 // enable vif DAC clock
668 HAL_DMD_RIU_WriteByte(0x10331b, 0x00);
669 HAL_DMD_RIU_WriteByte(0x10331a, 0x00);
670
671 // Set register at CLKGEN_DMD
672 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
673 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
674 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
675 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
676 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
677 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
678
679 // enable clk_atsc_adcd_sync
680 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
681 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
682
683 // enable dvbt inner clock
684 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
685 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
686
687 // enable dvbt inner clock
688 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
689 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
690
691 // enable dvbt inner clock
692 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
693 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
694
695 // enable dvbc outer clock
696 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
697 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
698
699 // enable dvbc inner-c clock
700 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
701 HAL_DMD_RIU_WriteByte(0x111f14, 0x00);
702
703 // enable dvbc eq clock
704 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
705 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
706
707 // enable vif clock
708 HAL_DMD_RIU_WriteByte(0x111f1d, 0x00);
709 HAL_DMD_RIU_WriteByte(0x111f1c, 0x00);
710
711 // For ADC DMA Dump
712 HAL_DMD_RIU_WriteByte(0x111f21, 0x00);
713 HAL_DMD_RIU_WriteByte(0x111f20, 0x00);
714
715 // select clock
716 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
717 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
718
719 MsOS_DelayTaskUs(1);
720
721 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
722
723 // Turn TSP
724 HAL_DMD_RIU_WriteByte(0x100b55, 0x00);
725 HAL_DMD_RIU_WriteByte(0x100b54, 0x00);
726
727 // set the ts0_clk from demod
728 HAL_DMD_RIU_WriteByte(0x100b51, 0x00);
729 HAL_DMD_RIU_WriteByte(0x100b50, 0x0C);
730 HAL_DMD_RIU_WriteByte(0x101e22, 0x02);
731
732 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
733 }
734 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)735 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
736 {
737 printf("--------------DMD_ATSC_CHIP_A7--------------\n");
738
739 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
740 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
741
742 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
743
744 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
745 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
746 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
747 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
748 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
749 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
750 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
751 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
752 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
753 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
754 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
755 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
756 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
757 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
758 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
759 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
760 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
761 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
762 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
763 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
764 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
765 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
766 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
767 HAL_DMD_RIU_WriteByte(0x111f25, 0x00);
768 HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
769 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
770 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
771
772 MsOS_DelayTaskUs(1);
773
774 HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
775
776 HAL_DMD_RIU_WriteByteMask(0x000e13, 0x00, 0x04);
777
778 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
779 }
780 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)781 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
782 {
783 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
784
785 printf("--------------DMD_ATSC_CHIP_K3--------------\n");
786
787 if (pRes->sDMD_ATSC_InitData.u8IS_DUAL)
788 {
789 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
790 HAL_DMD_RIU_WriteByte(0x101e3d, 0x00);
791
792 /****************DMD0****************/
793
794 //set CLK_DMDMCU as 108M Hz
795 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
796
797 // set parallet ts clock
798 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
799 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
800
801 // enable DVBTC ts clock
802 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
803
804 // enable dvbc adc clock
805 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
806 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
807
808 // enable clk_atsc_adcd_sync
809 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
810 HAL_DMD_RIU_WriteByte(0x111f0a, 0x04);
811
812 // enable dvbt inner clock
813 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
814
815 // enable dvbt outer clock
816 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
817
818 // enable dvbc outer clock
819 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
820 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
821
822 // enable dvbc inner-c clock
823 HAL_DMD_RIU_WriteByte(0x111f15, 0x04);
824
825 // enable dvbc eq clock
826 HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
827 HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
828
829 // For ADC DMA Dump
830 HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
831
832 // Turn TSP
833 //HAL_DMD_RIU_WriteByte(0x000e13, 0x01);
834
835 //set reg_allpad_in
836 HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
837 HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
838 HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
839
840 /****************DMD1****************/
841 HAL_DMD_RIU_WriteByte(0x10331f, 0x10);
842
843 HAL_DMD_RIU_WriteByte(0x103321, 0x07);
844 HAL_DMD_RIU_WriteByte(0x103320, 0x11);
845
846 HAL_DMD_RIU_WriteByte(0x103323, 0x00);
847 HAL_DMD_RIU_WriteByte(0x103322, 0x00);
848
849 HAL_DMD_RIU_WriteByte(0x11220b, 0x00);
850 HAL_DMD_RIU_WriteByte(0x11220a, 0x04);
851
852 HAL_DMD_RIU_WriteByte(0x11220c, 0x00);
853 HAL_DMD_RIU_WriteByte(0x112211, 0x00);
854
855 HAL_DMD_RIU_WriteByte(0x112213, 0x00);
856 HAL_DMD_RIU_WriteByte(0x112212, 0x00);
857
858 HAL_DMD_RIU_WriteByte(0x112215, 0x04);
859
860 HAL_DMD_RIU_WriteByte(0x112217, 0x00);
861 HAL_DMD_RIU_WriteByte(0x112216, 0x00);
862
863 HAL_DMD_RIU_WriteByte(0x112222, 0x04);
864
865 HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
866 HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
867 }
868 else
869 {
870 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
871
872 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
873 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
874
875 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
876 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
877
878 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
879
880 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
881 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
882
883 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
884 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
885
886 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
887
888 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
889
890 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
891 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
892
893 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
894
895 HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
896 HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
897
898 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
899
900 HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
901 HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
902 HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
903
904 HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
905 HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
906 }
907 }
908 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KELTIC)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)909 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
910 {
911 printf("--------------DMD_ATSC_CHIP_KELTIC--------------\n");
912
913 HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
914
915 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
916 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
917
918 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
919 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
920
921 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
922
923 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
924 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
925
926 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
927 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
928
929 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
930 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
931
932 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
933
934 HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
935 HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
936
937 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
938
939 HAL_DMD_RIU_WriteByte(0x1120bc, 0x00);
940
941 HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
942 HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
943
944 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
945 }
946 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KERES)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)947 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
948 {
949 MS_U8 u8Val=0x00;
950
951 printf("--------------DMD_ATSC_CHIP_KERES--------------\n");
952
953 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
954 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
955
956 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
957 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
958 HAL_DMD_RIU_WriteByte(0x103301,0x07);
959 HAL_DMD_RIU_WriteByte(0x103300,0x11);
960 HAL_DMD_RIU_WriteByte(0x103309,0x00);
961 HAL_DMD_RIU_WriteByte(0x103315,0x00);
962 HAL_DMD_RIU_WriteByte(0x103314,0x00);
963
964 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
965 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
966 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
967 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
968 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
969 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
970 HAL_DMD_RIU_WriteByte(0x111f15,0x00);
971 HAL_DMD_RIU_WriteByte(0x111f17,0x00);
972 HAL_DMD_RIU_WriteByte(0x111f16,0x00);
973 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
974 HAL_DMD_RIU_WriteByte(0x111f2b,0x00); //enable clk_rs
975 HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
976 //HAL_DMD_RIU_WriteByte(0x000e13,0x01); // No need, it cause uart issue.
977 HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
978
979 HAL_DMD_RIU_WriteByte(0x101e04,0x02);
980 HAL_DMD_RIU_WriteByte(0x101e76,0x03);
981
982 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
983 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
984 }
985 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDEN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)986 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
987 {
988 MS_U8 u8Val = 0x00;
989
990 printf("--------------DMD_ATSC_CHIP_EDEN--------------\n");
991
992 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
993 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
994
995 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
996 HAL_DMD_RIU_WriteByte(0x103301,0x04);
997 HAL_DMD_RIU_WriteByte(0x103300,0x0B);
998 HAL_DMD_RIU_WriteByte(0x103309,0x00);
999 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1000 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1001 HAL_DMD_RIU_WriteByte(0x103314,0x04);
1002
1003 HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1005 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1006 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1007 HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1008 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1009 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1010 HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1011
1012 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1013 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1014 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1015 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1016
1017 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1018 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1019 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1020 HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1021 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1022 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1023 HAL_DMD_RIU_WriteByte(0x111f23,0x40);
1024 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1025
1026 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1027 HAL_DMD_RIU_WriteByte(0x101e39, (u8Val|0x03));
1028 }
1029 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EMERALD)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1030 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1031 {
1032 MS_U8 u8Val = 0x00;
1033
1034 printf("--------------DMD_ATSC_CHIP_EMERALD--------------\n");
1035
1036 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1037 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1038
1039 HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1040 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1041 HAL_DMD_RIU_WriteByte(0x103301,0x05);//Different with EDEN!
1042 HAL_DMD_RIU_WriteByte(0x103300,0x11);//Different with EDEN!
1043 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1044 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1045 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1046 HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1047
1048 HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1049 HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1050 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1051 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1052 HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1053 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1054 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1055 HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1056
1057 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1058 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1059 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1060 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1061
1062 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1063 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1064 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1065 HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1066 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1067 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1068 HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1069 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1070
1071 HAL_DMD_RIU_WriteByte(0x111f25,0x00);//Different with EDEN!
1072 HAL_DMD_RIU_WriteByte(0x111f24,0x00);//Different with EDEN!
1073 HAL_DMD_RIU_WriteByte(0x111f1E,0x00);//Different with EDEN!
1074 HAL_DMD_RIU_WriteByte(0x111f09,0x00);//Different with EDEN!
1075
1076 u8Val = HAL_DMD_RIU_ReadByte(0x000e13);
1077 HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1078
1079 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1080 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1081 }
1082 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1083 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1084 {
1085 MS_U8 u8Val = 0;
1086
1087 printf("--------------DMD_ATSC_CHIP_EINSTEIN--------------\n");
1088
1089 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1090 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1091
1092 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1093 HAL_DMD_RIU_WriteByte(0x10331e, 0x10); //Denny: change 0x10!! 108M
1094 HAL_DMD_RIU_WriteByte(0x103301, 0x05); //addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1095 HAL_DMD_RIU_WriteByte(0x103300, 0x11); //addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1096 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1097 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1098 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1099 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1100
1101 HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1102 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1103 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1104 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1105 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1106 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1107 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1108 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1109 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1110
1111 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1112 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1113 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1114 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1115
1116 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1117 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1118 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1119 HAL_DMD_RIU_WriteByte(0x111f12, 0x08); //0406 update 0->8
1120 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1121 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1122
1123 HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1124 HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1125 HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1126 HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1127 HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1128 HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1129 HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1130 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1131 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1132 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1133
1134 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1135 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1136
1137 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1138 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1139 }
1140 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1141 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1142 {
1143 MS_U8 u8Val = 0;
1144
1145 printf("--------------DMD_ATSC_CHIP_EINSTEIN3--------------\n");
1146
1147 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1148 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1149
1150 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1151 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);// Denny: change 0x10!! 108M
1152 HAL_DMD_RIU_WriteByte(0x103301, 0x05);//addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1153 HAL_DMD_RIU_WriteByte(0x103300, 0x11);//addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1154 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1155 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1156 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1157 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1158
1159 HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1160 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1161 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1162 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1163 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1164 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1165 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1166 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1167 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1168
1169 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1170 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1171 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1172 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1173
1174 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1175 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1176 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1177 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);//0406 update 0->8
1178 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1179 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1180
1181 HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1182 HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1183 HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1184 HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1185 HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1186 HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1187 HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1188 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1189 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1190 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1191
1192 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1193 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1194
1195 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1196 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1197 }
1198 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MONACO)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1199 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1200 {
1201 MS_U8 u8Val = 0;
1202
1203 printf("--------------DMD_ATSC_CHIP_MONACO--------------\n");
1204
1205 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1206 u8Val &= (~0x03);
1207 HAL_DMD_RIU_WriteByte(0x101e39, u8Val);
1208 // DMDMCU 108M
1209 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1210 // Set parallel TS clock
1211 // [11] : reg_ckg_demod_test_in_en = 0
1212 // 0: select internal ADC CLK
1213 // 1: select external test-in clock
1214 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1215 // 0: select gated clock
1216 // 1: select free-run clock
1217 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1218 // 0: normal phase to pad
1219 // 1: invert phase to pad
1220 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1221 // 0: select clk_dmplldiv5
1222 // 1: select clk_dmplldiv3
1223 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1224 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1225 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1226 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1227 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1228 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1229 // Enable ATSC, DVBTC TS clock
1230 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1231 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1232 // Enable ADC clock in clkgen_demod
1233 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1234 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1235 // Enable VIF DAC clock in clkgen_demod
1236 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1237 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1238 // Enable ATSC clock
1239 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1240 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1241 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1242 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1243 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1244 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1245 // Enable clk_atsc_adcd_sync = 25.41
1246 // [3:0]: reg_ckg_atsc_adcd_sync
1247 // [0] : disable clock
1248 // [1] : invert clock
1249 // [3:2]: Select clock source
1250 // 00: clk_dmdadc_sync
1251 // 01: clk_atsc50_p
1252 // ^^^^^^^^^^^^
1253 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1254 // else => clk_dmplldiv17(50.82 MHz)
1255 // 10: clk_atsc25_p
1256 // ^^^^^^^^^^^^
1257 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1258 // else => clk_dmplldiv17_div2(25.41 MHz)
1259 // 11: 1'b0
1260 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1261 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1262 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1263 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1264 // Enable DVBT inner clock
1265 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1266 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1267 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1268 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1269 // Enable DVBT outer clock
1270 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1271 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1272 // Enable DVBC outer clock
1273 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1274 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1275 // Enable SRAM clock
1276 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1277 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1278 // Enable ISDBT SRAM share clock and symbol rate clock
1279 HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1280 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1281 // select clock
1282 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1283 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1284 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1285 // [0] : disable clock
1286 // [1] : invert clock
1287 // [3:2]: Select clock source
1288 // 00: dtmb_clk288_buf(256 MHz)
1289 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1290 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1291 // 11: 1'b0
1292 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1293 // ^^^^^^^^^^
1294 // [0] : disable clock
1295 // [1] : invert clock
1296 // [3:2]: Select clock source
1297 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1298 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1299 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1300 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1301 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1302 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1303 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1304 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1305 // ^^^^^^^^^^
1306 // [0] : disable clock
1307 // [1] : invert clock
1308 // [3:2]: Select clock source
1309 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1310 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1311 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1312 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1313 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1314 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1315 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1316 // [15:12]: reg_ckg_dtmb_sram_dump
1317 // [0] : disable clock
1318 // [1] : invert clock
1319 // [3:2]: Select clock source
1320 // 00: dtmb_clk18_buf(16 MHz)
1321 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1322 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1323 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1324 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1325 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1326 HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1327 HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1328 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1329 // ^^^^^^^^^^^^^^^^^^
1330 // [0] : disable clock
1331 // [1] : invert clock
1332 // [4:2]: Select clock source
1333 // 000: adc_clk_buf
1334 // 001: clk_atsc25_p
1335 // ^^^^^^^^^^^^
1336 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1337 // else => clk_dmplldiv17_div2(25.41 MHz)
1338 // 010: clk_atsc_eq25_p
1339 // ^^^^^^^^^^^^^^^
1340 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1341 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1342 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1343 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1344 // 2'b11: 1'b0
1345 // endcase
1346 // 011: dtmb_clk72_buf(72 MHz)
1347 // 100: dtmb_clk18_buf(18 MHz)
1348 // 101: 1'b0
1349 // 110: 1'b0
1350 // 111: 1'b0
1351 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1352 // ^^^^^^^^^^^^^^^^^^^^
1353 // [0] : disable clock
1354 // [1] : invert clock
1355 // [4:2]: Select clock source
1356 // 000: clk_adc_div2_buf
1357 // 001: clk_frontend_d2_p0
1358 // ^^^^^^^^^^^^^^^^^^
1359 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1360 // else => clk_dmplldiv17_div4(12.705 MHz)
1361 // 010: clk_atsc_eq25_div2_p
1362 // ^^^^^^^^^^^^^^^^^^^^
1363 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1364 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1365 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1366 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1367 // 2'b11: 1'b0
1368 // endcase
1369 // 011: dtmb_clk36_buf(36 MHz)
1370 // 100: dtmb_clk9_buf(9 MHz)
1371 // 101: 1'b0
1372 // 110: 1'b0
1373 // 111: 1'b0
1374 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1375 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1376 HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1377 HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1378
1379 //Enable SRAM power saving
1380 HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1381 HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1382
1383 u8Val |= 0x03;
1384 HAL_DMD_RIU_WriteByte(0x101e39, u8Val);
1385 }
1386 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDISON)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1387 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1388 {
1389 MS_U8 u8Val = 0x00;
1390
1391 printf("--------------DMD_ATSC_CHIP_EDISON--------------\n");
1392
1393 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1394 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1395
1396 HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1397 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1398 HAL_DMD_RIU_WriteByte(0x103301,0x06);//Different with EDEN!
1399 HAL_DMD_RIU_WriteByte(0x103300,0x0B);//Different with EDEN!
1400 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1401 HAL_DMD_RIU_WriteByte(0x103308,0x00);
1402 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1403 HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1404
1405 HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1406 HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1407 HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1408 HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1409 HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1410 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1411 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1412 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1413
1414 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1415 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1416 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1417 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1418
1419 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1420 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1421 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1422 HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1423 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1424 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1425 HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1426 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1427
1428 HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1429 HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1430
1431 HAL_DMD_RIU_WriteByte(0x111F1E,0x00);
1432 HAL_DMD_RIU_WriteByte(0x111F09,0x00);
1433
1434 u8Val = HAL_DMD_RIU_ReadByte(0x000e13);
1435 HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1436
1437 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1438 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1439 }
1440 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EIFFEL)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1441 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1442 {
1443 MS_U8 u8Val = 0x00;
1444
1445 printf("--------------DMD_ATSC_CHIP_EIFFEL--------------\n");
1446
1447 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1448 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1449
1450 HAL_DMD_RIU_WriteByte(0x101e39 ,0x00);
1451 HAL_DMD_RIU_WriteByte(0x10331f ,0x00);
1452 HAL_DMD_RIU_WriteByte(0x10331e ,0x10);
1453 HAL_DMD_RIU_WriteByte(0x103301 ,0x05);
1454 HAL_DMD_RIU_WriteByte(0x103300 ,0x11);
1455 HAL_DMD_RIU_WriteByte(0x103309 ,0x00);
1456 HAL_DMD_RIU_WriteByte(0x103308 ,0x00);
1457 HAL_DMD_RIU_WriteByte(0x103315 ,0x00);
1458 HAL_DMD_RIU_WriteByte(0x103314 ,0x00);
1459 HAL_DMD_RIU_WriteByte(0x111f28 ,0x00);
1460 // HAL_DMD_RIU_WriteByte(0x112028 ,0x03);
1461 HAL_DMD_RIU_WriteByte(0x111f03 ,0x00);
1462 HAL_DMD_RIU_WriteByte(0x111f02 ,0x00);
1463 HAL_DMD_RIU_WriteByte(0x111f05 ,0x00);
1464 HAL_DMD_RIU_WriteByte(0x111f04 ,0x00);
1465 HAL_DMD_RIU_WriteByte(0x111f07 ,0x00);
1466 HAL_DMD_RIU_WriteByte(0x111f06 ,0x00);
1467 HAL_DMD_RIU_WriteByte(0x111f0b ,0x00);
1468 HAL_DMD_RIU_WriteByte(0x111f0a ,0x08);
1469 HAL_DMD_RIU_WriteByte(0x111f0d ,0x00);
1470 HAL_DMD_RIU_WriteByte(0x111f0c ,0x00);
1471 HAL_DMD_RIU_WriteByte(0x111f0f ,0x00);
1472 HAL_DMD_RIU_WriteByte(0x111f0e ,0x00);
1473 HAL_DMD_RIU_WriteByte(0x111f11 ,0x00);
1474 HAL_DMD_RIU_WriteByte(0x111f10 ,0x00);
1475 HAL_DMD_RIU_WriteByte(0x111f13 ,0x00);
1476 HAL_DMD_RIU_WriteByte(0x111f12 ,0x08);
1477 HAL_DMD_RIU_WriteByte(0x111f19 ,0x00);
1478 HAL_DMD_RIU_WriteByte(0x111f18 ,0x00);
1479 HAL_DMD_RIU_WriteByte(0x111f23 ,0x00);
1480 HAL_DMD_RIU_WriteByte(0x111f22 ,0x00);
1481
1482 u8Val = HAL_DMD_RIU_ReadByte(0x000e61);
1483 HAL_DMD_RIU_WriteByte(0x000e61, u8Val&0xFE);
1484
1485 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1486 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1487 }
1488 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MIAMI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1489 stativ void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1490 {
1491 MS_U8 u8Val = 0;
1492
1493 printf("--------------DMD_ATSC_CHIP_MIAMI--------------\n");
1494
1495 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1496 u8Val &= (~0x03);
1497 HAL_DMD_RIU_WriteByte(0x101e39, u8Val);
1498 // DMDMCU 108M
1499 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1500 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1501 // Set parallel TS clock
1502 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1503 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1504 // Enable ATSC, DVBTC TS clock
1505 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1506 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1507 // Enable ADC clock in clkgen_demod
1508 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1509 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1510 // Select MPLLDIV17
1511 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1512 // Enable ATSC clock
1513 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1514 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1515 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1516 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1517 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1518 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1519 // enable clk_atsc_adcd_sync
1520 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1521 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1522 // Enable DVBT inner clock
1523 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1524 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1525 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1526 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1527 // Enable DVBT outer clock
1528 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1529 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1530 // Enable DVBC outer clock
1531 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1532 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1533 // Enable SRAM clock
1534 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1535 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1536 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1537 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1538 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1539 // select clock
1540 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1541 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1542 // enable CCI LMS clock
1543 HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1544 HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1545
1546 u8Val |= 0x03;
1547 HAL_DMD_RIU_WriteByte(0x101e39, u8Val);
1548 }
1549 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KERES)
HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1550 static void HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1551 {
1552 MS_U8 u8Val=0x00;
1553 u8Val=HAL_DMD_RIU_ReadByte(0x101e39);//MDrv_ReadByte(0x101e39);
1554 printf("--------------DMD_ATSC_CHIP_KERES--------------\n");
1555 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1556 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
1557 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1558 HAL_DMD_RIU_WriteByte(0x103301,0x07);
1559 HAL_DMD_RIU_WriteByte(0x103300,0x11);
1560 HAL_DMD_RIU_WriteByte(0x103309,0x00);
1561 HAL_DMD_RIU_WriteByte(0x103315,0x00);
1562 HAL_DMD_RIU_WriteByte(0x103314,0x00);
1563
1564 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1565 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1566 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1567 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1568 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1569 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1570 HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1571 HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1572 HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1573 HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1574 HAL_DMD_RIU_WriteByte(0x111f2b,0x00); //enable clk_rs
1575 HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1576 //HAL_DMD_RIU_WriteByte(0x000e13,0x01); // No need, it cause uart issue.
1577 HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1578
1579 HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1580 HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1581
1582 u8Val=HAL_DMD_RIU_ReadByte(0x101e39);
1583 HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1584 }
1585 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUJI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1586 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1587 {
1588 MS_U8 u8Val = 0;
1589
1590 printf("--------------DMD_ATSC_CHIP_MUJI--------------\n");
1591
1592 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1593 u8Val &= (~0x03);
1594 HAL_DMD_RIU_WriteByte(0x101e39, u8Val);
1595 // DMDMCU 108M
1596 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1597 // Set parallel TS clock
1598 // [11] : reg_ckg_demod_test_in_en = 0
1599 // 0: select internal ADC CLK
1600 // 1: select external test-in clock
1601 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1602 // 0: select gated clock
1603 // 1: select free-run clock
1604 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1605 // 0: normal phase to pad
1606 // 1: invert phase to pad
1607 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1608 // 0: select clk_dmplldiv5
1609 // 1: select clk_dmplldiv3
1610 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1611 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1612 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1613 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1614 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1615 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1616 // Enable ATSC, DVBTC TS clock
1617 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1618 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1619 // Enable ADC clock in clkgen_demod
1620 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1621 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1622 // Reset TS divider
1623 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1624 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1625 // Enable VIF DAC clock in clkgen_demod
1626 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1627 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1628 // Enable ATSC clock
1629 HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1630 HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1631 HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1632 HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1633 HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1634 HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1635 // Enable clk_atsc_adcd_sync = 25.41
1636 // [3:0]: reg_ckg_atsc_adcd_sync
1637 // [0] : disable clock
1638 // [1] : invert clock
1639 // [3:2]: Select clock source
1640 // 00: clk_dmdadc_sync
1641 // 01: clk_atsc50_p
1642 // ^^^^^^^^^^^^
1643 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1644 // else => clk_dmplldiv17(50.82 MHz)
1645 // 10: clk_atsc25_p
1646 // ^^^^^^^^^^^^
1647 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1648 // else => clk_dmplldiv17_div2(25.41 MHz)
1649 // 11: 1'b0
1650 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1651 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1652 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1653 HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1654 // Enable DVBT inner clock
1655 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1656 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1657 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1658 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1659 // Enable DVBT outer clock
1660 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1661 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1662 // Enable DVBC outer clock
1663 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1664 HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1665 // Enable SRAM clock
1666 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1667 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1668 // Enable ISDBT SRAM share clock and symbol rate clock
1669 HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1670 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1671 // select clock
1672 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1673 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1674 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1675 // [0] : disable clock
1676 // [1] : invert clock
1677 // [3:2]: Select clock source
1678 // 00: dtmb_clk288_buf(256 MHz)
1679 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1680 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1681 // 11: 1'b0
1682 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1683 // ^^^^^^^^^^
1684 // [0] : disable clock
1685 // [1] : invert clock
1686 // [3:2]: Select clock source
1687 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1688 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1689 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1690 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1691 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1692 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1693 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1694 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1695 // ^^^^^^^^^^
1696 // [0] : disable clock
1697 // [1] : invert clock
1698 // [3:2]: Select clock source
1699 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1700 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1701 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1702 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1703 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1704 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1705 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1706 // [15:12]: reg_ckg_dtmb_sram_dump
1707 // [0] : disable clock
1708 // [1] : invert clock
1709 // [3:2]: Select clock source
1710 // 00: dtmb_clk18_buf(16 MHz)
1711 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1712 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1713 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1714 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1715 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1716 HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1717 HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1718 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1719 // ^^^^^^^^^^^^^^^^^^
1720 // [0] : disable clock
1721 // [1] : invert clock
1722 // [4:2]: Select clock source
1723 // 000: adc_clk_buf
1724 // 001: clk_atsc25_p
1725 // ^^^^^^^^^^^^
1726 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1727 // else => clk_dmplldiv17_div2(25.41 MHz)
1728 // 010: clk_atsc_eq25_p
1729 // ^^^^^^^^^^^^^^^
1730 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1731 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1732 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1733 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1734 // 2'b11: 1'b0
1735 // endcase
1736 // 011: dtmb_clk72_buf(72 MHz)
1737 // 100: dtmb_clk18_buf(18 MHz)
1738 // 101: 1'b0
1739 // 110: 1'b0
1740 // 111: 1'b0
1741 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1742 // ^^^^^^^^^^^^^^^^^^^^
1743 // [0] : disable clock
1744 // [1] : invert clock
1745 // [4:2]: Select clock source
1746 // 000: clk_adc_div2_buf
1747 // 001: clk_frontend_d2_p0
1748 // ^^^^^^^^^^^^^^^^^^
1749 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1750 // else => clk_dmplldiv17_div4(12.705 MHz)
1751 // 010: clk_atsc_eq25_div2_p
1752 // ^^^^^^^^^^^^^^^^^^^^
1753 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1754 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1755 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1756 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1757 // 2'b11: 1'b0
1758 // endcase
1759 // 011: dtmb_clk36_buf(36 MHz)
1760 // 100: dtmb_clk9_buf(9 MHz)
1761 // 101: 1'b0
1762 // 110: 1'b0
1763 // 111: 1'b0
1764 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1765 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1766 HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1767 HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1768
1769 // Muji
1770 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
1771 // [0] : disable clock
1772 // [1] : invert clock
1773 // [3:2]: Select clock source
1774 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
1775 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
1776 // sel[1]= (~reg_demod_isdbt_on)
1777 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1778 // 00: isdbt_clk6_lat(6 MHz)
1779 // 01: isdbt_clk8_lat(8 MHz)
1780 // 10: clk_dmplldiv10_div2(43.2 MHz)
1781 // 11: 1'b0
1782 // [6:4] : reg_ckg_miu_dvbtc_outer2x
1783 // [0] : disable clock
1784 // [1] : invert clock
1785 // [2] : Select clock source
1786 // 0: clk_miu_p
1787 // 1: clk_dmplldiv10(86.4 MHz)
1788 // [12:8] : reg_ckg_dvbtc_rs
1789 // [0] : disable clock
1790 // [1] : invert clock
1791 // [4:2]: Select clock source
1792 // 000: clk_dmplldiv10(86.4 MHz)
1793 // 001: clk_dmplldiv10_div2(43.2 MHz)
1794 // 010: clk_atsc50_p
1795 // ^^^^^^^^^^^^
1796 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1797 // else => clk_dmplldiv17(50.82 MHz)
1798 // 011: clk_dvbtc_rs_216_buf(216 MHz)
1799 // 100: clk_dvbtc_rs_172_buf(172 MHz)
1800 // 101: clk_dvbtc_rs_144_buf(144 MHz)
1801 // 110: 1'b0
1802 // 111: 1'b0
1803 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1804 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1805 HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
1806
1807 //Enable SRAM power saving
1808 HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1809 HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1810
1811 u8Val |= 0x03;
1812 HAL_DMD_RIU_WriteByte(0x101e39, u8Val);
1813 }
1814 #else
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1815 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1816 {
1817 printf("--------------DMD_ATSC_CHIP_NONE--------------\n");
1818 }
1819 #endif
1820
_HAL_INTERN_ATSC_Download(void)1821 static MS_BOOL _HAL_INTERN_ATSC_Download(void)
1822 {
1823 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
1824
1825 MS_U8 udata = 0x00;
1826 MS_U16 i=0;
1827 MS_U16 fail_cnt=0;
1828 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
1829 MS_U8 u8TmpData;
1830 MS_U16 u16AddressOffset;
1831 #endif
1832
1833 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
1834 if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x08) HAL_PWS_Stop_VDMCU();
1835 else
1836 {
1837 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1838 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1839 MsOS_DelayTask(20);
1840 return TRUE;
1841 }
1842 #else
1843 if (pRes->sDMD_ATSC_PriData.bDownloaded)
1844 {
1845 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1846 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1847 MsOS_DelayTask(20);
1848 return TRUE;
1849 }
1850 #endif
1851
1852 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1853 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1854
1855 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1856
1857 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1858 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1859 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1860 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1861
1862 //// Load code thru VDMCU_IF ////
1863 HAL_INTERN_ATSC_DBINFO(printf(">Load Code...\n"));
1864
1865 for (i = 0; i < u16Lib_size; i++)
1866 {
1867 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, INTERN_ATSC_table[i]); // write data to VD MCU 51 code sram
1868 }
1869
1870 //// Content verification ////
1871 HAL_INTERN_ATSC_DBINFO(printf(">Verify Code...\n"));
1872
1873 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1874 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1875
1876 for (i = 0; i < u16Lib_size; i++)
1877 {
1878 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1879
1880 if (udata != INTERN_ATSC_table[i])
1881 {
1882 HAL_INTERN_ATSC_DBINFO(printf(">fail add = 0x%x\n", i));
1883 HAL_INTERN_ATSC_DBINFO(printf(">code = 0x%x\n", INTERN_ATSC_table[i]));
1884 HAL_INTERN_ATSC_DBINFO(printf(">data = 0x%x\n", udata));
1885
1886 if (fail_cnt++ > 10)
1887 {
1888 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode fail!"));
1889 return FALSE;
1890 }
1891 }
1892 }
1893
1894 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
1895 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
1896 _initTable();
1897 #endif
1898
1899 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x80); // sram address low byte
1900 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9 || DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
1901 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x6B); // sram address high byte
1902 #else
1903 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x5B); // sram address high byte
1904 #endif
1905
1906 for (i = 0; i < sizeof(Demod_Flow_register); i++)
1907 {
1908 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, Demod_Flow_register[i]);
1909 }
1910 #else // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
1911 u16AddressOffset = (INTERN_ATSC_table[0x400] << 8)|INTERN_ATSC_table[0x401];
1912
1913 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1914 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1915
1916 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16IF_KHZ;
1917 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1918 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16IF_KHZ >> 8);
1919 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1920 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.bIQSwap;
1921 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1922 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE;
1923 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1924 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE >> 8);
1925 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1926 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u8IS_DUAL;
1927 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1928 u8TmpData = (MS_U8)u8DMD_ATSC_DMD_ID;
1929 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1930 #endif // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
1931
1932 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1933 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1934
1935 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1936
1937 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1938 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1939
1940 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
1941 HAL_DMD_RIU_WriteByte(0x101E3E, 0x08); // ATSC = BIT3 -> 0x08
1942 HAL_DMD_RIU_WriteByte(0x11051C, 0x00);
1943 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
1944 HAL_DMD_RIU_WriteByte(0x11261C, 0x00);
1945 pRes->sDMD_ATSC_PriData.bDownloaded = true;
1946 #else
1947 pRes->sDMD_ATSC_PriData.bDownloaded = true;
1948 #endif
1949
1950 MsOS_DelayTask(20);
1951
1952 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode done.\n"));
1953
1954 return TRUE;
1955 }
1956
_HAL_INTERN_ATSC_FWVERSION(void)1957 static void _HAL_INTERN_ATSC_FWVERSION(void)
1958 {
1959 MS_U8 data1,data2,data3;
1960
1961 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
1962 _MBX_ReadReg(0x20C4, &data1);
1963 _MBX_ReadReg(0x20C5, &data2);
1964 _MBX_ReadReg(0x20C6, &data3);
1965 #else
1966 _MBX_ReadReg(0x20C4, &data1);
1967 _MBX_ReadReg(0x20CF, &data2);
1968 _MBX_ReadReg(0x20D0, &data3);
1969 #endif
1970
1971 HAL_INTERN_ATSC_DBINFO(printf("INTERN_ATSC_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
1972 }
1973
_HAL_INTERN_ATSC_Exit(void)1974 static MS_BOOL _HAL_INTERN_ATSC_Exit(void)
1975 {
1976 MS_U8 u8CheckCount = 0;
1977
1978 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1979
1980 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1981 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1982
1983 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1984 {
1985 MsOS_DelayTaskUs(10);
1986
1987 if (u8CheckCount++ == 0xFF)
1988 {
1989 printf(">> ATSC Exit Fail!\n");
1990 return FALSE;
1991 }
1992 }
1993
1994 printf(">> ATSC Exit Ok!\n");
1995
1996 return TRUE;
1997 }
1998
_HAL_INTERN_ATSC_SoftReset(void)1999 static MS_BOOL _HAL_INTERN_ATSC_SoftReset(void)
2000 {
2001 MS_U8 u8Data = 0xFF;
2002
2003 //Reset FSM
2004 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
2005
2006 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2007 while (u8Data != 0x02)
2008 #else
2009 while (u8Data != 0x00)
2010 #endif
2011 {
2012 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
2013 }
2014
2015 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2016 //Execute demod top reset
2017 _MBX_ReadReg(0x2002, &u8Data);
2018 _MBX_WriteReg(0x2002, (u8Data|0x10));
2019 return _MBX_WriteReg(0x2002, (u8Data&(~0x10)));
2020 #else
2021 return TRUE;
2022 #endif
2023 }
2024
_HAL_INTERN_ATSC_SetVsbMode(void)2025 static MS_BOOL _HAL_INTERN_ATSC_SetVsbMode(void)
2026 {
2027 return _MBX_WriteReg(0x20C0, 0x08);
2028 }
2029
_HAL_INTERN_ATSC_Set64QamMode(void)2030 static MS_BOOL _HAL_INTERN_ATSC_Set64QamMode(void)
2031 {
2032 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2033 if (_MBX_WriteReg(0x20C3, 0x00)==FALSE) return FALSE;
2034 #endif
2035 return _MBX_WriteReg(0x20C0, 0x04);
2036 }
2037
_HAL_INTERN_ATSC_Set256QamMode(void)2038 static MS_BOOL _HAL_INTERN_ATSC_Set256QamMode(void)
2039 {
2040 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2041 if (_MBX_WriteReg(0x20C3, 0x01)==FALSE) return FALSE;
2042 #endif
2043 return _MBX_WriteReg(0x20C0, 0x04);
2044 }
2045
_HAL_INTERN_ATSC_SetModeClean(void)2046 static MS_BOOL _HAL_INTERN_ATSC_SetModeClean(void)
2047 {
2048 return _MBX_WriteReg(0x20C0, 0x00);
2049 }
2050
_HAL_INTERN_ATSC_Check8VSB64_256QAM(void)2051 static DMD_ATSC_DEMOD_TYPE _HAL_INTERN_ATSC_Check8VSB64_256QAM(void)
2052 {
2053 MS_U8 mode = 0;
2054
2055 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2056 _MBX_ReadReg(0x2A02, &mode); //EQ mode check
2057
2058 mode &= 0x07;
2059
2060 if (mode == QAM16_J83ABC) return DMD_ATSC_DEMOD_ATSC_16QAM;
2061 else if (mode == QAM32_J83ABC) return DMD_ATSC_DEMOD_ATSC_32QAM;
2062 else if (mode == QAM64_J83ABC) return DMD_ATSC_DEMOD_ATSC_64QAM;
2063 else if (mode == QAM128_J83ABC) return DMD_ATSC_DEMOD_ATSC_128QAM;
2064 else if (mode == QAM256_J83ABC) return DMD_ATSC_DEMOD_ATSC_256QAM;
2065 else return DMD_ATSC_DEMOD_ATSC_256QAM;
2066 #else
2067 _MBX_ReadReg(0x2900, &mode); //mode check
2068
2069 if ((mode&VSB_ATSC) == VSB_ATSC) return DMD_ATSC_DEMOD_ATSC_VSB;
2070 else if ((mode & QAM256_ATSC) == QAM256_ATSC) return DMD_ATSC_DEMOD_ATSC_256QAM;
2071 else return DMD_ATSC_DEMOD_ATSC_64QAM;
2072 #endif
2073 }
2074
_HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)2075 static MS_BOOL _HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)
2076 {
2077 MS_U8 data1 = 0;
2078
2079 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2080 _MBX_ReadReg(0x271D, &data1); //AGC_LOCK
2081 #else
2082 _MBX_ReadReg(0x293A, &data1); //AGC_LOCK
2083 #endif
2084
2085 if(data1&0x01)
2086 {
2087 return TRUE;
2088 }
2089 else
2090 {
2091 return FALSE;
2092 }
2093 }
2094
_HAL_INTERN_ATSC_Vsb_PreLock(void)2095 static MS_BOOL _HAL_INTERN_ATSC_Vsb_PreLock(void)
2096 {
2097 MS_U8 data1 = 0;
2098 MS_U8 data2 = 0;
2099 MS_U16 checkValue;
2100
2101 _MBX_ReadReg(0x20C2, &data1); //<0>TR_LOCK, <1>PTK_LOCK
2102
2103 if ((data1&0x02) == 0x02)
2104 {
2105 _MBX_ReadReg(0x2AEA, &data1);
2106 _MBX_ReadReg(0x2AEB, &data2);
2107
2108 checkValue = data1 << 8;
2109 checkValue |= data2;
2110
2111 HAL_INTERN_ATSC_DBINFO(printf("Internal Pre Locking time :[%d]ms\n",checkValue));
2112
2113 return TRUE;
2114 }
2115 else
2116 {
2117 HAL_INTERN_ATSC_DBINFO(printf("\nPreLock - FALSE"));
2118
2119 return FALSE;
2120 }
2121 }
2122
_HAL_INTERN_ATSC_Vsb_FSync_Lock(void)2123 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FSync_Lock(void)
2124 {
2125 MS_U8 data1 = 0;
2126 MS_U8 data2 = 0;
2127 MS_U16 checkValue;
2128
2129 _MBX_ReadReg(0x2A24, &data1); //<4>1:Field Sync lock = Fsync lock
2130
2131 if ((data1&0x10) == 0x10)
2132 {
2133 _MBX_ReadReg(0x2AEE, &data1);
2134 _MBX_ReadReg(0x2AEF, &data2);
2135
2136 checkValue = data1 << 8;
2137 checkValue |= data2;
2138
2139 HAL_INTERN_ATSC_DBINFO(printf("Internal Fsync Locking time :[%d]ms\n",checkValue));
2140
2141 return TRUE;
2142 }
2143 else
2144 {
2145 HAL_INTERN_ATSC_DBINFO(printf("\nFsync Lock - FALSE"));
2146
2147 return FALSE;
2148 }
2149 }
2150
_HAL_INTERN_ATSC_Vsb_CE_Lock(void)2151 static MS_BOOL _HAL_INTERN_ATSC_Vsb_CE_Lock(void)
2152 {
2153 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2154 return TRUE;
2155 #else
2156 MS_U8 data1 = 0;
2157
2158 _MBX_ReadReg(0x20C2, &data1); //<4>1:CE Search Fail
2159
2160 if((data1&0x10) == 0)
2161 {
2162 HAL_INTERN_ATSC_DBINFO(printf("\nCE Lock"));
2163 return TRUE;
2164 }
2165 else
2166 {
2167 HAL_INTERN_ATSC_DBINFO(printf("\nCE unLock"));
2168 return FALSE;
2169 }
2170 #endif
2171 }
2172
_HAL_INTERN_ATSC_Vsb_FEC_Lock(void)2173 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FEC_Lock(void)
2174 {
2175 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0;
2176 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2177 MS_U8 data6 =0, data7 = 0;
2178 #endif
2179
2180 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2181 _MBX_ReadReg(0x20C1, &data1);
2182 _MBX_ReadReg(0x2C17, &data2);//AD_NOISE_PWR_TRAIN1
2183 _MBX_ReadReg(0x20C2, &data3);//<0>TR_LOCK, <1>PTK_LOCK
2184 _MBX_ReadReg(0x2B01, &data4);//FEC_EN_CTL
2185 _MBX_ReadReg(0x2D67, &data5);//addy
2186 _MBX_ReadReg(0x1F01, &data6);
2187 _MBX_ReadReg(0x1F40, &data7);
2188
2189 //Driver update 0426 :suggestion for field claim
2190 if (data1==INTERN_ATSC_OUTER_STATE &&
2191 ((data2<=INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
2192 ((data3&0x02)==0x02) &&
2193 ((data4&INTERN_ATSC_FEC_ENABLE)==INTERN_ATSC_FEC_ENABLE) &&
2194 ((data6&0x10) == 0x10) && ((data7&0x01) == 0x01))
2195 {
2196 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
2197 return TRUE;
2198 }
2199 else
2200 {
2201 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
2202 return FALSE;
2203 }
2204 #else
2205 _MBX_ReadReg(0x20C1, &data1);
2206 _MBX_ReadReg(0x2C17, &data2); //AD_NOISE_PWR_TRAIN1 (DFS)
2207 _MBX_ReadReg(0x20C2, &data3); //<0>TR_LOCK, <1>PTK_LOCK
2208 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
2209 _MBX_ReadReg(0x2C15, &data5); //AD_NOISE_PWR_TRAIN1 (DSS)
2210
2211 if ((data1 == INTERN_ATSC_OUTER_STATE) &&
2212 ((data2 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
2213 ((data3&0x02)==0x02) &&
2214 ((data4&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE))
2215 {
2216 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
2217 return TRUE;
2218 }
2219 else
2220 {
2221 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
2222 return FALSE;
2223 }
2224 #endif
2225 }
2226
_HAL_INTERN_ATSC_QAM_PreLock(void)2227 static MS_BOOL _HAL_INTERN_ATSC_QAM_PreLock(void)
2228 {
2229 MS_U8 data1 = 0;
2230
2231 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2232 _MBX_ReadReg(0x2950, &data1); //TR_LOCK
2233 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2234 _MBX_ReadReg(0x2615, &data1); //TR_LOCK
2235 #else
2236 _MBX_ReadReg(0x2921, &data1); //TR_LOCK
2237 #endif
2238
2239 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2240 if (data1&0x01)
2241 {
2242 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
2243 return TRUE;
2244 }
2245 else
2246 {
2247 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
2248 return FALSE;
2249 }
2250 #else
2251 if((data1&0x10) == 0x10)
2252 {
2253 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
2254 return TRUE;
2255 }
2256 else
2257 {
2258 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
2259 return FALSE;
2260 }
2261 #endif
2262 }
2263
_HAL_INTERN_ATSC_QAM_Main_Lock(void)2264 static MS_BOOL _HAL_INTERN_ATSC_QAM_Main_Lock(void)
2265 {
2266 #if DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1
2267 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0, data6=0;
2268 #else
2269 MS_U8 data1=0, data4=0, data5=0, data6=0;
2270 #endif
2271
2272 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2273 _MBX_ReadReg(0x20C1, &data1);
2274 _MBX_ReadReg(0x2B18, &data2); //boundary detected
2275 _MBX_ReadReg(0x2950, &data3); //TR_LOCK
2276 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
2277 _MBX_ReadReg(0x2101, &data5); //RS_backend
2278 _MBX_ReadReg(0x2140, &data6); //RS_backend
2279
2280 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
2281 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x01) ==0x01 &&
2282 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
2283 {
2284 return TRUE;
2285 }
2286 else
2287 {
2288 return FALSE;
2289 }
2290 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2291 _MBX_ReadReg(0x20C1, &data1);
2292 _MBX_ReadReg(0x2B18, &data2); //boundary detected
2293 _MBX_ReadReg(0x2615, &data3); //TR_LOCK
2294 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
2295 _MBX_ReadReg(0x1F01, &data5);
2296 _MBX_ReadReg(0x1F40, &data6);
2297
2298 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
2299 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x10)==0x10 &&
2300 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
2301 {
2302 return TRUE;
2303 }
2304 else
2305 {
2306 return FALSE;
2307 }
2308 #else
2309 _MBX_ReadReg(0x2B18, &data4); //boundary detected
2310 _MBX_ReadReg(0x2B01, &data5); //FEC_EN_CTL
2311 _MBX_ReadReg(0x2921, &data6); //TR_LOCK
2312 _MBX_ReadReg(0x20C1, &data1);
2313
2314 if (data1==INTERN_ATSC_OUTER_STATE && (data4&0x01) == 0x01 &&
2315 (data5&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE &&
2316 (data6&0x10) == 0x10)
2317 {
2318 return TRUE;
2319 }
2320 else
2321 {
2322 return FALSE;
2323 }
2324 #endif
2325 }
2326
_HAL_INTERN_ATSC_ReadIFAGC(void)2327 static MS_U8 _HAL_INTERN_ATSC_ReadIFAGC(void)
2328 {
2329 MS_U16 data = 0;
2330
2331 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2332 _MBX_ReadReg(0x2726, ((MS_U8*)(&data))+1); //reg_frontend
2333 _MBX_ReadReg(0x2727, (MS_U8*)(&data));
2334 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2335 _MBX_ReadReg(0x2944, ((MS_U8*)(&data))+1);
2336 _MBX_ReadReg(0x2945, (MS_U8*)(&data));
2337 #endif
2338
2339 return data;
2340 }
2341
_HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION * pstatus)2342 static void _HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION* pstatus)
2343 {
2344 DMD_ATSC_DEMOD_TYPE eMode;
2345 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2346 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
2347 static MS_U8 u8NoisePowerL_Last = 0xff;
2348 #else
2349 MS_U8 u8NoisePowerH=0;
2350 #endif
2351 static MS_U8 u8NoisePowerH_Last = 0xff;
2352
2353 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
2354
2355 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2356 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
2357 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
2358 #else
2359 _MBX_ReadReg(0x2C15, &u8NoisePowerH);
2360 #endif
2361
2362 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
2363 {
2364 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) u8NoisePowerH=0xFF;
2365 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
2366 u8NoisePowerH_Last = u8NoisePowerH;
2367 else u8NoisePowerH = u8NoisePowerH_Last;
2368
2369 if (u8NoisePowerH > 0xBE) //SNR<14.5
2370 *pstatus=DMD_ATSC_SIGNAL_NO;
2371 else if (u8NoisePowerH > 0x4D) //SNR<18.4
2372 *pstatus=DMD_ATSC_SIGNAL_WEAK;
2373 else if (u8NoisePowerH > 0x23) //SNR<21.8
2374 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
2375 else if (u8NoisePowerH > 0x0A) //SNR<26.9
2376 *pstatus=DMD_ATSC_SIGNAL_STRONG;
2377 else
2378 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
2379 }
2380 else //QAM MODE
2381 {
2382 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2383 if (!_HAL_INTERN_ATSC_QAM_Main_Lock() || u8NoisePowerH) u8NoisePowerL=0xFF;
2384 else if (abs(u8NoisePowerL_Last-u8NoisePowerL) > 5)
2385 u8NoisePowerL_Last = u8NoisePowerL;
2386 else u8NoisePowerL = u8NoisePowerL_Last;
2387
2388 //SNR=10*log10(65536/noisepower)
2389 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM)
2390 {
2391 if (u8NoisePowerL > 0x71) //SNR<27.6
2392 *pstatus=DMD_ATSC_SIGNAL_NO;
2393 else if (u8NoisePowerL > 0x31) //SNR<31.2
2394 *pstatus=DMD_ATSC_SIGNAL_WEAK;
2395 else if (u8NoisePowerL > 0x25) //SNR<32.4
2396 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
2397 else if (u8NoisePowerL > 0x17) //SNR<34.4
2398 *pstatus=DMD_ATSC_SIGNAL_STRONG;
2399 else
2400 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
2401 }
2402 else
2403 {
2404 if (u8NoisePowerL > 0x1D) //SNR<21.5
2405 *pstatus=DMD_ATSC_SIGNAL_NO;
2406 else if (u8NoisePowerL > 0x14) //SNR<25.4
2407 *pstatus=DMD_ATSC_SIGNAL_WEAK;
2408 else if (u8NoisePowerL > 0x0F) //SNR<27.8
2409 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
2410 else if (u8NoisePowerL > 0x0B) //SNR<31.4
2411 *pstatus=DMD_ATSC_SIGNAL_STRONG;
2412 else
2413 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
2414 }
2415 #else
2416 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) u8NoisePowerH=0xFF;
2417 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
2418 u8NoisePowerH_Last = u8NoisePowerH;
2419 else u8NoisePowerH = u8NoisePowerH_Last;
2420
2421 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//SNR=10*log10((2720<<10)/noisepower)
2422 {
2423 if (u8NoisePowerH > 0x13) //SNR<27.5
2424 *pstatus=DMD_ATSC_SIGNAL_NO;
2425 else if (u8NoisePowerH > 0x08) //SNR<31.2
2426 *pstatus=DMD_ATSC_SIGNAL_WEAK;
2427 else if (u8NoisePowerH > 0x06) //SNR<32.4
2428 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
2429 else if (u8NoisePowerH > 0x04) //SNR<34.2
2430 *pstatus=DMD_ATSC_SIGNAL_STRONG;
2431 else
2432 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
2433 }
2434 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
2435 {
2436 if (u8NoisePowerH > 0x4C) //SNR<21.5
2437 *pstatus=DMD_ATSC_SIGNAL_NO;
2438 else if (u8NoisePowerH > 0x1F) //SNR<25.4
2439 *pstatus=DMD_ATSC_SIGNAL_WEAK;
2440 else if (u8NoisePowerH > 0x11) //SNR<27.8
2441 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
2442 else if (u8NoisePowerH > 0x07) //SNR<31.4
2443 *pstatus=DMD_ATSC_SIGNAL_STRONG;
2444 else
2445 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
2446 }
2447 #endif
2448 }
2449 }
2450
_HAL_INTERN_ATSC_ReadSNRPercentage(void)2451 static MS_U8 _HAL_INTERN_ATSC_ReadSNRPercentage(void)
2452 {
2453 DMD_ATSC_DEMOD_TYPE eMode;
2454 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
2455 MS_U16 u16NoisePower;
2456
2457 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
2458
2459 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2460 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
2461 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
2462 #else
2463 _MBX_ReadReg(0x2C14, &u8NoisePowerL);
2464 _MBX_ReadReg(0x2C15, &u8NoisePowerH);
2465 #endif
2466
2467 u16NoisePower = (u8NoisePowerH<<8) | u8NoisePowerL;
2468
2469 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
2470 {
2471 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock())
2472 return 0;//SNR=0;
2473 else if (u16NoisePower<=0x008A)//SNR>=40dB
2474 return 100;//SNR=MAX_SNR;
2475 else if (u16NoisePower<=0x0097)//SNR>=39.6dB
2476 return 99;//
2477 else if (u16NoisePower<=0x00A5)//SNR>=39.2dB
2478 return 98;//
2479 else if (u16NoisePower<=0x00B5)//SNR>=38.8dB
2480 return 97;//
2481 else if (u16NoisePower<=0x00C7)//SNR>=38.4dB
2482 return 96;//
2483 else if (u16NoisePower<=0x00DA)//SNR>=38.0dB
2484 return 95;//
2485 else if (u16NoisePower<=0x00EF)//SNR>=37.6dB
2486 return 94;//
2487 else if (u16NoisePower<=0x0106)//SNR>=37.2dB
2488 return 93;//
2489 else if (u16NoisePower<=0x0120)//SNR>=36.8dB
2490 return 92;//
2491 else if (u16NoisePower<=0x013B)//SNR>=36.4dB
2492 return 91;//
2493 else if (u16NoisePower<=0x015A)//SNR>=36.0dB
2494 return 90;//
2495 else if (u16NoisePower<=0x017B)//SNR>=35.6dB
2496 return 89;//
2497 else if (u16NoisePower<=0x01A0)//SNR>=35.2dB
2498 return 88;//
2499 else if (u16NoisePower<=0x01C8)//SNR>=34.8dB
2500 return 87;//
2501 else if (u16NoisePower<=0x01F4)//SNR>=34.4dB
2502 return 86;//
2503 else if (u16NoisePower<=0x0224)//SNR>=34.0dB
2504 return 85;//
2505 else if (u16NoisePower<=0x0259)//SNR>=33.6dB
2506 return 84;//
2507 else if (u16NoisePower<=0x0293)//SNR>=33.2dB
2508 return 83;//
2509 else if (u16NoisePower<=0x02D2)//SNR>=32.8dB
2510 return 82;//
2511 else if (u16NoisePower<=0x0318)//SNR>=32.4dB
2512 return 81;//
2513 else if (u16NoisePower<=0x0364)//SNR>=32.0dB
2514 return 80;//
2515 else if (u16NoisePower<=0x03B8)//SNR>=31.6dB
2516 return 79;//
2517 else if (u16NoisePower<=0x0414)//SNR>=31.2dB
2518 return 78;//
2519 else if (u16NoisePower<=0x0479)//SNR>=30.8dB
2520 return 77;//
2521 else if (u16NoisePower<=0x04E7)//SNR>=30.4dB
2522 return 76;//
2523 else if (u16NoisePower<=0x0560)//SNR>=30.0dB
2524 return 75;//
2525 else if (u16NoisePower<=0x05E5)//SNR>=29.6dB
2526 return 74;//
2527 else if (u16NoisePower<=0x0677)//SNR>=29.2dB
2528 return 73;//
2529 else if (u16NoisePower<=0x0716)//SNR>=28.8dB
2530 return 72;//
2531 else if (u16NoisePower<=0x07C5)//SNR>=28.4dB
2532 return 71;//
2533 else if (u16NoisePower<=0x0885)//SNR>=28.0dB
2534 return 70;//
2535 else if (u16NoisePower<=0x0958)//SNR>=27.6dB
2536 return 69;//
2537 else if (u16NoisePower<=0x0A3E)//SNR>=27.2dB
2538 return 68;//
2539 else if (u16NoisePower<=0x0B3B)//SNR>=26.8dB
2540 return 67;//
2541 else if (u16NoisePower<=0x0C51)//SNR>=26.4dB
2542 return 66;//
2543 else if (u16NoisePower<=0x0D81)//SNR>=26.0dB
2544 return 65;//
2545 else if (u16NoisePower<=0x0ECF)//SNR>=25.6dB
2546 return 64;//
2547 else if (u16NoisePower<=0x103C)//SNR>=25.2dB
2548 return 63;//
2549 else if (u16NoisePower<=0x11CD)//SNR>=24.8dB
2550 return 62;//
2551 else if (u16NoisePower<=0x1385)//SNR>=24.4dB
2552 return 61;//
2553 else if (u16NoisePower<=0x1567)//SNR>=24.0dB
2554 return 60;//
2555 else if (u16NoisePower<=0x1778)//SNR>=23.6dB
2556 return 59;//
2557 else if (u16NoisePower<=0x19BB)//SNR>=23.2dB
2558 return 58;//
2559 else if (u16NoisePower<=0x1C37)//SNR>=22.8dB
2560 return 57;//
2561 else if (u16NoisePower<=0x1EF0)//SNR>=22.4dB
2562 return 56;//
2563 else if (u16NoisePower<=0x21EC)//SNR>=22.0dB
2564 return 55;//
2565 else if (u16NoisePower<=0x2531)//SNR>=21.6dB
2566 return 54;//
2567 else if (u16NoisePower<=0x28C8)//SNR>=21.2dB
2568 return 53;//
2569 else if (u16NoisePower<=0x2CB7)//SNR>=20.8dB
2570 return 52;//
2571 else if (u16NoisePower<=0x3108)//SNR>=20.4dB
2572 return 51;//
2573 else if (u16NoisePower<=0x35C3)//SNR>=20.0dB
2574 return 50;//
2575 else if (u16NoisePower<=0x3AF2)//SNR>=19.6dB
2576 return 49;//
2577 else if (u16NoisePower<=0x40A2)//SNR>=19.2dB
2578 return 48;//
2579 else if (u16NoisePower<=0x46DF)//SNR>=18.8dB
2580 return 47;//
2581 else if (u16NoisePower<=0x4DB5)//SNR>=18.4dB
2582 return 46;//
2583 else if (u16NoisePower<=0x5534)//SNR>=18.0dB
2584 return 45;//
2585 else if (u16NoisePower<=0x5D6D)//SNR>=17.6dB
2586 return 44;//
2587 else if (u16NoisePower<=0x6670)//SNR>=17.2dB
2588 return 43;//
2589 else if (u16NoisePower<=0x7052)//SNR>=16.8dB
2590 return 42;//
2591 else if (u16NoisePower<=0x7B28)//SNR>=16.4dB
2592 return 41;//
2593 else if (u16NoisePower<=0x870A)//SNR>=16.0dB
2594 return 40;//
2595 else if (u16NoisePower<=0x9411)//SNR>=15.6dB
2596 return 39;//
2597 else if (u16NoisePower<=0xA25A)//SNR>=15.2dB
2598 return 38;//
2599 else if (u16NoisePower<=0xB204)//SNR>=14.8dB
2600 return 37;//
2601 else if (u16NoisePower<=0xC331)//SNR>=14.4dB
2602 return 36;//
2603 else if (u16NoisePower<=0xD606)//SNR>=14.0dB
2604 return 35;//
2605 else if (u16NoisePower<=0xEAAC)//SNR>=13.6dB
2606 return 34;//
2607 else// if (u16NoisePower>=0xEAAC)//SNR<13.6dB
2608 return 33;//
2609 }
2610 else //QAM MODE
2611 {
2612 if( eMode == DMD_ATSC_DEMOD_ATSC_256QAM ) //256QAM//SNR=10*log10((2720<<10)/noisepower)
2613 {
2614 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
2615 return 0;//SNR=0;
2616 else if (u16NoisePower<=0x0117)//SNR>=40dB
2617 return 100;//
2618 else if (u16NoisePower<=0x0131)//SNR>=39.6dB
2619 return 99;//
2620 else if (u16NoisePower<=0x014F)//SNR>=39.2dB
2621 return 98;//
2622 else if (u16NoisePower<=0x016F)//SNR>=38.8dB
2623 return 97;//
2624 else if (u16NoisePower<=0x0193)//SNR>=38.4dB
2625 return 96;//
2626 else if (u16NoisePower<=0x01B9)//SNR>=38.0dB
2627 return 95;//
2628 else if (u16NoisePower<=0x01E4)//SNR>=37.6dB
2629 return 94;//
2630 else if (u16NoisePower<=0x0213)//SNR>=37.2dB
2631 return 93;//
2632 else if (u16NoisePower<=0x0246)//SNR>=36.8dB
2633 return 92;//
2634 else if (u16NoisePower<=0x027E)//SNR>=36.4dB
2635 return 91;//
2636 else if (u16NoisePower<=0x02BC)//SNR>=36.0dB
2637 return 90;//
2638 else if (u16NoisePower<=0x02FF)//SNR>=35.6dB
2639 return 89;//
2640 else if (u16NoisePower<=0x0349)//SNR>=35.2dB
2641 return 88;//
2642 else if (u16NoisePower<=0x039A)//SNR>=34.8dB
2643 return 87;//
2644 else if (u16NoisePower<=0x03F3)//SNR>=34.4dB
2645 return 86;//
2646 else if (u16NoisePower<=0x0455)//SNR>=34.0dB
2647 return 85;//
2648 else if (u16NoisePower<=0x04C0)//SNR>=33.6dB
2649 return 84;//
2650 else if (u16NoisePower<=0x0535)//SNR>=33.2dB
2651 return 83;//
2652 else if (u16NoisePower<=0x05B6)//SNR>=32.8dB
2653 return 82;//
2654 else if (u16NoisePower<=0x0643)//SNR>=32.4dB
2655 return 81;//
2656 else if (u16NoisePower<=0x06DD)//SNR>=32.0dB
2657 return 80;//
2658 else if (u16NoisePower<=0x0787)//SNR>=31.6dB
2659 return 79;//
2660 else if (u16NoisePower<=0x0841)//SNR>=31.2dB
2661 return 78;//
2662 else if (u16NoisePower<=0x090D)//SNR>=30.8dB
2663 return 77;//
2664 else if (u16NoisePower<=0x09EC)//SNR>=30.4dB
2665 return 76;//
2666 else if (u16NoisePower<=0x0AE1)//SNR>=30.0dB
2667 return 75;//
2668 else if (u16NoisePower<=0x0BEE)//SNR>=29.6dB
2669 return 74;//
2670 else if (u16NoisePower<=0x0D15)//SNR>=29.2dB
2671 return 73;//
2672 else if (u16NoisePower<=0x0E58)//SNR>=28.8dB
2673 return 72;//
2674 else if (u16NoisePower<=0x0FBA)//SNR>=28.4dB
2675 return 71;//
2676 else if (u16NoisePower<=0x113E)//SNR>=28.0dB
2677 return 70;//
2678 else if (u16NoisePower<=0x12E8)//SNR>=27.6dB
2679 return 69;//
2680 else if (u16NoisePower<=0x14BB)//SNR>=27.2dB
2681 return 68;//
2682 else if (u16NoisePower<=0x16BB)//SNR>=26.8dB
2683 return 67;//
2684 else if (u16NoisePower<=0x18ED)//SNR>=26.4dB
2685 return 66;//
2686 else if (u16NoisePower<=0x1B54)//SNR>=26.0dB
2687 return 65;//
2688 else if (u16NoisePower<=0x1DF7)//SNR>=25.6dB
2689 return 64;//
2690 else if (u16NoisePower<=0x20DB)//SNR>=25.2dB
2691 return 63;//
2692 else if (u16NoisePower<=0x2407)//SNR>=24.8dB
2693 return 62;//
2694 else if (u16NoisePower<=0x2781)//SNR>=24.4dB
2695 return 61;//
2696 else if (u16NoisePower<=0x2B50)//SNR>=24.0dB
2697 return 60;//
2698 else if (u16NoisePower<=0x2F7E)//SNR>=23.6dB
2699 return 59;//
2700 else if (u16NoisePower<=0x3413)//SNR>=23.2dB
2701 return 58;//
2702 else if (u16NoisePower<=0x3919)//SNR>=22.8dB
2703 return 57;//
2704 else if (u16NoisePower<=0x3E9C)//SNR>=22.4dB
2705 return 56;//
2706 else if (u16NoisePower<=0x44A6)//SNR>=22.0dB
2707 return 55;//
2708 else if (u16NoisePower<=0x4B45)//SNR>=21.6dB
2709 return 54;//
2710 else if (u16NoisePower<=0x5289)//SNR>=21.2dB
2711 return 53;//
2712 else if (u16NoisePower<=0x5A7F)//SNR>=20.8dB
2713 return 52;//
2714 else if (u16NoisePower<=0x633A)//SNR>=20.4dB
2715 return 51;//
2716 else if (u16NoisePower<=0x6CCD)//SNR>=20.0dB
2717 return 50;//
2718 else if (u16NoisePower<=0x774C)//SNR>=19.6dB
2719 return 49;//
2720 else if (u16NoisePower<=0x82CE)//SNR>=19.2dB
2721 return 48;//
2722 else if (u16NoisePower<=0x8F6D)//SNR>=18.8dB
2723 return 47;//
2724 else if (u16NoisePower<=0x9D44)//SNR>=18.4dB
2725 return 46;//
2726 else if (u16NoisePower<=0xAC70)//SNR>=18.0dB
2727 return 45;//
2728 else if (u16NoisePower<=0xBD13)//SNR>=17.6dB
2729 return 44;//
2730 else if (u16NoisePower<=0xCF50)//SNR>=17.2dB
2731 return 43;//
2732 else if (u16NoisePower<=0xE351)//SNR>=16.8dB
2733 return 42;//
2734 else if (u16NoisePower<=0xF93F)//SNR>=16.4dB
2735 return 41;//
2736 else// if (u16NoisePower>=0xF93F)//SNR<16.4dB
2737 return 40;//
2738 }
2739 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
2740 {
2741 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
2742 return 0;//SNR=0;
2743 else if (u16NoisePower<=0x0113)//SNR>=40dB
2744 return 100;//
2745 else if (u16NoisePower<=0x012E)//SNR>=39.6dB
2746 return 99;//
2747 else if (u16NoisePower<=0x014B)//SNR>=39.2dB
2748 return 98;//
2749 else if (u16NoisePower<=0x016B)//SNR>=38.8dB
2750 return 97;//
2751 else if (u16NoisePower<=0x018E)//SNR>=38.4dB
2752 return 96;//
2753 else if (u16NoisePower<=0x01B4)//SNR>=38.0dB
2754 return 95;//
2755 else if (u16NoisePower<=0x01DE)//SNR>=37.6dB
2756 return 94;//
2757 else if (u16NoisePower<=0x020C)//SNR>=37.2dB
2758 return 93;//
2759 else if (u16NoisePower<=0x023F)//SNR>=36.8dB
2760 return 92;//
2761 else if (u16NoisePower<=0x0277)//SNR>=36.4dB
2762 return 91;//
2763 else if (u16NoisePower<=0x02B3)//SNR>=36.0dB
2764 return 90;//
2765 else if (u16NoisePower<=0x02F6)//SNR>=35.6dB
2766 return 89;//
2767 else if (u16NoisePower<=0x033F)//SNR>=35.2dB
2768 return 88;//
2769 else if (u16NoisePower<=0x038F)//SNR>=34.8dB
2770 return 87;//
2771 else if (u16NoisePower<=0x03E7)//SNR>=34.4dB
2772 return 86;//
2773 else if (u16NoisePower<=0x0448)//SNR>=34.0dB
2774 return 85;//
2775 else if (u16NoisePower<=0x04B2)//SNR>=33.6dB
2776 return 84;//
2777 else if (u16NoisePower<=0x0525)//SNR>=33.2dB
2778 return 83;//
2779 else if (u16NoisePower<=0x05A5)//SNR>=32.8dB
2780 return 82;//
2781 else if (u16NoisePower<=0x0630)//SNR>=32.4dB
2782 return 81;//
2783 else if (u16NoisePower<=0x06C9)//SNR>=32.0dB
2784 return 80;//
2785 else if (u16NoisePower<=0x0770)//SNR>=31.6dB
2786 return 79;//
2787 else if (u16NoisePower<=0x0828)//SNR>=31.2dB
2788 return 78;//
2789 else if (u16NoisePower<=0x08F1)//SNR>=30.8dB
2790 return 77;//
2791 else if (u16NoisePower<=0x09CE)//SNR>=30.4dB
2792 return 76;//
2793 else if (u16NoisePower<=0x0AC1)//SNR>=30.0dB
2794 return 75;//
2795 else if (u16NoisePower<=0x0BCA)//SNR>=29.6dB
2796 return 74;//
2797 else if (u16NoisePower<=0x0CED)//SNR>=29.2dB
2798 return 73;//
2799 else if (u16NoisePower<=0x0E2D)//SNR>=28.8dB
2800 return 72;//
2801 else if (u16NoisePower<=0x0F8B)//SNR>=28.4dB
2802 return 71;//
2803 else if (u16NoisePower<=0x110A)//SNR>=28.0dB
2804 return 70;//
2805 else if (u16NoisePower<=0x12AF)//SNR>=27.6dB
2806 return 69;//
2807 else if (u16NoisePower<=0x147D)//SNR>=27.2dB
2808 return 68;//
2809 else if (u16NoisePower<=0x1677)//SNR>=26.8dB
2810 return 67;//
2811 else if (u16NoisePower<=0x18A2)//SNR>=26.4dB
2812 return 66;//
2813 else if (u16NoisePower<=0x1B02)//SNR>=26.0dB
2814 return 65;//
2815 else if (u16NoisePower<=0x1D9D)//SNR>=25.6dB
2816 return 64;//
2817 else if (u16NoisePower<=0x2078)//SNR>=25.2dB
2818 return 63;//
2819 else if (u16NoisePower<=0x239A)//SNR>=24.8dB
2820 return 62;//
2821 else if (u16NoisePower<=0x270A)//SNR>=24.4dB
2822 return 61;//
2823 else if (u16NoisePower<=0x2ACE)//SNR>=24.0dB
2824 return 60;//
2825 else if (u16NoisePower<=0x2EEF)//SNR>=23.6dB
2826 return 59;//
2827 else if (u16NoisePower<=0x3376)//SNR>=23.2dB
2828 return 58;//
2829 else if (u16NoisePower<=0x386D)//SNR>=22.8dB
2830 return 57;//
2831 else if (u16NoisePower<=0x3DDF)//SNR>=22.4dB
2832 return 56;//
2833 else if (u16NoisePower<=0x43D7)//SNR>=22.0dB
2834 return 55;//
2835 else if (u16NoisePower<=0x4A63)//SNR>=21.6dB
2836 return 54;//
2837 else if (u16NoisePower<=0x5190)//SNR>=21.2dB
2838 return 53;//
2839 else if (u16NoisePower<=0x596E)//SNR>=20.8dB
2840 return 52;//
2841 else if (u16NoisePower<=0x620F)//SNR>=20.4dB
2842 return 51;//
2843 else if (u16NoisePower<=0x6B85)//SNR>=20.0dB
2844 return 50;//
2845 else if (u16NoisePower<=0x75E5)//SNR>=19.6dB
2846 return 49;//
2847 else if (u16NoisePower<=0x8144)//SNR>=19.2dB
2848 return 48;//
2849 else if (u16NoisePower<=0x8DBD)//SNR>=18.8dB
2850 return 47;//
2851 else if (u16NoisePower<=0x9B6A)//SNR>=18.4dB
2852 return 46;//
2853 else if (u16NoisePower<=0xAA68)//SNR>=18.0dB
2854 return 45;//
2855 else if (u16NoisePower<=0xBAD9)//SNR>=17.6dB
2856 return 44;//
2857 else if (u16NoisePower<=0xCCE0)//SNR>=17.2dB
2858 return 43;//
2859 else if (u16NoisePower<=0xE0A4)//SNR>=16.8dB
2860 return 42;//
2861 else if (u16NoisePower<=0xF650)//SNR>=16.4dB
2862 return 41;//
2863 else// if (u16NoisePower>=0xF650)//SNR<16.4dB
2864 return 40;//
2865 }
2866 }
2867 }
2868
_HAL_INTERN_ATSC_GET_QAM_SNR(float * f_snr)2869 static MS_BOOL _HAL_INTERN_ATSC_GET_QAM_SNR(float *f_snr)
2870 {
2871 MS_U8 u8Data = 0;
2872 MS_U16 noisepower = 0;
2873
2874 if (_HAL_INTERN_ATSC_QAM_Main_Lock())
2875 {
2876 // latch
2877 _MBX_WriteReg(0x2905, 0x80);
2878 // read noise power
2879 _MBX_ReadReg(0x2A45, &u8Data);
2880 noisepower = u8Data;
2881 _MBX_ReadReg(0x2A44, &u8Data);
2882 noisepower = (noisepower<<8)|u8Data;
2883 // unlatch
2884 _MBX_WriteReg(0x2905, 0x00);
2885
2886 if (noisepower == 0x0000)
2887 noisepower = 0x0001;
2888
2889 #ifdef MSOS_TYPE_LINUX
2890 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
2891 #else
2892 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
2893 #endif
2894 }
2895 else
2896 {
2897 *f_snr = 0.0f;
2898 }
2899
2900 return TRUE;
2901 }
2902
_HAL_INTERN_ATSC_ReadPKTERR(void)2903 static MS_U16 _HAL_INTERN_ATSC_ReadPKTERR(void)
2904 {
2905 MS_U16 data = 0;
2906 DMD_ATSC_DEMOD_TYPE eMode;
2907
2908 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
2909
2910 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
2911 {
2912 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) data = 0;
2913 else
2914 {
2915 _MBX_ReadReg(0x2B20, ((MS_U8*)(&data))+1);
2916 _MBX_ReadReg(0x2B21, (MS_U8*)(&data));
2917 }
2918 }
2919 else
2920 {
2921 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) data = 0;
2922 else
2923 {
2924 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2925 _MBX_ReadReg(0x1F66, ((MS_U8*)(&data))+1);
2926 _MBX_ReadReg(0x1F67, (MS_U8*)(&data));
2927 #else
2928 _MBX_ReadReg(0x2B20, ((MS_U8*)(&data))+1);
2929 _MBX_ReadReg(0x2B21, (MS_U8*)(&data));
2930 #endif
2931 }
2932 }
2933
2934 return data;
2935 }
2936
_HAL_INTERN_ATSC_ReadBER(float * pBer)2937 static MS_BOOL _HAL_INTERN_ATSC_ReadBER(float *pBer)
2938 {
2939 MS_BOOL status = true;
2940 MS_U8 reg = 0, reg_frz = 0;
2941 MS_U16 BitErrPeriod;
2942 MS_U32 BitErr;
2943 DMD_ATSC_DEMOD_TYPE eMode;
2944
2945 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
2946
2947 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
2948 {
2949 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) *pBer = 0;
2950 else
2951 {
2952 _MBX_ReadReg(0x1F03, ®_frz);
2953 _MBX_WriteReg(0x1F03, reg_frz|0x03);
2954
2955 _MBX_ReadReg(0x1F47, ®);
2956 BitErrPeriod = reg;
2957 _MBX_ReadReg(0x1F46, ®);
2958 BitErrPeriod = (BitErrPeriod << 8)|reg;
2959
2960 status &= _MBX_ReadReg(0x1F6d, ®);
2961 BitErr = reg;
2962 status &= _MBX_ReadReg(0x1F6c, ®);
2963 BitErr = (BitErr << 8)|reg;
2964 status &= _MBX_ReadReg(0x1F6b, ®);
2965 BitErr = (BitErr << 8)|reg;
2966 status &= _MBX_ReadReg(0x1F6a, ®);
2967 BitErr = (BitErr << 8)|reg;
2968
2969 reg_frz=reg_frz&(~0x03);
2970 _MBX_WriteReg(0x1F03, reg_frz);
2971
2972 if (BitErrPeriod == 0 ) //protect 0
2973 BitErrPeriod = 1;
2974 if (BitErr <=0 )
2975 *pBer = 0.5f / ((float)BitErrPeriod*8*187*128);
2976 else
2977 *pBer = (float)BitErr / ((float)BitErrPeriod*8*187*128);
2978 }
2979 }
2980 else
2981 {
2982 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) *pBer = 0;
2983 else
2984 {
2985 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2986 _MBX_ReadReg(0x2103, ®_frz);
2987 _MBX_WriteReg(0x2103, reg_frz|0x03);
2988
2989 _MBX_ReadReg(0x2147, ®);
2990 BitErrPeriod = reg;
2991 _MBX_ReadReg(0x2146, ®);
2992 BitErrPeriod = (BitErrPeriod << 8)|reg;
2993
2994 status &= _MBX_ReadReg(0x216d, ®);
2995 BitErr = reg;
2996 status &= _MBX_ReadReg(0x216c, ®);
2997 BitErr = (BitErr << 8)|reg;
2998 status &= _MBX_ReadReg(0x216b, ®);
2999 BitErr = (BitErr << 8)|reg;
3000 status &= _MBX_ReadReg(0x216a, ®);
3001 BitErr = (BitErr << 8)|reg;
3002
3003 reg_frz=reg_frz&(~0x03);
3004 _MBX_WriteReg(0x2103, reg_frz);
3005
3006 if (BitErrPeriod == 0) //protect 0
3007 BitErrPeriod = 1;
3008 if (BitErr <=0)
3009 *pBer = 0.5f / ((float)BitErrPeriod*8*188*128);
3010 else
3011 *pBer = (float)BitErr / ((float)BitErrPeriod*8*188*128);
3012 #else
3013 _MBX_ReadReg(0x1F03, ®_frz);
3014 _MBX_WriteReg(0x1F03, reg_frz|0x03);
3015
3016 _MBX_ReadReg(0x1F47, ®);
3017 BitErrPeriod = reg;
3018 _MBX_ReadReg(0x1F46, ®);
3019 BitErrPeriod = (BitErrPeriod << 8)|reg;
3020
3021 BitErr = reg;
3022 status &= _MBX_ReadReg(0x1F6c, ®);
3023 BitErr = (BitErr << 8)|reg;
3024 status &= _MBX_ReadReg(0x1F6b, ®);
3025 BitErr = (BitErr << 8)|reg;
3026 status &= _MBX_ReadReg(0x1F6a, ®);
3027 BitErr = (BitErr << 8)|reg;
3028
3029 reg_frz=reg_frz&(~0x03);
3030 _MBX_WriteReg(0x1F03, reg_frz);
3031
3032 if (BitErrPeriod == 0 ) //protect 0
3033 BitErrPeriod = 1;
3034 if (BitErr <=0 )
3035 *pBer = 0.5f / ((float)BitErrPeriod*7*122*128);
3036 else
3037 *pBer = (float)BitErr / ((float)BitErrPeriod*7*122*128);
3038 #endif
3039 }
3040 }
3041
3042 return status;
3043 }
3044
_HAL_INTERN_ATSC_ReadFrequencyOffset(void)3045 static MS_S16 _HAL_INTERN_ATSC_ReadFrequencyOffset(void)
3046 {
3047 DMD_ATSC_DEMOD_TYPE eMode;
3048 MS_U8 u8PTK_LOOP_FF_R3=0, u8PTK_LOOP_FF_R2=0;
3049 MS_U8 u8PTK_RATE_2=0;
3050 MS_U8 u8AD_CRL_LOOP_VALUE0=0, u8AD_CRL_LOOP_VALUE1=0;
3051 MS_U8 u8MIX_RATE_0=0, u8MIX_RATE_1=0, u8MIX_RATE_2=0;
3052 MS_S16 PTK_LOOP_FF;
3053 MS_S16 AD_CRL_LOOP_VALUE;
3054 MS_S16 MIX_RATE;
3055 MS_S16 FreqOffset = 0; //kHz
3056
3057 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3058
3059 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//
3060 {
3061 _MBX_WriteReg(0x297E, 0x01);
3062 _MBX_WriteReg(0x29E6, 0xff);
3063 _MBX_ReadReg(0x297C, &u8PTK_LOOP_FF_R2);
3064 _MBX_ReadReg(0x297D, &u8PTK_LOOP_FF_R3);
3065 _MBX_WriteReg(0x297E, 0x00);
3066 _MBX_WriteReg(0x29E6, 0xff);
3067
3068 PTK_LOOP_FF = (u8PTK_LOOP_FF_R3<<8) | u8PTK_LOOP_FF_R2;
3069 FreqOffset = (float)(-PTK_LOOP_FF*0.04768);
3070
3071 _MBX_ReadReg(0x2982, &u8PTK_RATE_2);
3072
3073 if (u8PTK_RATE_2 == 0x07)
3074 FreqOffset = FreqOffset-100;
3075 else if (u8PTK_RATE_2 == 0x08)
3076 FreqOffset = FreqOffset-500;
3077 }
3078 else //QAM MODE
3079 {
3080 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3081 _MBX_ReadReg(0x2A40, &u8AD_CRL_LOOP_VALUE0);
3082 _MBX_ReadReg(0x2A41, &u8AD_CRL_LOOP_VALUE1);
3083 _MBX_ReadReg(0x2758, &u8MIX_RATE_0);
3084 _MBX_ReadReg(0x2759, &u8MIX_RATE_1);
3085 _MBX_ReadReg(0x275A, &u8MIX_RATE_2);
3086
3087 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1 << 8) | u8AD_CRL_LOOP_VALUE0;
3088 MIX_RATE = ((u8MIX_RATE_2 << 16) | (u8MIX_RATE_1 << 8) | u8MIX_RATE_0) >> 4;
3089
3090 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
3091 {
3092 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000199); //5.360537E6/2^28*1000
3093 }
3094 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
3095 {
3096 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000188); //5.056941E6/2^21*1000
3097 }
3098
3099 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3A07)/330.13018; //(0.001/25.41*2^27/16)???
3100 #else
3101 _MBX_ReadReg(0x2C04, &u8AD_CRL_LOOP_VALUE0);
3102 _MBX_ReadReg(0x2C05, &u8AD_CRL_LOOP_VALUE1);
3103
3104 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1<<8) | u8AD_CRL_LOOP_VALUE0;
3105
3106 _MBX_ReadReg(0x2904, &u8MIX_RATE_0);
3107 _MBX_ReadReg(0x2905, &u8MIX_RATE_1);
3108 _MBX_ReadReg(0x2906, &u8MIX_RATE_2);
3109
3110 MIX_RATE = (u8MIX_RATE_2<<12)|(u8MIX_RATE_1<<4)|(u8MIX_RATE_0>>4);
3111
3112 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
3113 {
3114 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0025561); //5.360537E6/2^21*1000
3115 }
3116 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
3117 {
3118 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.00241134); //5.056941E6/2^21*1000
3119 }
3120
3121 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3D70)/2.62144; //(0.001/25*2^20/16)
3122 #endif
3123 }
3124
3125 return FreqOffset;
3126 }
3127
_HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)3128 static MS_BOOL _HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
3129 {
3130 return _MBX_ReadReg(u16Addr, pu8Data);
3131 }
3132
_HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr,MS_U8 u8Data)3133 static MS_BOOL _HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
3134 {
3135 return _MBX_WriteReg(u16Addr, u8Data);
3136 }
3137
3138 //-------------------------------------------------------------------------------------------------
3139 // Global Functions
3140 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd,void * pArgs)3141 MS_BOOL HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd, void *pArgs)
3142 {
3143 MS_BOOL bResult = TRUE;
3144
3145 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
3146 _SEL_DMD();
3147 #endif
3148
3149 switch(eCmd)
3150 {
3151 case DMD_ATSC_HAL_CMD_Exit:
3152 bResult = _HAL_INTERN_ATSC_Exit();
3153 break;
3154 case DMD_ATSC_HAL_CMD_InitClk:
3155 _HAL_INTERN_ATSC_InitClk(false);
3156 break;
3157 case DMD_ATSC_HAL_CMD_Download:
3158 bResult = _HAL_INTERN_ATSC_Download();
3159 break;
3160 case DMD_ATSC_HAL_CMD_FWVERSION:
3161 _HAL_INTERN_ATSC_FWVERSION();
3162 break;
3163 case DMD_ATSC_HAL_CMD_SoftReset:
3164 bResult = _HAL_INTERN_ATSC_SoftReset();
3165 break;
3166 case DMD_ATSC_HAL_CMD_SetVsbMode:
3167 bResult = _HAL_INTERN_ATSC_SetVsbMode();
3168 break;
3169 case DMD_ATSC_HAL_CMD_Set64QamMode:
3170 bResult = _HAL_INTERN_ATSC_Set64QamMode();
3171 break;
3172 case DMD_ATSC_HAL_CMD_Set256QamMode:
3173 bResult = _HAL_INTERN_ATSC_Set256QamMode();
3174 break;
3175 case DMD_ATSC_HAL_CMD_SetModeClean:
3176 bResult = _HAL_INTERN_ATSC_SetModeClean();
3177 break;
3178 case DMD_ATSC_HAL_CMD_Set_QAM_SR:
3179 break;
3180 case DMD_ATSC_HAL_CMD_Active:
3181 break;
3182 case DMD_ATSC_HAL_CMD_Check8VSB64_256QAM:
3183 *((DMD_ATSC_DEMOD_TYPE *)pArgs) = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3184 break;
3185 case DMD_ATSC_HAL_CMD_AGCLock:
3186 bResult = _HAL_INTERN_ATSC_Vsb_QAM_AGCLock();
3187 break;
3188 case DMD_ATSC_HAL_CMD_Vsb_PreLock:
3189 bResult = _HAL_INTERN_ATSC_Vsb_PreLock();
3190 break;
3191 case DMD_ATSC_HAL_CMD_Vsb_FSync_Lock:
3192 bResult = _HAL_INTERN_ATSC_Vsb_FSync_Lock();
3193 break;
3194 case DMD_ATSC_HAL_CMD_Vsb_CE_Lock:
3195 bResult = _HAL_INTERN_ATSC_Vsb_CE_Lock();
3196 break;
3197 case DMD_ATSC_HAL_CMD_Vsb_FEC_Lock:
3198 bResult = _HAL_INTERN_ATSC_Vsb_FEC_Lock();
3199 break;
3200 case DMD_ATSC_HAL_CMD_QAM_PreLock:
3201 bResult = _HAL_INTERN_ATSC_QAM_PreLock();
3202 break;
3203 case DMD_ATSC_HAL_CMD_QAM_Main_Lock:
3204 bResult = _HAL_INTERN_ATSC_QAM_Main_Lock();
3205 break;
3206 case DMD_ATSC_HAL_CMD_ReadIFAGC:
3207 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadIFAGC();
3208 break;
3209 case DMD_ATSC_HAL_CMD_CheckSignalCondition:
3210 _HAL_INTERN_ATSC_CheckSignalCondition((DMD_ATSC_SIGNAL_CONDITION *)pArgs);
3211 break;
3212 case DMD_ATSC_HAL_CMD_ReadSNRPercentage:
3213 *((MS_U8 *)pArgs) = _HAL_INTERN_ATSC_ReadSNRPercentage();
3214 break;
3215 case CMD_ATSC_HAL_CMD_GET_QAM_SNR:
3216 bResult = _HAL_INTERN_ATSC_GET_QAM_SNR((float *)pArgs);
3217 break;
3218 case DMD_ATSC_HAL_CMD_ReadPKTERR:
3219 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadPKTERR();
3220 break;
3221 case DMD_ATSC_HAL_CMD_GetPreViterbiBer:
3222 break;
3223 case DMD_ATSC_HAL_CMD_GetPostViterbiBer:
3224 bResult = _HAL_INTERN_ATSC_ReadBER((float *)pArgs);
3225 break;
3226 case DMD_ATSC_HAL_CMD_ReadFrequencyOffset:
3227 *((MS_S16 *)pArgs) = _HAL_INTERN_ATSC_ReadFrequencyOffset();
3228 break;
3229 case DMD_ATSC_HAL_CMD_TS_INTERFACE_CONFIG:
3230 break;
3231 case DMD_ATSC_HAL_CMD_IIC_Bypass_Mode:
3232 break;
3233 case DMD_ATSC_HAL_CMD_SSPI_TO_GPIO:
3234 break;
3235 case DMD_ATSC_HAL_CMD_GPIO_GET_LEVEL:
3236 break;
3237 case DMD_ATSC_HAL_CMD_GPIO_SET_LEVEL:
3238 break;
3239 case DMD_ATSC_HAL_CMD_GPIO_OUT_ENABLE:
3240 break;
3241 case DMD_ATSC_HAL_CMD_GET_REG:
3242 bResult = _HAL_INTERN_ATSC_GetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ATSC_REG_DATA *)pArgs)).u8Data));
3243 break;
3244 case DMD_ATSC_HAL_CMD_SET_REG:
3245 bResult = _HAL_INTERN_ATSC_SetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, (*((DMD_ATSC_REG_DATA *)pArgs)).u8Data);
3246 break;
3247 default:
3248 break;
3249 }
3250
3251 return bResult;
3252 }
3253
MDrv_DMD_ATSC_Initial_Hal_Interface(void)3254 MS_BOOL MDrv_DMD_ATSC_Initial_Hal_Interface(void)
3255 {
3256 return TRUE;
3257 }
3258