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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include <math.h>
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 //#include "apiPWS.h"
109
110 #include "MsTypes.h"
111 #include "drvBDMA.h"
112 //#include "drvIIC.h"
113 //#include "msAPI_Tuner.h"
114 //#include "msAPI_MIU.h"
115 //#include "BinInfo.h"
116 //#include "halVif.h"
117 #include "drvDMD_INTERN_DVBC.h"
118 #include "halDMD_INTERN_DVBC.h"
119 #include "halDMD_INTERN_common.h"
120 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
121 #include "InfoBlock.h"
122 #endif
123 #include "drvMMIO.h"
124 //#include "TDAG4D01A_SSI_DVBT.c"
125 #include "drvDMD_VD_MBX.h"
126 #include "ULog.h"
127 #define TEST_EMBEDED_DEMOD 0
128 //U8 load_data_variable=1;
129 //-----------------------------------------------------------------------
130 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
131
132 #define TDE_REG_BASE 0x2400
133 #define INNC_REG_BASE 0x2A00
134 #define EQE_REG_BASE 0x2B00
135 //#define EQE2_REG_BASE 0x2d00
136
137
138
139 #ifdef MS_DEBUG
140 #define DBG_INTERN_DVBC(x) x
141 #define DBG_GET_SIGNAL_DVBC(x) x
142 #define DBG_INTERN_DVBC_TIME(x) x
143 #define DBG_INTERN_DVBC_LOCK(x) x
144 #define INTERN_DVBC_INTERNAL_DEBUG 1
145 #else
146 #define DBG_INTERN_DVBC(x) //x
147 #define DBG_GET_SIGNAL_DVBC(x) //x
148 #define DBG_INTERN_DVBC_TIME(x) //x
149 #define DBG_INTERN_DVBC_LOCK(x) //x
150 #define INTERN_DVBC_INTERNAL_DEBUG 0
151 #endif
152 #define DBG_DUMP_LOAD_DSP_TIME 0
153
154
155 #define SIGNAL_LEVEL_OFFSET 0.00f
156 #define TAKEOVERPOINT -60.0f
157 #define TAKEOVERRANGE 0.5f
158 #define LOG10_OFFSET -0.21f
159 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
160 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
161
162 #define TUNER_IF 5000
163
164 #define TS_SER_C 0x00 //0: parallel 1:serial
165
166 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
167 #define TS_INV_C 0x01
168 #else
169 #define TS_INV_C 0x00
170 #endif
171
172 #define DVBC_FS 45473
173 #define CFG_ZIF 0x00 //For ZIF ,FC=0
174 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
175 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
176 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
177 #define FS_L_C (DVBC_FS&0xFF)
178 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
179 #define IQ_SWAP_C 0x01
180 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
181 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
182 // Symbol Rate: 6875 = 0x1ADB
183 // Symbol Rate: 6900 = 0x1AF4
184 // Symbol Rate: 7000 = 0x1B58
185 // Symbol Rate: 4000 = 0x0FA0
186 // Symbol Rate: 6125 = 0x17ED
187 #define SR0_H 0x1A
188 #define SR0_L 0xF4 //6900
189 #define SR1_H 0x1B
190 #define SR1_L 0x58 //7000
191 #define SR2_H 0x17
192 #define SR2_L 0xED //6125
193 #define SR3_H 0x0F
194 #define SR3_L 0xA0 //4000
195 #define SR4_H 0x1B
196 #define SR4_L 0x26 //6950
197 #define SR5_H 0x1A
198 #define SR5_L 0xDB //6875
199 #define SR6_H 0x1C
200 #define SR6_L 0x20 //7200
201 #define SR7_H 0x1C
202 #define SR7_L 0x52 //7250
203 #define SR8_H 0x0B
204 #define SR8_L 0xB8 //3000
205 #define SR9_H 0x03
206 #define SR9_L 0xE8 //1000
207 #define SR10_H 0x07
208 #define SR10_L 0xD0 //2000
209 #define SR11_H 0x00
210 #define SR11_L 0x00 //0000
211
212
213 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
214
215 // SAR dependent
216 #define NO_SIGNAL_TH_A 0xA3
217 // Tuner dependent
218 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
219 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
220 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
221 #define NO_SIGNAL_TH_C_H 0xff //0x00
222 #define DAGC1_REF 0x70
223 #define DAGC2_REF 0x30
224 #define AGC_REF_L 0xF0
225 #define AGC_REF_H 0x02
226
227 #define INTERN_AUTO_SR_C 1
228 #define INTERN_AUTO_QAM_C 1
229
230 #define ATV_DET_EN 1
231
232 #if 0
233 MS_U8 INTERN_DVBC_DSPREG[] =
234 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
235 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
236 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
237 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
238 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
239 };
240 #else
241 MS_U8 INTERN_DVBC_DSPREG[] =
242 {
243 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
244 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
245 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
246 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
247 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
248 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
249 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
250 };
251 #endif
252 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
253
254 //-----------------------------------------------------------------------
255 /****************************************************************
256 *Local Variables *
257 ****************************************************************/
258
259 //static MS_BOOL TPSLock = 0;
260 static MS_U32 u32ChkScanTimeStartDVBC = 0;
261 static MS_U8 g_dvbc_lock = 0;
262 static float intern_dvb_c_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
263
264 //Global Variables
265 S_CMDPKTREG gsCmdPacketDVBC;
266 //MS_U8 gCalIdacCh0, gCalIdacCh1;
267 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
268 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
269 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
270 MS_U8 INTERN_DVBC_table[] = {
271 #include "fwDMD_INTERN_DVBC.dat"
272 };
273
274 #endif
275
276 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
277 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
278 // MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
279 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
280 // MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff);
281 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
282 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
283 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
284
285 #if (INTERN_DVBC_INTERNAL_DEBUG)
286 void INTERN_DVBC_info(void);
287 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
288 #endif
289
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)290 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
291 {
292 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
293 MS_U8 status = TRUE;
294 MS_U16 u16DspAddr = 0;
295
296 DBG_INTERN_DVBC(ULOGD("Utopia","INTERN_DVBC_DSPReg_Init\n"));
297
298 #if 0//def MS_DEBUG
299 {
300 MS_U8 u8buffer[256];
301 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init Reset\n");
302 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
303 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
304
305 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
306 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
307 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
308 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
309 ULOGD("Utopia","%x ", u8buffer[idx]);
310 ULOGD("Utopia","\n");
311
312 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init Value\n");
313 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
314 ULOGD("Utopia","%x ", INTERN_DVBC_DSPREG[idx]);
315 ULOGD("Utopia","\n");
316 }
317 #endif
318
319 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
320 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
321
322 // readback to confirm.
323 #ifdef MS_DEBUG
324 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
325 {
326 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
327 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
328 {
329 ULOGE("Utopia","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
330 }
331 }
332 #endif
333
334 if (u8DVBC_DSPReg != NULL)
335 {
336 if (1 == u8DVBC_DSPReg[0])
337 {
338 u8DVBC_DSPReg+=2;
339 for (idx = 0; idx<u8Size; idx++)
340 {
341 u16DspAddr = *u8DVBC_DSPReg;
342 u8DVBC_DSPReg++;
343 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
344 u8DVBC_DSPReg++;
345 u8Mask = *u8DVBC_DSPReg;
346 u8DVBC_DSPReg++;
347 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
348 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
349 u8DVBC_DSPReg++;
350 DBG_INTERN_DVBC(ULOGD("Utopia","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
351 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
352 }
353 }
354 else
355 {
356 ULOGE("Utopia","FATAL: parameter version incorrect\n");
357 }
358 }
359
360 #if 0//def MS_DEBUG
361 {
362 MS_U8 u8buffer[256];
363 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
364 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
365 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init ReadBack\n");
366 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
367 ULOGD("Utopia","%x ", u8buffer[idx]);
368 ULOGD("Utopia","\n");
369 }
370 #endif
371
372 #if 0//def MS_DEBUG
373 {
374 MS_U8 u8buffer[256];
375 for (idx = 0; idx<128; idx++)
376 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
377 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
378 for (idx = 0; idx<128; idx++)
379 {
380 ULOGD("Utopia","%x ", u8buffer[idx]);
381 if ((idx & 0xF) == 0xF) ULOGD("Utopia","\n");
382 }
383 ULOGD("Utopia","\n");
384 }
385 #endif
386 return status;
387 }
388
389 /***********************************************************************************
390 Subject: Command Packet Interface
391 Function: INTERN_DVBC_Cmd_Packet_Send
392 Parmeter:
393 Return: MS_BOOL
394 Remark:
395 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)396 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
397 {
398 MS_U8 status = true, indx;
399 MS_U8 reg_val, timeout = 0;
400 return TRUE;
401 // ==== Command Phase ===================
402 DBG_INTERN_DVBC(ULOGD("Utopia","--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
403 pCmdPacket->param[0],pCmdPacket->param[1],
404 pCmdPacket->param[2],pCmdPacket->param[3],
405 pCmdPacket->param[4],pCmdPacket->param[5] ));
406
407 // wait _BIT_END clear
408 do
409 {
410 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
411 if((reg_val & _BIT_END) != _BIT_END)
412 {
413 break;
414 }
415 MsOS_DelayTask(5);
416 if (timeout > 200)
417 {
418 ULOGE("Utopia","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
419 return false;
420 }
421 timeout++;
422 } while (1);
423
424 // set cmd_3:0 and _BIT_START
425 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
426 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
427 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
428
429
430 //DBG_INTERN_DVBT(ULOGD("Utopia","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
431 // wait _BIT_START clear
432 do
433 {
434 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
435 if((reg_val & _BIT_START) != _BIT_START)
436 {
437 break;
438 }
439 MsOS_DelayTask(10);
440 if (timeout > 200)
441 {
442 ULOGE("Utopia","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
443 return false;
444 }
445 timeout++;
446 } while (1);
447
448 // ==== Data Phase ======================
449
450 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
451
452 for (indx = 0; indx < param_cnt; indx++)
453 {
454 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
455 //DBG_INTERN_DVBT(ULOGD("Utopia","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
456
457 // set param[indx] and _BIT_DRQ
458 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
459 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
460 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
461
462 // wait _BIT_DRQ clear
463 do
464 {
465 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
466 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
467 {
468 break;
469 }
470 MsOS_DelayTask(5);
471 if (timeout > 200)
472 {
473 ULOGE("Utopia","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
474 return false;
475 }
476 timeout++;
477 } while (1);
478 }
479
480 // ==== End Phase =======================
481
482 // set _BIT_END to finish command
483 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
484 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
485 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
486 return status;
487 }
488
489
490 /***********************************************************************************
491 Subject: Command Packet Interface
492 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
493 Parmeter:
494 Return: MS_BOOL
495 Remark:
496 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)497 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
498 {
499 return TRUE;
500 }
501
502 /***********************************************************************************
503 Subject: SoftStop
504 Function: INTERN_DVBC_SoftStop
505 Parmeter:
506 Return: MS_BOOL
507 Remark:
508 ************************************************************************************/
509
INTERN_DVBC_SoftStop(void)510 MS_BOOL INTERN_DVBC_SoftStop ( void )
511 {
512 #if 1
513 MS_U16 u8WaitCnt=0;
514
515 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
516 {
517 ULOGE("Utopia",">> MB Busy!\n");
518 return FALSE;
519 }
520
521 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
522
523 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
524 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
525
526 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
527 {
528 #if TEST_EMBEDED_DEMOD
529 MsOS_DelayTask(1); // << Ken 20090629
530 #endif
531 if (u8WaitCnt++ >= 0xFF)
532 {
533 ULOGE("Utopia",">> DVBT SoftStop Fail!\n");
534 return FALSE;
535 }
536 }
537
538 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
539 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
540 #endif
541 return TRUE;
542 }
543
544
545 /***********************************************************************************
546 Subject: Reset
547 Function: INTERN_DVBC_Reset
548 Parmeter:
549 Return: MS_BOOL
550 Remark:
551 ************************************************************************************/
552 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)553 MS_BOOL INTERN_DVBC_Reset ( void )
554 {
555 DBG_INTERN_DVBC(ULOGD("Utopia"," @INTERN_DVBC_reset\n"));
556
557 DBG_INTERN_DVBC_TIME(ULOGD("Utopia","INTERN_DVBC_Reset, t = %ld\n",MsOS_GetSystemTime()));
558
559 INTERN_DVBC_SoftStop();
560
561
562 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
563 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
564 MsOS_DelayTask(5);
565 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
566 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
567 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
568 MsOS_DelayTask(5);
569
570 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
571 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
572
573 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
574 g_dvbc_lock = 0;
575
576 return TRUE;
577 }
578
579 /***********************************************************************************
580 Subject: Exit
581 Function: INTERN_DVBC_Exit
582 Parmeter:
583 Return: MS_BOOL
584 Remark:
585 ************************************************************************************/
INTERN_DVBC_Exit(void)586 MS_BOOL INTERN_DVBC_Exit ( void )
587 {
588
589 INTERN_DVBC_SoftStop();
590
591
592 //diable clk gen
593 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
594 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
595
596 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
597 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
598
599 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
600 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
601
602 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
603 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
604
605 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
606 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
607
608 HAL_DMD_RIU_WriteByte(0x103312, 0x05); // dvbt_t:0x0000, dvb_c: 0x0004
609 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
610
611 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
612 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
613
614 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
615 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
616
617 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
618 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
619
620 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
621 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
622
623 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
624
625 return TRUE;
626 }
627
628 /***********************************************************************************
629 Subject: Load DSP code to chip
630 Function: INTERN_DVBC_LoadDSPCode
631 Parmeter:
632 Return: MS_BOOL
633 Remark:
634 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)635 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
636 {
637 MS_U8 udata = 0x00;
638 MS_U16 i;
639 MS_U16 fail_cnt=0;
640
641 #if (DBG_DUMP_LOAD_DSP_TIME==1)
642 MS_U32 u32Time;
643 #endif
644
645
646 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
647 BININFO BinInfo;
648 MS_BOOL bResult;
649 MS_U32 u32GEAddr;
650 MS_U8 Data;
651 MS_S8 op;
652 MS_U32 srcaddr;
653 MS_U32 len;
654 MS_U32 SizeBy4K;
655 MS_U16 u16Counter=0;
656 MS_U8 *pU8Data;
657 #endif
658
659 #if 0
660 if(HAL_DMD_RIU_ReadByte(0x101E3E))
661 {
662 ULOGD("Utopia","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
663 return FALSE;
664 }
665 #endif
666
667 // MDrv_Sys_DisableWatchDog();
668
669
670 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
671 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
672 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
673 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
674 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
675 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
676
677 //// Load code thru VDMCU_IF ////
678 DBG_INTERN_DVBC(ULOGD("Utopia",">Load Code.....\n"));
679 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
680 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
681 {
682 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
683 }
684 #else
685 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
686 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
687 if ( bResult != PASS )
688 {
689 return FALSE;
690 }
691 //ULOGD("Utopia","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
692
693 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
694 InfoBlock_Flash_2_Checking_Start(&BinInfo);
695 #endif
696
697 #if OBA2
698 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
699 #else
700 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
701 #endif
702
703 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
704 InfoBlock_Flash_2_Checking_End(&BinInfo);
705 #endif
706
707 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
708 SizeBy4K=BinInfo.B_Len/0x1000;
709 //ULOGD("Utopia","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
710
711 #if (DBG_DUMP_LOAD_DSP_TIME==1)
712 u32Time = msAPI_Timer_GetTime0();
713 #endif
714
715 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
716
717 for (i=0;i<=SizeBy4K;i++)
718 {
719 if(i==SizeBy4K)
720 len=BinInfo.B_Len%0x1000;
721 else
722 len=0x1000;
723
724 srcaddr = u32GEAddr+(0x1000*i);
725 //ULOGD("Utopia","\t i = %08X\n", i);
726 //ULOGD("Utopia","\t len = %08X\n", len);
727 op = 1;
728 u16Counter = 0 ;
729 //ULOGD("Utopia","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
730 while(len--)
731 {
732 u16Counter ++ ;
733 //ULOGD("Utopia","file: %s, line: %d\n", __FILE__, __LINE__);
734 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
735 #if OBA2
736 pU8Data = (MS_U8 *)(srcaddr);
737 #else
738 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
739 #endif
740 Data = *pU8Data;
741
742 #if 0
743 if(u16Counter < 0x100)
744 ULOGD("Utopia","0x%bx,", Data);
745 #endif
746 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
747
748 srcaddr += op;
749 }
750 // ULOGD("Utopia","\n\n\n");
751 }
752
753 #if (DBG_DUMP_LOAD_DSP_TIME==1)
754 ULOGD("Utopia","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
755 #endif
756
757 #endif
758
759 //// Content verification ////
760 DBG_INTERN_DVBC(ULOGD("Utopia",">Verify Code...\n"));
761
762 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
763 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
764
765 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
766 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
767 {
768 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
769 if (udata != INTERN_DVBC_table[i])
770 {
771 ULOGE("Utopia",">fail add = 0x%x\n", i);
772 ULOGE("Utopia",">code = 0x%x\n", INTERN_DVBC_table[i]);
773 ULOGE("Utopia",">data = 0x%x\n", udata);
774
775 if (fail_cnt > 10)
776 {
777 ULOGE("Utopia",">DVB-C DSP Loadcode fail!");
778 return false;
779 }
780 fail_cnt++;
781 }
782 }
783 #else
784 for (i=0;i<=SizeBy4K;i++)
785 {
786 if(i==SizeBy4K)
787 len=BinInfo.B_Len%0x1000;
788 else
789 len=0x1000;
790
791 srcaddr = u32GEAddr+(0x1000*i);
792 //printf("\t i = %08LX\n", i);
793 //printf("\t len = %08LX\n", len);
794 op = 1;
795 u16Counter = 0 ;
796 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
797 while(len--)
798 {
799 u16Counter ++ ;
800 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
801 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
802 #if OBA2
803 pU8Data = (MS_U8 *)(srcaddr);
804 #else
805 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
806 #endif
807 Data = *pU8Data;
808
809 #if 0
810 if(u16Counter < 0x100)
811 ULOGD("Utopia","0x%bx,", Data);
812 #endif
813 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
814 if (udata != Data)
815 {
816 ULOGE("Utopia",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
817 ULOGE("Utopia",">code = 0x%x\n", Data);
818 ULOGE("Utopia",">data = 0x%x\n", udata);
819
820 if (fail_cnt++ > 10)
821 {
822 ULOGE("Utopia",">DVB-C DSP Loadcode fail!");
823 return false;
824 }
825 }
826
827 srcaddr += op;
828 }
829 // printf("\n\n\n");
830 }
831 #endif
832
833 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
834 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
835 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
836 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
837
838 DBG_INTERN_DVBC(ULOGD("Utopia",">DSP Loadcode done."));
839 //while(load_data_variable);
840 #if 0
841 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
842 INTERN_DVBC_Active(ENABLE);
843 while(1);
844 #endif
845 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
846
847 return TRUE;
848 }
849
850 /***********************************************************************************
851 Subject: DVB-T CLKGEN initialized function
852 Function: INTERN_DVBC_Power_On_Initialization
853 Parmeter:
854 Return: MS_BOOL
855 Remark:
856 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)857 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
858 {
859 MS_U8 temp_val;
860 //move to drvSYS MS_U8 tmp;
861 // MS_U8 udatatemp = 0x00;
862 /************************************************************************
863 * T10 U01
864 * This bit0 is mux for DMD muc and HK,
865 * bit0: 0:HK can rw bank 0x1120, 1: DMD mcu can rw bank 0x1120;
866 ************************************************************************/
867 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
868 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
869 // CLK_DMDMCU clock setting
870 // [0] disable clock
871 // [1] invert clock
872 // [4:2]
873 // 000:170 MHz(MPLL_DIV_BUf)
874 // 001:160MHz
875 // 010:144MHz
876 // 011:123MHz
877 // 100:108MHz
878 // 101:mem_clcok
879 // 110:mem_clock div 2
880 // 111:select XTAL
881 //HAL_DMD_RIU_WriteByte(0x10331f,0x00);
882 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
883
884 // set parallet ts clock
885 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
886 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
887 // wriu 0x103301 0x06
888 // wriu 0x103300 0x19
889
890
891 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
892 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
893 temp_val|=0x07;
894 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
895
896 HAL_DMD_RIU_WriteByte(0x103300,0x13);
897
898 // enable atsc, DVBTC ts clock
899 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
900 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
901 // wriu 0x103309 0x00
902 // wriu 0x103308 0x00
903
904 HAL_DMD_RIU_WriteByte(0x103309,0x00);
905 HAL_DMD_RIU_WriteByte(0x103308,0x00); //Messi 0x00// Nike
906
907 // enable dvbc adc clock
908 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
909 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
910 // wriu 0x103315 0x00
911 // wriu 0x103314 0x00
912
913 HAL_DMD_RIU_WriteByte(0x103315,0x00);
914 HAL_DMD_RIU_WriteByte(0x103314,0x00);
915
916
917 HAL_DMD_RIU_WriteByte(0x103302,0x01);
918 HAL_DMD_RIU_WriteByte(0x103302,0x00);
919
920 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
921 HAL_DMD_RIU_WriteByte(0x111f28,0x04);
922
923 HAL_DMD_RIU_WriteByte(0x111f03,0x04);
924 HAL_DMD_RIU_WriteByte(0x111f02,0x04);
925
926 HAL_DMD_RIU_WriteByte(0x111f07,0x04);
927 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
928 // enable vif DAC clock
929 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
930 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
931 // wriu 0x10331b 0x00
932 // wriu 0x10331a 0x00
933
934 //HAL_DMD_RIU_WriteByte(0x10331b,0x00);
935 //HAL_DMD_RIU_WriteByte(0x10331a,0x00);
936
937 // Select MPLLDIV2
938 // [0] : reg_atsc_adc_sel_mplldiv2
939 // [1] : reg_atsc_eq_sel_mplldiv2
940 // [2] : reg_eq25_sel_mplldiv3
941 // [3] : reg_p4_cfo_sel_eq25
942 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h14, 2'b01, 16'h0003);
943 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h14, 2'b01, 16'h0003);
944 // wriu 0x112028 0x03
945 // HAL_DMD_RIU_WriteByte(0x111f28,0x04); // Eiffel // Nike MOVE to DMDMCU
946
947
948 // Select MPLLDIV2
949 // [0] : reg_fed_srd_on
950 // [1] : reg_dvbt_new_tdsfo_on
951 // [2] : reg_dvbc_p4_cfo_on
952 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h15, 2'b01, 16'h0001);
953 // wriu 0x111f2a 0x01
954 // HAL_DMD_RIU_WriteByte(0x111f2a,0x01); // Eiffel has, Nike mark
955
956
957 // *** Set register at CLKGEN_DMD
958 // enable atsc clock
959 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
960 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
961 // wriu 0x111f03 0x04
962 // wriu 0x111f02 0x04
963
964 // HAL_DMD_RIU_WriteByte(0x111f03,0x00);
965 // HAL_DMD_RIU_WriteByte(0x111f02,0x00);
966 // HAL_DMD_RIU_WriteByte(0x111f03,0x04); // Eiffle has, Nike mark
967 // HAL_DMD_RIU_WriteByte(0x111f02,0x04); // Eiffle has, Nike mark
968
969 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
970 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
971 // wriu 0x111f05 0x00
972 // wriu 0x111f04 0x00
973
974 // HAL_DMD_RIU_WriteByte(0x111f05,0x00); // Eiffle has, Nike mark
975 // HAL_DMD_RIU_WriteByte(0x111f04,0x00); // Eiffle has, Nike mark
976 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
977 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
978 // wriu 0x111f07 0x04
979 // wriu 0x111f06 0x04
980
981 // HAL_DMD_RIU_WriteByte(0x111f07,0x00);
982 // HAL_DMD_RIU_WriteByte(0x111f06,0x00);
983
984 // HAL_DMD_RIU_WriteByte(0x111f07,0x04); // Eiffle has, Nike mark
985 // HAL_DMD_RIU_WriteByte(0x111f06,0x00); // Eiffle has, Nike mark
986
987 // enable clk_atsc_adcd_sync
988 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
989 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
990 // wriu 0x111f0b 0x00
991 // wriu 0x111f0a 0x00
992
993 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
994 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
995
996 // enable dvbt inner clock
997 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
998 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
999 // wriu 0x111f0d 0x00
1000 // wriu 0x111f0c 0x00
1001
1002 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1003 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1004
1005 // enable dvbt inner clock
1006 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
1007 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
1008 // wriu 0x111f0f 0x00
1009 // wriu 0x111f0e 0x00
1010
1011 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1012 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1013
1014 // enable dvbt inner clock
1015 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
1016 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
1017 // wriu 0x111f11 0x00
1018 // wriu 0x111f10 0x00
1019
1020 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1021 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1022
1023 // enable dvbc outer clock
1024 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
1025 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
1026 // wriu 0x111f13 0x00
1027 // wriu 0x111f12 0x00
1028
1029 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1030 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1031
1032 // enable dvbc inner-c clock
1033 // [11:8]: reg_ckg_dvbtc_innc
1034 // [0] : disable clock
1035 // [1] : invert clock
1036 // [3:2]: Select clock source
1037 // 00: clk_dmdadc
1038 // 01: reserved
1039 // 10: reserved
1040 // 11: DFT_CLK
1041 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1042
1043 // enable dvbc inner-c clock
1044 // [11:8]: reg_ckg_dvbtc_innc
1045 // [0] : disable clock
1046 // [1] : invert clock
1047 // [3:2]: Select clock source
1048 // 00: clk_dmdadc
1049 // 01: reserved
1050 // 10: reserved
1051 // 11: DFT_CLK
1052 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1053 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1054 // wriu 0x111f15 0x00
1055 // wriu 0x111f14 0x00
1056 HAL_DMD_RIU_WriteByte(0x111f15,0x00); // nike has
1057 HAL_DMD_RIU_WriteByte(0x111f14,0x00); // nike has
1058
1059 // enable dvbc eq
1060 // [3:0] : reg_ckg_dvbtc_eq8x
1061 // [0] : disable clock
1062 // [1] : invert clock
1063 // [3:2]: Select clock source
1064 // 00: clk_dmplldiv3_div2
1065 // 01: reserved
1066 // 10: reserved
1067 // 11: DFT_CLK
1068 // [12:8]: reg_ckg_dvbtc_eq
1069 // [0] : disable clock
1070 // [1] : invert clock
1071 // [3:2]: Select clock source
1072 // 00: clk_dmplldiv3_div16
1073 // 01: reserved
1074 // 10: reserved
1075 // 11: DFT_CLK
1076 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1077 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1078 // wriu 0x111f17 0x00
1079 // wriu 0x111f16 0x00
1080 HAL_DMD_RIU_WriteByte(0x111f17,0x00); // nike has
1081 HAL_DMD_RIU_WriteByte(0x111f16,0x00); // nike has
1082
1083 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1084 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1085
1086
1087 // [9:8] : reg_ckg_adc1x_eq1x
1088 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1089 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b10, 16'h0000);
1090 // wriu 0x111f49 0x00
1091 HAL_DMD_RIU_WriteByte(0x111f49,0x00); // Eiffel for power4CFO open clock
1092 HAL_DMD_RIU_WriteByte(0x111f48,0x00); // Eiffel for power4CFO open clock
1093 // enable sram clock
1094 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1095 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1096 // wriu 0x111f19 0x00
1097 // wriu 0x111f18 0x00
1098
1099 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1100 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1101
1102 HAL_DMD_RIU_WriteByte(0x111f4c,0x11);
1103 // enable vif clock
1104 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1105 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1106 // wriu 0x111f1d 0x00
1107 // wriu 0x111f1c 0x00
1108
1109 //HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1110 //HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1111
1112 // enable DEMODE-DMA clock
1113 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1114 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1115 // wriu 0x111f21 0x00
1116 // wriu 0x111f20 0x00
1117
1118 //HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1119 //HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1120 // select clock
1121 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1122 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1123 // wriu 0x111f23 0x04
1124 // wriu 0x111f22 0x44
1125 // HAL_DMD_RIU_WriteByte(0x111f23,0x00);
1126 // HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1127
1128 // select clock
1129 // [3:0] : reg_ckg_frontend
1130 // [0] : disable clock
1131 // [1] : invert clock
1132 // [3:2]: Select clock source
1133 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
1134 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1135 // 10: reserved
1136 // 11: select DFT_CLK
1137 // [7:4] : reg_ckg_tr
1138 // [0] : disable clock
1139 // [1] : invert clock
1140 // [3:2]: Select clock source
1141 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
1142 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1143 // 10: reserved
1144 // 11: select DFT_CLK
1145 // [11:8]: reg_ckg_acifir
1146 // [0] : disable clock
1147 // [1] : invert clock
1148 // [3:2]: Select clock source
1149 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
1150 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1151 // 10: clk_dmplldiv10_div2 (43.2 MHz, VIF)
1152 // 11: select DFT_CLK
1153 // [15:12]: reg_ckg_frontend_d2
1154 // [0] : disable clock
1155 // [1] : invert clock
1156 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444); // ???
1157 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1158 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1159
1160
1161 HAL_DMD_RIU_WriteByte(0x111f71,0x14);
1162 HAL_DMD_RIU_WriteByte(0x111f70,0x41);
1163
1164 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1165 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1166
1167 HAL_DMD_RIU_WriteByte(0x111f4f,0x00);
1168
1169 HAL_DMD_RIU_WriteByte(0x111f81,0x00);
1170 HAL_DMD_RIU_WriteByte(0x111f80,0x00);
1171
1172 HAL_DMD_RIU_WriteByte(0x111f83,0x00);
1173 HAL_DMD_RIU_WriteByte(0x111f82,0x00);
1174
1175 HAL_DMD_RIU_WriteByte(0x111f85,0x00);
1176 HAL_DMD_RIU_WriteByte(0x111f84,0x00);
1177
1178 HAL_DMD_RIU_WriteByte(0x111f87,0x00);
1179 HAL_DMD_RIU_WriteByte(0x111f86,0x00);
1180
1181 HAL_DMD_RIU_WriteByte(0x111f8d,0x11);
1182 HAL_DMD_RIU_WriteByte(0x111f8c,0x01);
1183
1184 HAL_DMD_RIU_WriteByte(0x111f8f,0x00);
1185 HAL_DMD_RIU_WriteByte(0x111f8e,0x41);
1186
1187
1188 // Turn on New symbol rate detection
1189 // [3] : reg_dvbt_new_tdsfo_on
1190 // [2] : reg_fed_srd_on
1191 // `M3_RIU_W( (`RIUBASE_DMD_TOP_M3>>1)+7'h00, 2'b01, 16'h0004);
1192 // `M3_RIU_W( (`RIUBASE_DMD_TOP_M3>>1)+7'h00, 2'b01, 16'h0004);
1193 // HAL_DMD_RIU_WriteByte(0x112000, 0x04); // Eiffel
1194
1195
1196 // ----------------------------------------------
1197 // start demod CLKGEN setting
1198 // ----------------------------------------------
1199 // select DMD MCU
1200 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1201 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1202 // [0] 0:TOP HK; 1:DMDMCU
1203 // [1] 0:DMDANAQ HK; 1:DMDMCU
1204 // begin BY temp patch
1205 //HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1206 //HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1207 // end
1208 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1209
1210 // ----------------------------------------------
1211 // Turn TSP
1212 // ----------------------------------------------
1213 // set the ts0_clk from demod
1214 // [3:0]: CLK_TS0 clock setting
1215 // [0] : disable
1216 // [1] : invert clock
1217 // [3:2]: Select clock source
1218 // 00: select TS0_CLK
1219 // 01: select TS1_CLK
1220 // 10: reserved
1221 // 11: clk_demod_ts_p
1222 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28 , 2'b11, 16'h000c);
1223
1224 // PWDN_REF_eco => reg_reserve0[10] = 0
1225 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1226 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1227 // swch 3
1228 // wriu 0x000e13 0x01
1229
1230 //HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1231 }
1232
1233 /***********************************************************************************
1234 Subject: Power on initialized function
1235 Function: INTERN_DVBC_Power_On_Initialization
1236 Parmeter:
1237 Return: MS_BOOL
1238 Remark:
1239 ************************************************************************************/
1240
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)1241 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
1242 {
1243 MS_U8 status = true;
1244 DBG_INTERN_DVBC(ULOGD("Utopia","INTERN_DVBC_Power_On_Initialization\n"));
1245
1246 #if defined(PWS_ENABLE)
1247 Mapi_PWS_Stop_VDMCU();
1248 #endif
1249
1250 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1251 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1252 //// Firmware download //////////
1253 DBG_INTERN_DVBC(ULOGD("Utopia","INTERN_DVBC Load DSP...\n"));
1254 //MsOS_DelayTask(100);
1255
1256 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
1257 {
1258 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1259 {
1260 ULOGE("Utopia","DVB-C Load DSP Code Fail\n");
1261 return FALSE;
1262 }
1263 else
1264 {
1265 DBG_INTERN_DVBC(ULOGD("Utopia","DVB-C Load DSP Code OK\n"));
1266 }
1267 }
1268
1269 status &= INTERN_DVBC_Reset();
1270
1271 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1272
1273 return status;
1274 }
1275
1276 /************************************************************************************************
1277 Subject: Driving control
1278 Function: INTERN_DVBC_Driving_Control
1279 Parmeter: bInversionEnable : TRUE For High
1280 Return: void
1281 Remark:
1282 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1283 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1284 {
1285 MS_U8 u8Temp;
1286
1287 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1288
1289 if (bEnable)
1290 {
1291 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1292 }
1293 else
1294 {
1295 u8Temp = u8Temp & (~0x01);
1296 }
1297
1298 DBG_INTERN_DVBC(ULOGD("Utopia","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1299 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1300 }
1301 /************************************************************************************************
1302 Subject: Clk Inversion control
1303 Function: INTERN_DVBC_Clk_Inversion_Control
1304 Parmeter: bInversionEnable : TRUE For Inversion Action
1305 Return: void
1306 Remark:
1307 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1308 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1309 {
1310 MS_U8 u8Temp;
1311
1312 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1313
1314 if (bInversionEnable)
1315 {
1316 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1317 }
1318 else
1319 {
1320 u8Temp = u8Temp & (~0x02);
1321 }
1322
1323 DBG_INTERN_DVBC(ULOGD("Utopia","---> Inversion(Bit9) = 0x%x \n",u8Temp));
1324 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1325 }
1326 /************************************************************************************************
1327 Subject: Transport stream serial/parallel control
1328 Function: INTERN_DVBC_Serial_Control
1329 Parmeter: bEnable : TRUE For serial
1330 Return: MS_BOOL :
1331 Remark:
1332 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1333 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1334 {
1335 MS_U8 status = true;
1336 MS_U8 temp_val;
1337 DBG_INTERN_DVBC(ULOGD("Utopia"," @INTERN_DVBC_ts... u8TSClk=%d\n", u8TSClk));
1338
1339 if (u8TSClk == 0xFF) u8TSClk=0x13;
1340 if (bEnable) //Serial mode for TS pad
1341 {
1342 // serial
1343 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1344 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1345
1346 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1347 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1348 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1349 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1350 temp_val|=0x04;
1351 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1352 #else
1353 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1354 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1355 temp_val|=0x07;
1356 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1357 #endif
1358 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1359 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1360
1361 //// INTERN_DVBC TS Control: Serial //////////
1362
1363 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_SERIAL);
1364
1365 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1366 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1367 #else
1368 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1369 #endif
1370 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1371
1372 gsCmdPacketDVBC.param[0] = TS_SERIAL;
1373 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1374 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1375 #else
1376 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1377 #endif
1378 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1379 }
1380 else
1381 {
1382 //parallel
1383 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1384 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1385
1386 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1387 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1388 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1389 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1390 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1391 temp_val|=0x05;
1392 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1393 #else
1394 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1395 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1396 temp_val|=0x07;
1397 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1398 #endif
1399
1400 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1401 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1402
1403 //// INTERN_DVBC TS Control: Parallel //////////
1404
1405 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_PARALLEL);
1406
1407 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1408 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1409 #else
1410 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1411 #endif
1412 //// INTERN_DVBC TS Control: Parallel //////////
1413 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1414
1415 gsCmdPacketDVBC.param[0] = TS_PARALLEL;
1416 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1417 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1418 #else
1419 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1420 #endif
1421 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1422 }
1423
1424 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1425 DBG_INTERN_DVBC(ULOGD("Utopia","---> Inversion(Bit5) = %d \n",0 ));
1426 #else
1427 DBG_INTERN_DVBC(ULOGD("Utopia","---> Inversion(Bit5) = %d \n",1 ));
1428 #endif
1429
1430 INTERN_DVBC_Driving_Control(INTERN_DVBC_DTV_DRIVING_LEVEL);
1431 return status;
1432 }
1433
1434 /************************************************************************************************
1435 Subject: TS1 output control
1436 Function: INTERN_DVBC_PAD_TS1_Enable
1437 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1438 Return: void
1439 Remark:
1440 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1441 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1442 {
1443 DBG_INTERN_DVBC(ULOGD("Utopia"," @INTERN_DVBC_TS1_Enable... \n"));
1444
1445 if(flag) // PAD_TS1 Enable TS CLK PAD
1446 {
1447 //printf("=== TS1_Enable ===\n");
1448 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1449 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1450 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1451 }
1452 else // PAD_TS1 Disable TS CLK PAD
1453 {
1454 //printf("=== TS1_Disable ===\n");
1455 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1456 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1457 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1458 }
1459 }
1460
1461 /************************************************************************************************
1462 Subject: channel change config
1463 Function: INTERN_DVBC_Config
1464 Parmeter: BW: bandwidth
1465 Return: MS_BOOL :
1466 Remark:
1467 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1468 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1469 {
1470
1471 MS_U8 status = true;
1472 MS_U8 reg_symrate_l, reg_symrate_h;
1473 //MS_U16 u16Fc = 0;
1474 MS_U8 temp_val;
1475 // force
1476 // u16SymbolRate = 0;
1477 // eQamMode = DMD_DVBC_QAMAUTO;
1478
1479 //pu16_symbol_rate_list = pu16_symbol_rate_list;
1480 //u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1481
1482 DBG_INTERN_DVBC(ULOGD("Utopia"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk));
1483 DBG_INTERN_DVBC_TIME(ULOGD("Utopia","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime()));
1484
1485 if (u8TSClk == 0xFF) u8TSClk=0x13;
1486
1487 /*
1488 switch(u32IFFreq)
1489 {
1490 case 36125:
1491 case 36167:
1492 case 36000:
1493 case 6000:
1494 case 4560:
1495 //u16Fc = DVBC_FS - u32IFFreq;
1496 DBG_INTERN_DVBC(ULOGD("Utopia","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1497 break;
1498 case 44000:
1499 default:
1500 ULOGE("Utopia","IF frequency not supported\n");
1501 status = false;
1502 break;
1503 }
1504 */
1505
1506 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1507 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1508
1509 status &= INTERN_DVBC_Reset();
1510
1511 if (eQamMode == DMD_DVBC_QAMAUTO)
1512 {
1513 DBG_INTERN_DVBC(ULOGD("Utopia","DMD_DVBC_QAMAUTO\n"));
1514 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1515 // give default value.
1516 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1517 }
1518 else
1519 {
1520 DBG_INTERN_DVBC(ULOGD("Utopia","DMD_DVBC_QAM %d\n", eQamMode));
1521 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1522 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1523 }
1524 // auto symbol rate enable/disable
1525 if (u16SymbolRate == 0)
1526 {
1527 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1528 }
1529 else
1530 {
1531 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1532 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1533 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1534 MS_U8 indx = 0;
1535 MS_U8 max_len = (E_DMD_DVBC_CFG_BW11_H - E_DMD_DVBC_CFG_BW0_L + 1)/2;
1536
1537 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1538
1539 if (max_len < u8_symbol_rate_list_num)
1540 {
1541 ULOGE("Utopia","[a1_dvbc]Error!!! %s, %s, %d, max_len < u8_symbol_rate_list_num\n",__FILE__,__FUNCTION__,__LINE__);
1542
1543 // Force dvbc unlock.
1544 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, 0x01);
1545 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, 0x00);
1546 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW1_L, 0x00);
1547 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW1_H, 0x00);
1548 }
1549 else if (u8_symbol_rate_list_num == 0)
1550 {
1551 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1552 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1553 }
1554 else
1555 {
1556 for (indx = 0; indx < max_len ; indx++)
1557 {
1558 if (indx < u8_symbol_rate_list_num)
1559 {
1560 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2, (MS_U8)pu16_symbol_rate_list[indx]);
1561 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2 + 1, (MS_U8)(pu16_symbol_rate_list[indx]>>8));
1562 }
1563 else
1564 {
1565 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2, 0x00);
1566 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2 + 1, 0x00);
1567 }
1568 }
1569 }
1570 }
1571 // TS mode
1572 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1573
1574 // IQ Swap
1575 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1576
1577 // Fc
1578 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1579 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1580 // Lif
1581 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1582 // Fif
1583 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1584 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1585
1586 //// INTERN_DVBC system init: DVB-C //////////
1587 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1588
1589 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1590 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1591
1592 if (bSerialTS)
1593 {
1594 // serial
1595 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1596 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1597
1598 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1599 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1600 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1601 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1602 temp_val|=0x04;
1603 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1604 #else
1605 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1606 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1607 temp_val|=0x07;
1608 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1609 #endif
1610 }
1611 else
1612 {
1613 //parallel
1614 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1615 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1616
1617 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1618 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1619 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1620 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1621 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1622 temp_val|=0x05;
1623 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1624 #else
1625 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1626 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1627 temp_val|=0x07;
1628 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1629 #endif
1630 }
1631 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1632 INTERN_DVBC_Show_Demod_Version();
1633 #endif
1634
1635 return status;
1636 }
1637 /************************************************************************************************
1638 Subject: enable hw to lock channel
1639 Function: INTERN_DVBC_Active
1640 Parmeter: bEnable
1641 Return: MS_BOOL
1642 Remark:
1643 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1644 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1645 {
1646 MS_U8 status = true;
1647
1648 DBG_INTERN_DVBC(ULOGD("Utopia"," @INTERN_DVBC_active\n"));
1649
1650 //// INTERN_DVBC Finite State Machine on/off //////////
1651 #if 0
1652 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1653
1654 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1655 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1656 #else
1657 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1658 #endif
1659
1660 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1661 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1662 return status;
1663 }
1664
1665
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)1666 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1667 {
1668 MS_U16 u16Address = 0;
1669 MS_U8 cData = 0;
1670 MS_U8 cBitMask = 0;
1671
1672 if (fCurrRFPowerDbm < 100.0f)
1673 {
1674 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1675 {
1676 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1677 if (cData > 5)
1678 {
1679 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1680 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1681 }
1682 else
1683 {
1684 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
1685 {
1686 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1687 }
1688 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1689 {
1690 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1691 #ifdef MS_DEBUG
1692 ULOGD("Utopia","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1693 #endif
1694 return TRUE;
1695 }
1696 }
1697 #ifdef MS_DEBUG
1698 ULOGD("Utopia","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1699 #endif
1700 }
1701 }
1702
1703 {
1704 switch( eType )
1705 {
1706 case DMD_DVBC_GETLOCK_FEC_LOCK:
1707 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1708 #if (INTERN_DVBC_INTERNAL_DEBUG)
1709 INTERN_DVBC_info();
1710 #endif
1711 DBG_INTERN_DVBC(ULOGD("Utopia"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData));
1712 if (cData == 0x0C)
1713 {
1714 if(g_dvbc_lock == 0)
1715 {
1716 g_dvbc_lock = 1;
1717 DBG_INTERN_DVBC(ULOGD("Utopia","[T12][DVBC]lock++++\n"));
1718
1719 }
1720 return TRUE;
1721 }
1722 else
1723 {
1724 if(g_dvbc_lock == 1)
1725 {
1726 g_dvbc_lock = 0;
1727 DBG_INTERN_DVBC(ULOGD("Utopia","[T12][DVBC]unlock----\n"));
1728 }
1729 return FALSE;
1730 }
1731 break;
1732
1733 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1734 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1735 cBitMask = BIT(1);
1736 break;
1737
1738 case DMD_DVBC_GETLOCK_DCR_LOCK:
1739 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1740 cBitMask = BIT(0);
1741 break;
1742
1743 case DMD_DVBC_GETLOCK_AGC_LOCK:
1744 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1745 cBitMask = BIT(0);
1746 break;
1747
1748 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1749 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1750 cBitMask = BIT(2)|BIT(3)|BIT(4);
1751 #ifdef MS_DEBUG
1752 {
1753 MS_U8 reg_frz=0, FSM=0;
1754 MS_U16 u16Timer=0;
1755 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1756 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1757 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1758 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1759 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1760 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1761 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1762 u16Timer=(u16Timer<<8)+reg_frz;
1763 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1764 u16Timer=(u16Timer<<8)+reg_frz;
1765 ULOGD("Utopia","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1766 }
1767 #endif
1768 break;
1769
1770 case DMD_DVBC_GETLOCK_ATV_DETECT:
1771 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1772 cBitMask = BIT(1); // check atv
1773 break;
1774
1775 case DMD_DVBC_GETLOCK_TR_LOCK:
1776 #if 0 // 20111108 temporarily solution
1777 u16Address = INNC_REG_BASE + 0x50; //TR lock indicator,
1778 cBitMask = BIT(0);
1779 break;
1780 #endif
1781 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1782 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1783 cBitMask = BIT(4);
1784 break;
1785
1786 default:
1787 return FALSE;
1788 }
1789
1790 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1791 return FALSE;
1792
1793 if ((cData & cBitMask) != 0)
1794 {
1795 return TRUE;
1796 }
1797
1798 return FALSE;
1799 }
1800
1801 return FALSE;
1802 }
1803
1804
1805 /****************************************************************************
1806 Subject: To get the Post viterbi BER
1807 Function: INTERN_DVBC_GetPostViterbiBer
1808 Parmeter: Quility
1809 Return: E_RESULT_SUCCESS
1810 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1811 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1812 We will not read the Period, and have the "/256/8"
1813 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1814 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber)
1815 {
1816 MS_BOOL status = true;
1817 MS_U8 reg = 0, reg_frz = 0;
1818 MS_U16 BitErrPeriod;
1819 MS_U32 BitErr;
1820 MS_U16 PktErr;
1821
1822 /////////// Post-Viterbi BER /////////////
1823
1824 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1826 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1827
1828 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1829 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1830 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1831 BitErrPeriod = reg;
1832
1833 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1834 BitErrPeriod = (BitErrPeriod << 8)|reg;
1835
1836 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1837 // 0x6b [15:8] reg_bit_err_num_15_8
1838 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1839 // 0x6d [15:8] reg_bit_err_num_31_24
1840 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1841 BitErr = reg;
1842
1843 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1844 BitErr = (BitErr << 8)|reg;
1845
1846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1847 BitErr = (BitErr << 8)|reg;
1848
1849 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1850 BitErr = (BitErr << 8)|reg;
1851
1852 INTERN_DVBC_GetPacketErr(&PktErr);
1853
1854 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1855 reg_frz=reg_frz&(~0x03);
1856 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1857
1858 if (BitErrPeriod == 0 ) //protect 0
1859 BitErrPeriod = 1;
1860
1861 if (BitErr <=0 )
1862 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1863 else
1864 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1865
1866 DBG_GET_SIGNAL_DVBC(ULOGD("Utopia","INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1867
1868 return status;
1869 }
1870
1871
1872 /****************************************************************************
1873 Subject: To get the Packet error
1874 Function: INTERN_DVBC_GetPacketErr
1875 Parmeter: pktErr
1876 Return: E_RESULT_SUCCESS
1877 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1878 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1879 We will not read the Period, and have the "/256/8"
1880 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1881 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1882 {
1883 MS_BOOL status = true;
1884 MS_U8 reg = 0, reg_frz = 0;
1885 MS_U16 PktErr;
1886
1887 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1888 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1889 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1890
1891 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1892 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1894 PktErr = reg;
1895
1896 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1897 PktErr = (PktErr << 8)|reg;
1898
1899 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1900 reg_frz=reg_frz&(~0x03);
1901 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1902
1903 DBG_GET_SIGNAL_DVBC(ULOGD("Utopia","INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1904
1905 *pktErr = PktErr;
1906
1907 return status;
1908 }
1909
1910 /****************************************************************************
1911 Subject: Read the signal to noise ratio (SNR)
1912 Function: INTERN_DVBC_GetSNR
1913 Parmeter: None
1914 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1915 Remark:
1916 *****************************************************************************/
INTERN_DVBC_GetSNR(float * f_snr)1917 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr)
1918 {
1919 MS_BOOL status = true;
1920 MS_U8 u8Data = 0;
1921 // MS_U8 freeze = 0;
1922 MS_U16 noisepower = 0;
1923
1924 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1925 {
1926 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1927 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x20);
1928 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80);
1929 // read vk
1930 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45, &u8Data);
1931 noisepower = u8Data;
1932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44, &u8Data);
1933 noisepower = (noisepower<<8)|u8Data;
1934
1935 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1936 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x00);
1937 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00);
1938
1939 if(noisepower == 0x0000)
1940 noisepower = 0x0001;
1941
1942 #ifdef MSOS_TYPE_LINUX
1943 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1944 #else
1945 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1946 #endif
1947
1948 }
1949 else
1950 {
1951 *f_snr = 0.0f;
1952 }
1953 return status;
1954
1955
1956 }
1957
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1958 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1959 {
1960 MS_BOOL status = true;
1961 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1962 DMD_DVBC_MODULATION_TYPE Qam_mode;
1963
1964 DBG_INTERN_DVBC_TIME(ULOGD("Utopia","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi)));
1965
1966 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1967 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1968 /* Actually, it's more reasonable, that signal level depended on cable input power level
1969 * thougth the signal isn't dvb-t signal.
1970 */
1971 // use pointer of IFAGC table to identify
1972 // case 1: RFAGC from SAR, IFAGC controlled by demod
1973 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1974 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1975 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
1976 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1977 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1978 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
1979 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
1980
1981 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
1982
1983 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
1984 {
1985 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
1986 }
1987 else
1988 {
1989 ch_power_db_rel = -100.0f;
1990 }
1991
1992 if(ch_power_db_rel <= -85.0f)
1993 {*strength = 0;}
1994 else if (ch_power_db_rel <= -80.0f)
1995 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
1996 else if (ch_power_db_rel <= -75.0f)
1997 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
1998 else if (ch_power_db_rel <= -70.0f)
1999 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
2000 else if (ch_power_db_rel <= -65.0f)
2001 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
2002 else if (ch_power_db_rel <= -55.0f)
2003 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
2004 else if (ch_power_db_rel <= -45.0f)
2005 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
2006 else
2007 {*strength = 100;}
2008
2009 DBG_GET_SIGNAL_DVBC(ULOGD("Utopia",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2010 DBG_GET_SIGNAL_DVBC(ULOGD("Utopia",">>> SSI = %d <<<\n", (int)*strength));
2011
2012 return status;
2013 }
2014
2015 /****************************************************************************
2016 Subject: To get the DVT Signal quility
2017 Function: INTERN_DVBC_GetSignalQuality
2018 Parmeter: Quility
2019 Return: E_RESULT_SUCCESS
2020 E_RESULT_FAILURE
2021 Remark: Here we have 4 level range
2022 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2023 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2024 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2025 <4>.4th Range => Quality <10
2026 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(MS_U16 * quality,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2027 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2028 {
2029
2030 float fber;
2031 float log_ber;
2032 MS_BOOL status = true;
2033 DMD_DVBC_MODULATION_TYPE Qam_mode;
2034 float f_snr;
2035
2036 fRFPowerDbm = fRFPowerDbm;
2037 status &= INTERN_DVBC_GetSNR(&f_snr);
2038 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
2039 {
2040 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
2041 {
2042 DBG_INTERN_DVBC(ULOGE("Utopia","\nGetPostViterbiBer Fail!"));
2043 return FALSE;
2044 }
2045
2046 // log_ber = log10(fber)
2047 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
2048
2049 DBG_INTERN_DVBC(ULOGD("Utopia","\nLog(BER) = %f",log_ber));
2050 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2051 if (Qam_mode == DMD_DVBC_QAM16)
2052 {
2053 if(log_ber <= (-5.5f))
2054 *quality = 100;
2055 else if(log_ber <= (-5.1f))
2056 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
2057 else if(log_ber <= (-4.9f))
2058 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2059 else if(log_ber <= (-4.5f))
2060 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
2061 else if(log_ber <= (-3.7f))
2062 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
2063 else if(log_ber <= (-3.2f))
2064 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2065 else if(log_ber <= (-2.9f))
2066 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2067 else if(log_ber <= (-2.5f))
2068 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
2069 else if(log_ber <= (-2.2f))
2070 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
2071 else if(log_ber <= (-2.0f))
2072 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2073 else
2074 *quality = 0;
2075 }
2076 else if (Qam_mode == DMD_DVBC_QAM32)
2077 {
2078 if(log_ber <= (-5.0f))
2079 *quality = 100;
2080 else if(log_ber <= (-4.7f))
2081 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
2082 else if(log_ber <= (-4.5f))
2083 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
2084 else if(log_ber <= (-3.8f))
2085 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
2086 else if(log_ber <= (-3.5f))
2087 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
2088 else if(log_ber <= (-3.0f))
2089 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
2090 else if(log_ber <= (-2.7f))
2091 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
2092 else if(log_ber <= (-2.4f))
2093 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2094 else if(log_ber <= (-2.2f))
2095 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2096 else if(log_ber <= (-2.0f))
2097 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2098 else
2099 *quality = 0;
2100 }
2101 else if (Qam_mode == DMD_DVBC_QAM64)
2102 {
2103 if(log_ber <= (-5.4f))
2104 *quality = 100;
2105 else if(log_ber <= (-5.1f))
2106 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
2107 else if(log_ber <= (-4.9f))
2108 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2109 else if(log_ber <= (-4.3f))
2110 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
2111 else if(log_ber <= (-3.7f))
2112 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
2113 else if(log_ber <= (-3.2f))
2114 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2115 else if(log_ber <= (-2.9f))
2116 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2117 else if(log_ber <= (-2.4f))
2118 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
2119 else if(log_ber <= (-2.2f))
2120 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2121 else if(log_ber <= (-2.05f))
2122 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
2123 else
2124 *quality = 0;
2125 }
2126 else if (Qam_mode == DMD_DVBC_QAM128)
2127 {
2128 if(log_ber <= (-5.1f))
2129 *quality = 100;
2130 else if(log_ber <= (-4.9f))
2131 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2132 else if(log_ber <= (-4.7f))
2133 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
2134 else if(log_ber <= (-4.1f))
2135 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
2136 else if(log_ber <= (-3.5f))
2137 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
2138 else if(log_ber <= (-3.1f))
2139 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2140 else if(log_ber <= (-2.7f))
2141 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2142 else if(log_ber <= (-2.5f))
2143 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
2144 else if(log_ber <= (-2.06f))
2145 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
2146 //else if(log_ber <= (-2.05))
2147 else
2148 {
2149 if (f_snr >= 27.2f)
2150 *quality = 20;
2151 else if (f_snr >= 25.1f)
2152 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
2153 else
2154 *quality = 0;
2155 }
2156 }
2157 else //256QAM
2158 {
2159 if(log_ber <= (-4.8f))
2160 *quality = 100;
2161 else if(log_ber <= (-4.6f))
2162 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
2163 else if(log_ber <= (-4.4f))
2164 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
2165 else if(log_ber <= (-4.0f))
2166 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
2167 else if(log_ber <= (-3.5f))
2168 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
2169 else if(log_ber <= (-3.1f))
2170 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2171 else if(log_ber <= (-2.7f))
2172 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2173 else if(log_ber <= (-2.4f))
2174 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2175 else if(log_ber <= (-2.06f))
2176 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
2177 //else if(log_ber <= (-2.05))
2178 else
2179 {
2180 if (f_snr >= 29.6f)
2181 *quality = 20;
2182 else if (f_snr >= 27.3f)
2183 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
2184 else
2185 *quality = 0;
2186 }
2187 }
2188 }
2189 else
2190 {
2191 *quality = 0;
2192 }
2193
2194 //DBG_GET_SIGNAL_DVBC(ULOGD("Utopia","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2195 DBG_GET_SIGNAL_DVBC(ULOGD("Utopia","BER = %8.3e\n", fber));
2196 DBG_GET_SIGNAL_DVBC(ULOGD("Utopia","Signal Quility = %d\n", *quality));
2197 return TRUE;
2198 }
2199
2200 /****************************************************************************
2201 Subject: To get the Cell ID
2202 Function: INTERN_DVBC_Get_CELL_ID
2203 Parmeter: point to return parameter cell_id
2204
2205 Return: TRUE
2206 FALSE
2207 Remark:
2208 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)2209 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
2210 {
2211 MS_BOOL status = true;
2212 MS_U8 value1 = 0;
2213 MS_U8 value2 = 0;
2214
2215 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
2216 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
2217
2218 *cell_id = ((MS_U16)value1<<8)|value2;
2219 return status;
2220 }
2221
2222 /****************************************************************************
2223 Subject: To get the DVBC Carrier Freq Offset
2224 Function: INTERN_DVBC_Get_FreqOffset
2225 Parmeter: Frequency offset (in KHz), bandwidth
2226 Return: E_RESULT_SUCCESS
2227 E_RESULT_FAILURE
2228 Remark:
2229 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2230 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2231 {
2232 MS_U16 FreqB, config_Fc=0;
2233 float FreqCfo_offset,f_Fc;
2234 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
2235 MS_U8 reg = 0;
2236 MS_BOOL status = TRUE;
2237
2238 // no use.
2239 u8BW = u8BW;
2240
2241 DBG_INTERN_DVBC(ULOGD("Utopia","INTERN_DVBC_Get_FreqOffset\n"));
2242
2243 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2244 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x20);
2245 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80);
2246
2247 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, ®);
2248 RegCfo_offset = reg;
2249 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, ®);
2250 RegCfo_offset = (RegCfo_offset<<8)|reg;
2251 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, ®);
2252 RegCfo_offset = (RegCfo_offset<<8)|reg;
2253 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, ®);
2254 RegCfo_offset = (RegCfo_offset<<8)|reg;
2255
2256 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2257 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x00);
2258 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00);
2259
2260 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
2261 Reg_Fc_over_Fs = reg;
2262 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
2263 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2264 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
2265 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2266 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
2267 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2268
2269 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
2270 config_Fc = reg;
2271 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
2272 config_Fc = (config_Fc<<8)|reg;
2273
2274 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
2275
2276 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
2277
2278 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
2279
2280 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
2281
2282 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
2283 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
2284 FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc));
2285
2286 *pFreqOff = FreqCfo_offset;
2287
2288 return status;
2289 }
2290
2291
2292
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)2293 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
2294 {
2295
2296 bPowerOn = bPowerOn;
2297 }
2298
INTERN_DVBC_Power_Save(void)2299 MS_BOOL INTERN_DVBC_Power_Save(void)
2300 {
2301
2302 return TRUE;
2303 }
2304
2305 /****************************************************************************
2306 Subject: To get the current modulation type at the DVB-C Demod
2307 Function: INTERN_DVBC_GetCurrentModulationType
2308 Parmeter: pointer for return QAM type
2309
2310 Return: TRUE
2311 FALSE
2312 Remark:
2313 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)2314 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
2315 {
2316 MS_U8 u8Data=0;
2317
2318 DBG_INTERN_DVBC(ULOGD("Utopia","INTERN_DVBC_GetCurrentModulationType\n"));
2319
2320 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &u8Data);
2321
2322 switch(u8Data&0x07)
2323 {
2324 case 0:
2325 *pQAMMode = DMD_DVBC_QAM16;
2326 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]QAM=16\n"));
2327 return TRUE;
2328 break;
2329 case 1:
2330 *pQAMMode = DMD_DVBC_QAM32;
2331 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]QAM=32\n"));
2332 return TRUE;
2333 break;
2334 case 2:
2335 *pQAMMode = DMD_DVBC_QAM64;
2336 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]QAM=64\n"));
2337 return TRUE;
2338 break;
2339 case 3:
2340 *pQAMMode = DMD_DVBC_QAM128;
2341 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]QAM=128\n"));
2342 return TRUE;
2343 break;
2344 case 4:
2345 *pQAMMode = DMD_DVBC_QAM256;
2346 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]QAM=256\n"));
2347 return TRUE;
2348 break;
2349 default:
2350 *pQAMMode = DMD_DVBC_QAMAUTO;
2351 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]QAM=invalid\n"));
2352 return FALSE;
2353 }
2354 }
2355
2356 /****************************************************************************
2357 Subject: To get the current symbol rate at the DVB-C Demod
2358 Function: INTERN_DVBC_GetCurrentSymbolRate
2359 Parmeter: pointer pData for return Symbolrate
2360
2361 Return: TRUE
2362 FALSE
2363 Remark:
2364 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2365 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2366 {
2367 MS_U8 tmp = 0;
2368 MS_U16 u16SymbolRateTmp = 0;
2369
2370 // intp
2371 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd2, &tmp);
2372 u16SymbolRateTmp = tmp;
2373 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd1, &tmp);
2374 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2375
2376 if (abs(u16SymbolRateTmp-6900)<2)
2377 {
2378 u16SymbolRateTmp=6900;
2379 }
2380
2381 if (abs(u16SymbolRateTmp-6875)<2)
2382 {
2383 u16SymbolRateTmp=6875;
2384 }
2385
2386 *u16SymbolRate = u16SymbolRateTmp;
2387
2388 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]SR=%d\n",*u16SymbolRate));
2389
2390 return TRUE;
2391 }
2392
2393
2394 /****************************************************************************
2395 Subject: To get the current symbol rate offset at the DVB-C Demod
2396 Function: INTERN_DVBC_GetCurrentSymbolRate
2397 Parmeter: pointer pData for return Symbolrate offset
2398
2399 Return: TRUE
2400 FALSE
2401 Remark:
2402 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)2403 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2404 {
2405 MS_U8 u8Data = 0;
2406 MS_U32 u32Data = 0;
2407 // MS_S32 s32Data = 0;
2408 MS_BOOL status = TRUE;
2409 MS_U16 u16SymbolRate = 0;
2410 float f_symb_offset = 0.0f;
2411
2412
2413 // bank 26 0x03 [7] reg_bit_err_num_freeze
2414 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3A, 0x00);
2415 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x4A, 0x00);
2416 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x05, 0x80);
2417
2418 // sel, SFO debug output.
2419 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4E, &u8Data);
2420 u32Data = u8Data;
2421 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4D, &u8Data);
2422 u32Data = (u32Data<<8)|u8Data;
2423 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4C, &u8Data);
2424 u32Data = (u32Data<<8)|u8Data;
2425
2426 // bank 26 0x03 [7] reg_bit_err_num_freeze
2427 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x05, 0x00);
2428 // s32Data = (MS_S32)(u32Data<<8);
2429
2430 ULOGD("Utopia","[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2431
2432 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2433 if (u32Data >= 0x800000)
2434 {
2435 u32Data = 0x1000000 - u32Data;
2436 f_symb_offset = -1.0f*(float)u32Data * 0.003725f * (float)u16SymbolRate/(float)DVBC_FS;
2437 }
2438 else
2439 {
2440 f_symb_offset = (float)u32Data * 0.003725f * (float)u16SymbolRate/(float)DVBC_FS;
2441 }
2442
2443 *pData = (MS_U16)(f_symb_offset + 0.5f);
2444
2445 DBG_INTERN_DVBC_LOCK(ULOGD("Utopia","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset));
2446
2447 return status;
2448 }
2449
INTERN_DVBC_Version(MS_U16 * ver)2450 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2451 {
2452
2453 MS_U8 status = true;
2454 MS_U8 tmp = 0;
2455 MS_U16 u16_INTERN_DVBC_Version;
2456
2457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2458 u16_INTERN_DVBC_Version = tmp;
2459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2460 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2461 *ver = u16_INTERN_DVBC_Version;
2462
2463 return status;
2464 }
2465
2466
INTERN_DVBC_Show_Demod_Version(void)2467 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2468 {
2469
2470 MS_BOOL status = true;
2471 MS_U16 u16_INTERN_DVBC_Version;
2472
2473 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2474
2475 ULOGD("Utopia","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2476
2477 return status;
2478 }
2479
2480
2481
2482
2483
INTERN_DVBC_Show_AGC_Info(void)2484 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2485 {
2486 MS_U8 tmp = 0;
2487 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2488 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2489 MS_U16 if_agc_err = 0;
2490 MS_BOOL status = TRUE;
2491
2492 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2493 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2495 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2496 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2498
2499
2500 // select IF gain to read
2501 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2502 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2503
2504 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2505 if_agc_gain = tmp;
2506 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2507 if_agc_gain = (if_agc_gain<<8)|tmp;
2508
2509
2510 // select d1 gain to read.
2511 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2512 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2513
2514 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2515 d1_gain = tmp;
2516 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2517 d1_gain = (d1_gain<<8)|tmp;
2518
2519 // select d2 gain to read.
2520 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2521 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2522
2523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2524 d2_gain = tmp;
2525 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2526 d2_gain = (d2_gain<<8)|tmp;
2527
2528 // select IF gain err to read
2529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2530 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2531
2532 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2533 if_agc_err = tmp;
2534 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2535 if_agc_err = (if_agc_err<<8)|tmp;
2536
2537 DBG_INTERN_DVBC(ULOGD("Utopia","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2538 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref));
2539
2540 DBG_INTERN_DVBC(ULOGD("Utopia","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err));
2541
2542 return status;
2543 }
2544
INTERN_DVBC_info(void)2545 void INTERN_DVBC_info(void)
2546 {
2547 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2548 MS_U8 qam,tmp = 0;
2549 MS_U8 fft_u8 = 0;
2550 MS_U16 fft_u16bw = 0;
2551 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2552 float f_snr = 0,f_freq = 0;
2553 DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2554 MS_U16 f_start = 0,f_end = 0;
2555 MS_U8 s0_count = 0;
2556 MS_U8 sc4 = 0,sc3 = 0;
2557 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2558 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2559 MS_U16 count = 0;
2560 MS_U16 fb_i_1,fb_q_1;
2561 MS_U8 e0 = 0,e1 = 0,e2 = 0,e3 = 0 ;
2562 MS_S16 reg_freq;
2563 float freq,mag;
2564
2565
2566
2567 INTERN_DVBC_Version(&version);
2568
2569 // fb_fs
2570 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2571 fb_fs = tmp;
2572 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2573 fb_fs = (fb_fs<<8)|tmp;
2574 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2575 fb_fs = (fb_fs<<8)|tmp;
2576 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2577 fb_fs = (fb_fs<<8)|tmp;
2578 // fc_fs
2579 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2580 fc_fs = tmp;
2581 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2582 fc_fs = (fc_fs<<8)|tmp;
2583 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2584 fc_fs = (fc_fs<<8)|tmp;
2585 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2586 fc_fs = (fc_fs<<8)|tmp;
2587 // crv
2588 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2589 crv = tmp;
2590 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2591 crv = (crv<<8)|tmp;
2592 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2593 crv = (crv<<8)|tmp;
2594 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2595 crv = (crv<<8)|tmp;
2596 // tr_error
2597 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2598 tr_error = tmp;
2599 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2600 tr_error = (tr_error<<8)|tmp;
2601 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2602 tr_error = (tr_error<<8)|tmp;
2603
2604 // intp
2605 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2606 intp = tmp;
2607 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2608 intp = (intp<<8)|tmp;
2609 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2610 intp = (intp<<8)|tmp;
2611 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2612 intp = (intp<<8)|tmp;
2613
2614 // fft info
2615 // intp
2616 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2617 fft_u16bw = tmp;
2618 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2619 fft_u16bw = (fft_u16bw<<8)|tmp;
2620 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2621 fft_u8 = tmp;
2622
2623
2624 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2625 qam = tmp;
2626
2627 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2628 f_start = tmp;
2629 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2630 f_start = (f_start<<8)|tmp;
2631 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2632 f_end = tmp;
2633 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2634 f_end = (f_end<<8)|tmp;
2635 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2636 s0_count = tmp;
2637
2638 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2639 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2640
2641 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2642 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2643 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2644 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2645 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2646 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2647 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2648
2649
2650 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2651
2652 count = 0x400;
2653 while(count--);
2654
2655 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2656 aci_e0 = tmp&0x0f;
2657 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2658 aci_e0 = aci_e0<<8|tmp;
2659
2660 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2661
2662 count = 0x400;
2663 while(count--);
2664
2665
2666 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2667 aci_e1 = tmp&0x0f;
2668 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2669 aci_e1 = aci_e1<<8|tmp;
2670
2671 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2672
2673 count = 0x400;
2674 while(count--);
2675
2676 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2677 aci_e2 = tmp&0x0f;
2678 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2679 aci_e2 = aci_e2<<8|tmp;
2680
2681 // read aci coef
2682 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2683
2684 count = 0x400;
2685 while(count--);
2686
2687 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2688 aci_e3 = tmp&0x0f;
2689 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2690 aci_e3 = aci_e3<<8|tmp;
2691
2692 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2693 fb_i_1 = tmp;
2694 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2695 fb_i_1 = fb_i_1<<8|tmp;
2696
2697 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2698 fb_q_1 = tmp;
2699 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2700 fb_q_1 = fb_q_1<<8|tmp;
2701
2702
2703 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2704 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2705 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2706 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2707
2708 reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2709 freq = (float)reg_freq*45473.0/65536.0;
2710 mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2711
2712
2713 INTERN_DVBC_GetPacketErr(&packetErr);
2714 INTERN_DVBC_GetSNR(&f_snr);
2715 INTERN_DVBC_Show_AGC_Info();
2716 INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2717 INTERN_DVBC_Get_FreqOffset(&f_freq,8);
2718 INTERN_DVBC_GetCurrentSymbolRate(&symb_rate);
2719 INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2720 INTERN_DVBC_GetCurrentModulationType(&QAMMode);
2721
2722 DBG_INTERN_DVBC(ULOGD("Utopia","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr));
2723 DBG_INTERN_DVBC(ULOGD("Utopia","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr));
2724 DBG_INTERN_DVBC(ULOGD("Utopia","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4));
2725 DBG_INTERN_DVBC(ULOGD("Utopia","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th));
2726 DBG_INTERN_DVBC(ULOGD("Utopia","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th));
2727 DBG_INTERN_DVBC(ULOGD("Utopia","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th));
2728 return;
2729 }
2730
2731
2732
2733
2734 /***********************************************************************************
2735 Subject: read register
2736 Function: MDrv_1210_IIC_Bypass_Mode
2737 Parmeter:
2738 Return:
2739 Remark:
2740 ************************************************************************************/
2741 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2742 //{
2743 // UNUSED(enable);
2744 // if (enable)
2745 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2746 // else
2747 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2748 //}
2749