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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT2.c
98 /// @brief INTERN_DVBT2 DVBT2
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT2_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 //#include "BinInfo.h"
114 #include "drvDMD_VD_MBX.h"
115 #include "drvDMD_INTERN_DVBT2.h"
116 #include "halDMD_INTERN_DVBT2.h"
117 #include "halDMD_INTERN_common.h"
118
119 extern void *memcpy(void *destination, const void *source, size_t num);
120
121 #define TEST_EMBEDED_DEMOD 0
122 //U8 load_data_variable=1;
123 //-----------------------------------------------------------------------
124 #define BIN_ID_INTERN_DVBT2_DEMOD BIN_ID_INTERN_DVBT
125
126 #define TDE_REG_BASE 0x2400
127 #define DIV_REG_BASE 0x2500
128 #define TR_REG_BASE 0x2600
129 #define FTN_REG_BASE 0x2700
130 #define FTNEXT_REG_BASE 0x2800
131
132
133
134 #if 0//ENABLE_SCAN_ONELINE_MSG
135 #define DBG_INTERN_DVBT2_ONELINE(x) x
136 #else
137 #define DBG_INTERN_DVBT2_ONELINE(x) // x
138 #endif
139
140 #ifdef MS_DEBUG
141 #define DBG_INTERN_DVBT2(x) x
142 #define DBG_GET_SIGNAL(x) x
143 #define DBG_INTERN_DVBT2_TIME(x) x
144 #define DBG_INTERN_DVBT2_LOCK(x) x
145 #else
146 #define DBG_INTERN_DVBT2(x) //x
147 #define DBG_GET_SIGNAL(x) //x
148 #define DBG_INTERN_DVBT2_TIME(x) // x
149 #define DBG_INTERN_DVBT2_LOCK(x) //x
150 #endif
151 #define DBG_DUMP_LOAD_DSP_TIME 0
152
153 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0
154 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1
155 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1
156 #define INTERN_DVBT2_INTERNAL_DEBUG 1
157
158 #define SIGNAL_LEVEL_OFFSET 0.00
159 #define TAKEOVERPOINT -59.0
160 #define TAKEOVERRANGE 0.5
161 #define LOG10_OFFSET -0.21
162 #define INTERN_DVBT2_USE_SAR_3_ENABLE 0
163 #define INTERN_DVBT2_GET_TIME msAPI_Timer_GetTime0()
164
165
166 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
167 #define TUNER_VPP 2
168 #define IF_AGC_VPP 2
169 #else
170 #define TUNER_VPP 1
171 #define IF_AGC_VPP 2
172 #endif
173
174 #if (TUNER_VPP == 1)
175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
176 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
178 #endif
179
180 /*BEG INTERN_DVBT2_DSPREG_TABLE*/
181 #define DVBT2_FS 24000
182
183 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
184 #define T2_BW_VAL 0x04
185 // FC: FC = FS = 5000 = 0x1388 (5.0MHz IF)
186 #define T2_FC_L_VAL 0x88 // 5.0M
187 #define T2_FC_H_VAL 0x13
188 #define T2_TS_SERIAL_VAL 0x00
189 #define T2_TS_CLK_RATE_VAL 0x06
190 #define T2_TS_OUT_INV_VAL 0x00
191 #define T2_TS_DATA_SWAP_VAL 0x00
192 #define T2_IF_AGC_INV_PWM_EN_VAL 0x00
193 #define T2_LITE_VAL 0x00
194 #define T2_AGC_REF_VAL 0x40
195
196 #define DVBT2_BER_TH_HY 0.1
197
198 /*END INTERN_DVBT2_DSPREG_TABLE*/
199 //-----------------------------------------------------------------------
200 /****************************************************************
201 *Local Variables *
202 ****************************************************************/
203 static MS_BOOL bFECLock=0;
204 static MS_BOOL bP1Lock = 0;
205 static MS_U32 u32ChkScanTimeStart = 0;
206 static MS_U32 u32FecFirstLockTime=0;
207 static MS_U32 u32FecLastLockTime=0;
208 static float fLDPCBerFiltered=-1;
209 static float fBerFilteredDVBT2 = -1.0;
210
211 //Global Variables
212 S_CMDPKTREG gsCmdPacket;
213 //U8 gCalIdacCh0, gCalIdacCh1;
214 extern MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
215 extern MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
216 extern MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
217 extern MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
218 extern MS_U32 u32DMD_DVBT2_FW_START_ADDR;
219
220 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
221 MS_U8 INTERN_DVBT2_table[] = {
222 #include "fwDMD_INTERN_DVBT2.dat"
223 };
224
225 #endif
226 /*
227 static DMD_T2_SSI_DBM_NORDIGP1 dvbt2_ssi_dbm_nordigp1[] =
228 {
229 {_T2_QPSK, _T2_CR1Y2, -95.7},
230 {_T2_QPSK, _T2_CR3Y5, -94.4},
231 {_T2_QPSK, _T2_CR2Y3, -93.6},
232 {_T2_QPSK, _T2_CR3Y4, -92.6},
233 {_T2_QPSK, _T2_CR4Y5, -92.0},
234 {_T2_QPSK, _T2_CR5Y6, -91.5},
235
236 {_T2_16QAM, _T2_CR1Y2, -90.8},
237 {_T2_16QAM, _T2_CR3Y5, -89.1},
238 {_T2_16QAM, _T2_CR2Y3, -87.9},
239 {_T2_16QAM, _T2_CR3Y4, -86.7},
240 {_T2_16QAM, _T2_CR4Y5, -85.8},
241 {_T2_16QAM, _T2_CR5Y6, -85.2},
242
243 {_T2_64QAM, _T2_CR1Y2, -86.9},
244 {_T2_64QAM, _T2_CR3Y5, -84.6},
245 {_T2_64QAM, _T2_CR2Y3, -83.2},
246 {_T2_64QAM, _T2_CR3Y4, -81.4},
247 {_T2_64QAM, _T2_CR4Y5, -80.3},
248 {_T2_64QAM, _T2_CR5Y6, -79.7},
249
250 {_T2_256QAM, _T2_CR1Y2, -83.5},
251 {_T2_256QAM, _T2_CR3Y5, -80.4},
252 {_T2_256QAM, _T2_CR2Y3, -78.6},
253 {_T2_256QAM, _T2_CR3Y4, -76.0},
254 {_T2_256QAM, _T2_CR4Y5, -74.4},
255 {_T2_256QAM, _T2_CR5Y6, -73.3},
256 {_T2_QAM_UNKNOWN, _T2_CR_UNKNOWN, 0.0}
257 };
258 */
259 static float dvbt2_ssi_dbm_nordigp1[][6] =
260 {
261 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
262 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
263 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
264 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
265 };
266
267 // cr, 3/5(1), 2/3(2), 3/4 (3)
268 float fT2_SSI_formula[][12]=
269 {
270 {1.0/5, 97.0, 3.0/2, 82.0, 16.0/5, 50.0, 29.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/5
271 {2.0/3, 95.0, 9.0/5, 77.0, 17.0/5, 43.0, 14.0/5.0, 15.0, 13.0/15, 2.0, 2.0/5, 0.0}, // CR2/3
272 {1.0/2, 93.0, 19.0/10, 74.0, 31.0/10, 43.0, 22.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/4
273 };
274 static void INTERN_DVBT2_SignalQualityReset(void);
275 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void);
276
INTERN_DVBT2_SignalQualityReset(void)277 static void INTERN_DVBT2_SignalQualityReset(void)
278 {
279 u32FecFirstLockTime=0;
280 fLDPCBerFiltered=-1;
281 }
282
INTERN_DVBT2_DSPReg_Init(const MS_U8 * u8DVBT2_DSPReg,MS_U8 u8Size)283 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT2_DSPReg, MS_U8 u8Size)
284 {
285 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
286 MS_BOOL status = TRUE;
287 MS_U16 u16DspAddr = 0;
288
289 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_DSPReg_Init\n"));
290
291 //for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
292 // status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
293 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_BW, T2_BW_VAL) != TRUE)
294 {
295 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
296 }
297 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_L, T2_FC_L_VAL) != TRUE)
298 {
299 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
300 }
301 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_H, T2_FC_H_VAL) != TRUE)
302 {
303 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
304 }
305 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_SERIAL, T2_TS_SERIAL_VAL) != TRUE)
306 {
307 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
308 }
309 //if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_CLK_RATE, T2_TS_CLK_RATE_VAL) != TRUE)
310 //{
311 // printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
312 //}
313 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_OUT_INV, T2_TS_OUT_INV_VAL) != TRUE)
314 {
315 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
316 }
317 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_SWAP, T2_TS_DATA_SWAP_VAL) != TRUE)
318 {
319 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
320 }
321 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_IF_AGC_INV_PWM_EN, T2_IF_AGC_INV_PWM_EN_VAL) != TRUE)
322 {
323 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
324 }
325 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_LITE, T2_LITE_VAL) != TRUE)
326 {
327 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
328 }
329
330 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_AGC_REF, T2_AGC_REF_VAL) != TRUE) //brown:0x40->agc_ref
331 {
332 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
333 }
334
335 if (u8DVBT2_DSPReg != NULL)
336 {
337 /*temp solution until new dsp table applied.*/
338 // if (INTERN_DVBT2_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
339 if (u8DVBT2_DSPReg[0] >= 1)
340 {
341 u8DVBT2_DSPReg+=2;
342 for (idx = 0; idx<u8Size; idx++)
343 {
344 u16DspAddr = *u8DVBT2_DSPReg;
345 u8DVBT2_DSPReg++;
346 u16DspAddr = (u16DspAddr) + ((*u8DVBT2_DSPReg)<<8);
347 u8DVBT2_DSPReg++;
348 u8Mask = *u8DVBT2_DSPReg;
349 u8DVBT2_DSPReg++;
350 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
351 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT2_DSPReg) & (u8Mask));
352 u8DVBT2_DSPReg++;
353 DBG_INTERN_DVBT2(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
354 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
355 }
356 }
357 else
358 {
359 printf("FATAL: parameter version incorrect\n");
360 }
361 }
362
363 return status;
364 }
365
366 /***********************************************************************************
367 Subject: SoftStop
368 Function: INTERN_DVBT2_SoftStop
369 Parmeter:
370 Return: MS_BOOL
371 Remark:
372 ************************************************************************************/
373
INTERN_DVBT2_SoftStop(void)374 MS_BOOL INTERN_DVBT2_SoftStop ( void )
375 {
376 MS_U16 u8WaitCnt=0;
377 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
378 {
379 printf(">> MB Busy!\n");
380 return FALSE;
381 }
382
383 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
384
385 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
386 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
387
388 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
389 {
390 if (u8WaitCnt++ >= 0xFFF)
391 {
392 printf(">> DVBT2 SoftStop Fail!\n");
393 return FALSE;
394 }
395 }
396
397 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
398 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
399 return TRUE;
400 }
401
INTERN_DVBT2_SoftReset(void)402 MS_BOOL INTERN_DVBT2_SoftReset ( void )
403 {
404 MS_BOOL bRet=TRUE;
405 //MS_U8 u8Data, fdp_fifo_done, djb_fifo_done, tdi_fifo_done;
406 MS_U8 u8Data = 0, fdp_fifo_done = 0, tdi_fifo_done = 0;
407 MS_U8 u8_timeout = 0;
408
409 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_SoftReset\n"));
410
411 //stop FSM_EN
412 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN
413
414 MsOS_DelayTask(5);
415
416 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
417 DBG_INTERN_DVBT2(printf("@@@TOP_RESET:0x%x\n", u8Data));
418 // MIU hold function
419 if((u8Data & 0x20) == 0x00)
420 {
421 // mask miu service with fdp, djb, tdi
422 //fdp 0x17 [12] reg_fdp_fifo_stop=1'b1
423 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
424 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10));
425 // [8] reg_fdp_load, fdp register dynamic change protection, 1->load register
426 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10);
427 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
428 //printf("@@@@@@ DVBT2 [reg_fdp_fifo_stop]=0x%x\n", u8Data);
429 //djb 0x65 [0] reg_stop_mu_request
430 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
431 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01));
432 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
433 //printf("@@@@@@ DVBT2 [reg_stop_mu_request]=0x%x\n", u8Data);
434 //snr 0x23 [8] reg_tdi_miu_off
435 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
436 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01));
437 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
438 //printf("@@@@@@ DVBT2 [reg_tdi_miu_off]=0x%x\n", u8Data);
439 // ---------------------------------------------
440 // Wait MIU mask or timeout!
441 // DVBT2_TIMER_INT[ 7:0] : indicator of the selected Timer's max count(15:8) (r)
442 // DVBT2_TIMER_INT[11:8] : timer3~timer0 interrupt (r)
443 // ---------------------------------------------
444 //fdp 0x18 [2] reg_fdp_fifo_req_done
445 //djb 0x65 [8] reg_miu_req_terminate_done
446 //tdi 0x23 [9] reg_tdi_miu_off_done
447 do
448 {
449 // Wait MIU mask done or timeout!
450 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data);
451 fdp_fifo_done = u8Data & 0x04;
452 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2)+1, &u8Data);
453 //djb_fifo_done = u8Data & 0x01;
454 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
455 tdi_fifo_done = u8Data & 0x02;
456
457 u8_timeout++;
458 }
459 //while(((fdp_fifo_done != 0x04)||(djb_fifo_done != 0x01)||(tdi_fifo_done != 0x02))
460 while(((fdp_fifo_done != 0x04)||(tdi_fifo_done != 0x02))
461 && u8_timeout != 0x7f);
462
463 //printf(">> DVBT2 fdp_fifo_done=%d, djb_fifo_done=%d, tdi_fifo_done=%d \n", fdp_fifo_done, djb_fifo_done, tdi_fifo_done);
464 printf(">> DVBT2 [fdp_fifo_done]=%d, [tdi_fifo_done]=%d \n", fdp_fifo_done, tdi_fifo_done);
465
466 MsOS_DelayTask(2);
467
468 if(u8_timeout == 0x7f)
469 {
470 printf(">> DVBT2 MIU hold function Fail!\n");
471 //return FALSE;
472 }
473 else
474 {
475 printf(">> DVBT2 MIU hold function done!!\n");
476 }
477 }
478 else
479 printf(">> No need DVBT2 MIU hold function!!\n");
480
481 // demod_top reset
482 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
483 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data|0x20));
484
485 MsOS_DelayTask(1);
486
487 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data&(~0x20)));
488
489 DBG_INTERN_DVBT2(printf("@INTERN_DVBT2_SoftReset done!!\n"));
490
491 return bRet;
492 }
493
494
495 /***********************************************************************************
496 Subject: Reset
497 Function: INTERN_DVBT2_Reset
498 Parmeter:
499 Return: MS_BOOL
500 Remark:
501 ************************************************************************************/
502 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT2_Reset(void)503 MS_BOOL INTERN_DVBT2_Reset ( void )
504 {
505 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_reset\n"));
506
507 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Reset, t = %ld\n",MsOS_GetSystemTime()));
508
509 INTERN_DVBT2_SoftStop();
510
511
512 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
513 MsOS_DelayTask(5);
514 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
515
516 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
517 MsOS_DelayTask(5);
518
519 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
520 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
521
522 bFECLock = FALSE;
523 bP1Lock = FALSE;
524 u32ChkScanTimeStart = MsOS_GetSystemTime();
525 return TRUE;
526 }
527
528 /***********************************************************************************
529 Subject: Exit
530 Function: INTERN_DVBT2_Exit
531 Parmeter:
532 Return: MS_BOOL
533 Remark:
534 ************************************************************************************/
INTERN_DVBT2_Exit(void)535 MS_BOOL INTERN_DVBT2_Exit ( void )
536 {
537 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_Exit\n"));
538
539 INTERN_DVBT2_SoftStop();
540
541
542 //diable clk gen
543 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
544 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
545 /*
546 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
547 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
548
549 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
550 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
551
552 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
553 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
554
555 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
556 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
557
558 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
559 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
560
561 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
562 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
563
564 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
565 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
566
567 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
568 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
569
570 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
571 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
572
573 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
574 */
575 return TRUE;
576 }
577 /*
578 MS_BOOL INTERN_DVBT2_Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length)
579 {
580
581 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Load2Sdram, len=0x%x, \n",data_length));
582 MS_U8 addrhi, addrlo;
583 int i, j, k, old_i=0;
584 int sdram_start_addr = 0;//1024 >> 2; //StrToInt(ed_sdram_start->Text)>>2; // 4KB alignment
585
586 //I2C_CH_Exit(); // exit CH4
587 //I2C_CH5_Reset(); // switch to CH5
588 //MDrv_DMD_I2C_Channel_Change(5);
589 //--------------------------------------------------------------------------
590 // Set xData map for DRAM
591 //--------------------------------------------------------------------------
592
593 //banknum = 0x1d; //dmdmcu51_xdmiu
594
595 //set xData map upper and low bound for 64k DRAM window
596 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x2020);
597 if(SLAVE_I2CWrite16(banknum,0x63,0x2020)==false)
598 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
599
600 //set xData map offset for 64k DRAM window
601 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x64, 0x0000);
602 if(SLAVE_I2CWrite16(banknum,0x64,0x0000)==false)
603 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
604
605 //set xData map upper and low bound for 4k DRAM window
606 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x65, 0x2420);
607 if(SLAVE_I2CWrite16(banknum,0x65,0x2420)==false)
608 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
609
610 //set xData map offset for 4k DRAM window
611 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, sdram_start_addr);
612 if(SLAVE_I2CWrite16(banknum,0x66,sdram_start_addr)==false)
613 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
614
615 //I2C_CH_Exit(); // exit CH5
616 //EnterDebugMode(1); // switch to CH1
617
618 //enable xData map for DRAM
619 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x0007);
620 if(SLAVE_I2CWrite16(banknum,0x62,0x0007)==false)
621 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
622
623
624 for ( i = 0, j = SDRAM_BASE, k = sdram_start_addr + 0x01; i < size;)
625 {
626 if (j == SDRAM_BASE + 0x1000)
627 {
628 //I2C_CH_Exit(); // exit CH1
629 //I2C_CH5_Reset(); // switch to CH5
630 //set xData map offset for 4k DRAM window
631 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, k++);
632 if(SLAVE_I2CWrite16(banknum,0x66,k++)==false)
633 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
634 j = SDRAM_BASE;
635
636 //I2C_CH_Exit(); // exit CH5
637 //EnterDebugMode(1); // switch to CH1
638
639 }
640
641 addrhi = (j >> 8) & 0xff;
642 addrlo = j & 0xff;
643
644 if (i+EZUSB_Write_Buffer<size)
645 {
646 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,EZUSB_Write_Buffer)==FALSE)
647 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
648
649 j=j+EZUSB_Write_Buffer;
650 i=i+EZUSB_Write_Buffer;
651 }
652 else
653 {
654 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,size-i)==FALSE)
655 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
656
657 i=size;
658 }
659
660 if ((i-old_i)>=2048)
661 {
662 ShowMCUDL_Progress(0,3*i,size);
663 old_i=i;
664 }
665 }//end for
666
667
668 FWDLRichEdit->Lines->Add(">SDRAM Down Load OK!");
669
670 I2C_CH_Exit(); // exit CH1
671 I2C_CH5_Reset(); // switch to CH5
672
673 //--------------------------------------------------------------------------
674 // Release xData map for SDRAM
675 //--------------------------------------------------------------------------
676
677 if(SLAVE_I2CWrite16(banknum,0x62,0x0000)==false)
678 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
679
680 }
681 */
682 /***********************************************************************************
683 Subject: Load DSP code to chip
684 Function: INTERN_DVBT2_LoadDSPCode
685 Parmeter:
686 Return: MS_BOOL
687 Remark:
688 ************************************************************************************/
INTERN_DVBT2_LoadDSPCode(void)689 static MS_BOOL INTERN_DVBT2_LoadDSPCode(void)
690 {
691 MS_U8 u8data = 0x00;
692 MS_U16 i;
693 MS_U16 fail_cnt=0;
694 //MS_U16 u16AddressOffset;
695 MS_U32 u32VA_DramCodeAddr;
696
697 #if (DBG_DUMP_LOAD_DSP_TIME==1)
698 MS_U32 u32Time;
699 #endif
700
701
702 #ifndef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
703 BININFO BinInfo;
704 MS_BOOL bResult;
705 MS_U32 u32GEAddr;
706 MS_U8 Data;
707 MS_S8 op;
708 MS_U32 srcaddr;
709 MS_U32 len;
710 MS_U32 SizeBy4K;
711 MS_U16 u16Counter=0;
712 MS_U8 *pU8Data;
713 #endif
714
715 #if 0
716 if(HAL_DMD_RIU_ReadByte(0x101E3E))
717 {
718 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
719 return FALSE;
720 }
721 #endif
722
723 // MDrv_Sys_DisableWatchDog();
724
725
726 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
727 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
728 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
729 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
730 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
731 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
732
733 //// Load code thru VDMCU_IF ////
734 DBG_INTERN_DVBT2(printf(">Load Code...\n"));
735 //#ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
736 //for ( i = 0; i < sizeof(INTERN_DVBT2_table); i++)
737 //{
738 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
739 //}
740 if (sizeof(INTERN_DVBT2_table) < 0x8000)
741 {
742 printf("----->Bin file Size is not match...\n");
743 }
744 else
745 {
746 // load half code to SRAM
747 for ( i = 0; i < 0x8000; i++)
748 {
749 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
750 }
751 DBG_INTERN_DVBT2(printf(">Load SRAM code done...\n"));
752
753
754 if((u32DMD_DVBT2_FW_START_ADDR & 0x8000) != 0x8000)
755 {
756 printf(">DVB-T2 DRAM Start address is not correct!!\n");
757 }
758 else
759 {
760 // load another half code to SDRAM
761 // VA = MsOS_PA2KSEG1(PA); //NonCache
762 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
763 u32VA_DramCodeAddr = MsOS_PA2KSEG1(u32DMD_DVBT2_FW_START_ADDR);
764 memcpy((void*)(MS_VIRT)u32VA_DramCodeAddr, &INTERN_DVBT2_table[0x8000], sizeof(INTERN_DVBT2_table) - 0x8000);
765
766 DBG_INTERN_DVBT2(printf(">Load DRAM code done...\n"));
767 }
768 }
769
770 //#endif
771
772 //// Content verification ////
773 DBG_INTERN_DVBT2(printf(">Verify Code...\n"));
774
775 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
776 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
777
778 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
779 for ( i = 0; i < 0x8000; i++)
780 {
781 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
782 if (u8data != INTERN_DVBT2_table[i])
783 {
784 printf(">fail add = 0x%x\n", i);
785 printf(">code = 0x%x\n", INTERN_DVBT2_table[i]);
786 printf(">data = 0x%x\n", u8data);
787
788 if (fail_cnt++ > 10)
789 {
790 printf(">DVB-T2 DSP SRAM Loadcode fail!\n");
791 return false;
792 }
793 }
794 }
795 #else
796 for (i=0;i<=SizeBy4K;i++)
797 {
798 if(i==SizeBy4K)
799 len=BinInfo.B_Len%0x1000;
800 else
801 len=0x1000;
802
803 srcaddr = u32GEAddr+(0x1000*i);
804 //printf("\t i = %08LX\n", i);
805 //printf("\t len = %08LX\n", len);
806 op = 1;
807 u16Counter = 0 ;
808 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
809 while(len--)
810 {
811 u16Counter ++ ;
812 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
813 //pU8Data = (U8 *)(srcaddr|0x80000000);
814 #if OBA2
815 pU8Data = (U8 *)(srcaddr);
816 #else
817 pU8Data = (U8 *)(srcaddr|0x80000000);
818 #endif
819 Data = *pU8Data;
820
821 #if 0
822 if(u16Counter < 0x100)
823 printf("0x%bx,", Data);
824 #endif
825 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
826 if (u8data != Data)
827 {
828 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
829 printf(">code = 0x%x\n", Data);
830 printf(">data = 0x%x\n", u8data);
831
832 if (fail_cnt++ > 10)
833 {
834 printf(">DVB-T DSP Loadcode fail!");
835 return false;
836 }
837 }
838
839 srcaddr += op;
840 }
841 // printf("\n\n\n");
842 }
843 #endif
844
845 // add T2 DRAM bufer start address into fixed location
846 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
847 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
848
849 // write Start address to VD MCU 51 code sram
850 // //0x30~0x33
851 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR);
852 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 8));
853 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 16));
854 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 24));
855 //0x30~0x33
856 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_EQ_START_ADDR);
857 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 8));
858 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 16));
859 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 24));
860 //0x34~0x37
861 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_TDI_START_ADDR);
862 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 8));
863 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 16));
864 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 24));
865 //0x38~0x3b
866 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_DJB_START_ADDR);
867 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 8));
868 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 16));
869 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 24));
870 //0x3c~0x3f
871 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_FW_START_ADDR);
872 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 8));
873 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 16));
874 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 24));
875
876 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR));
877 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR));
878 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR));
879 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
880
881 #if 0
882 // DEBUG
883 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
884 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
885
886 // for ( i = 0; i < 16; i++)
887 // {
888 // u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
889 // printf(">add = 0x%x\t", i);
890 // printf(">data = 0x%x\n", u8data);
891 // }
892
893 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR);
894 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR);
895 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR);
896 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR);
897 #endif
898
899 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
900 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
901 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
902 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
903
904 DBG_INTERN_DVBT2(printf(">DSP Loadcode done."));
905 //while(load_data_variable);
906
907 return TRUE;
908 }
909
910 /***********************************************************************************
911 Subject: DVB-T CLKGEN initialized function
912 Function: INTERN_DVBT2_Power_On_Initialization
913 Parmeter:
914 Return: MS_BOOL
915 Remark:
916 ************************************************************************************/
INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)917 void INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)
918 {
919 MS_U8 temp_val;
920 MS_U16 u16_temp_val;
921
922 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_InitClkgen\n"));
923
924 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
925 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
926 // ----------------------------------------------
927 // start demod CLKGEN setting
928 // ----------------------------------------------
929 // *** Set register at CLKGEN1
930 // enable DMD MCU clock "bit[0] set 0"
931 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
932 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
933 // CLK_DMDMCU clock setting
934 // [0] disable clock
935 // [1] invert clock
936 // [4:2]
937 // 000:170 MHz(MPLL_DIV_BUf)
938 // 001:160MHz
939 // 010:144MHz
940 // 011:123MHz
941 // 100:108MHz
942 // 101:mem_clcok
943 // 110:mem_clock div 2
944 // 111:select XTAL
945 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
946 // HAL_DMD_RIU_WriteByte(0x10331e,0x1c); // 24MHz
947 HAL_DMD_RIU_WriteByte(0x10331e,0x10); // 108MHz
948
949 // set parallet ts clock
950 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
951 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
952 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0615
953 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
954 temp_val|=0x05;
955 // temp_val|=0x07;
956 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
957
958 HAL_DMD_RIU_WriteByte(0x103300,0x10);
959
960 // enable DVBTC ts clock
961 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
962 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
963 HAL_DMD_RIU_WriteByte(0x103309,0x00);
964 HAL_DMD_RIU_WriteByte(0x103308,0x00);
965
966 // enable dvbc adc clock
967 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
968 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
969 HAL_DMD_RIU_WriteByte(0x103315,0x00);
970 HAL_DMD_RIU_WriteByte(0x103314,0x00);
971
972 // ----------------------------------------------
973 // start demod_0 CLKGEN setting
974 // ----------------------------------------------
975
976 // enable clk_atsc_adcd_sync
977 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
978 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
979 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
980 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
981
982 //reg_ckg_dvbt_inner
983 HAL_DMD_RIU_WriteByte(0x111f21,0x11);
984 HAL_DMD_RIU_WriteByte(0x111f20,0x10);
985
986 //reg_ckg_dvbt_outer
987 HAL_DMD_RIU_WriteByte(0x111f23,0x01);
988 HAL_DMD_RIU_WriteByte(0x111f22,0x11);
989
990 //reg_ckg_acifir
991 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
992
993 //reg_ckg_dvbtm_sram_t1o2x_t22x
994 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
995 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
996
997 //reg_ckg_dvbtm_sram_adc_t22x
998 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
999 HAL_DMD_RIU_WriteByte(0x111f2c,0x01);
1000
1001 //reg_ckg_dvbtm_sram_t12x_t24x
1002 HAL_DMD_RIU_WriteByte(0x111f2f,0x00);
1003 HAL_DMD_RIU_WriteByte(0x111f2e,0x00);
1004
1005 //reg_ckg_dvbtm_ts_in
1006 HAL_DMD_RIU_WriteByte(0x111f31,0x04);
1007 HAL_DMD_RIU_WriteByte(0x111f30,0x00);
1008
1009 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
1010 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
1011
1012 HAL_DMD_RIU_WriteByte(0x111f35,0x00);
1013 HAL_DMD_RIU_WriteByte(0x111f34,0x00);
1014
1015 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
1016 HAL_DMD_RIU_WriteByte(0x111f36,0x00);
1017
1018 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
1019 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
1020
1021 HAL_DMD_RIU_WriteByte(0x111f3d,0x00);
1022 HAL_DMD_RIU_WriteByte(0x111f3c,0x00);
1023
1024 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1025 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1026
1027 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1028 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1029
1030 HAL_DMD_RIU_WriteByte(0x111fe1,0x00);
1031 HAL_DMD_RIU_WriteByte(0x111fe0,0x00);
1032
1033 HAL_DMD_RIU_WriteByte(0x111fe3,0x00);
1034 HAL_DMD_RIU_WriteByte(0x111fe2,0x00);
1035
1036 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1037 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1038
1039 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1040 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1041
1042 HAL_DMD_RIU_WriteByte(0x111fe9,0x00);
1043 HAL_DMD_RIU_WriteByte(0x111fe8,0x00);
1044
1045 HAL_DMD_RIU_WriteByte(0x111feb,0xc8);
1046 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1047
1048 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1049 HAL_DMD_RIU_WriteByte(0x111fec,0x0c);
1050
1051 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1052 HAL_DMD_RIU_WriteByte(0x111fee,0x00);
1053
1054 // Maserati special
1055 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1056 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1057
1058 HAL_DMD_RIU_WriteByte(0x111ff0,0x00);
1059
1060 // Mulan special
1061 // TEQ CLK for DVBT2
1062 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1063
1064 // SRAM share
1065 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
1066 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
1067
1068 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1069 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1070
1071 HAL_DMD_RIU_WriteByte(0x111f79,0x00);
1072 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
1073
1074 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
1075 HAL_DMD_RIU_WriteByte(0x111f7a,0x00);
1076
1077 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1078 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1079
1080 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
1081 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
1082
1083 // 32+4K xdata sram
1084 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
1085 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1086 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
1087 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1088
1089 // SRAM allocation
1090 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1091 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1092
1093 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1094 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1095
1096 HAL_DMD_RIU_WriteByte(0x111703,0x00);
1097 HAL_DMD_RIU_WriteByte(0x111702,0x00);
1098
1099 HAL_DMD_RIU_WriteByte(0x111707,0x7f);
1100 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1101
1102 // SDRAM address offset
1103 u16_temp_val = (MS_U16)(u32DMD_DVBT2_FW_START_ADDR>>16);
1104 HAL_DMD_RIU_WriteByte(0x11171b,(MS_U8)(u16_temp_val>>8));
1105 HAL_DMD_RIU_WriteByte(0x11171a,(MS_U8)u16_temp_val);
1106
1107 // DRAM allocation
1108 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1109 HAL_DMD_RIU_WriteByte(0x111708,0x00);
1110
1111 HAL_DMD_RIU_WriteByte(0x11170d,0x80);
1112 HAL_DMD_RIU_WriteByte(0x11170c,0x00);
1113
1114 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1115 HAL_DMD_RIU_WriteByte(0x11170a,0x00);
1116
1117 HAL_DMD_RIU_WriteByte(0x11170f,0xff);
1118 HAL_DMD_RIU_WriteByte(0x11170e,0xff);
1119
1120 // DRAM EN
1121 HAL_DMD_RIU_WriteByte(0x111718,0x04);
1122
1123 // [0]switch dram address mode:
1124 // 0: address from dmdmcu51 bank (old mode)
1125 // 1: address from dmdmcu51_top bank (new mode)
1126 HAL_DMD_RIU_WriteByte(0x11171c,0x01);
1127
1128 // ----------------------------------------------
1129 // start demod CLKGEN setting
1130 // ----------------------------------------------
1131 // select DMD MCU
1132 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1133 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1134 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1135
1136 // stream2miu_en, activate rst_wadr
1137 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1138 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1139 // stream2miu_en, turn off rst_wadr
1140 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1141
1142 }
1143
1144 /***********************************************************************************
1145 Subject: Power on initialized function
1146 Function: INTERN_DVBT2_Power_On_Initialization
1147 Parmeter:
1148 Return: MS_BOOL
1149 Remark:
1150 ************************************************************************************/
1151
INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT2_DSPRegInitExt,MS_U8 u8DMD_DVBT2_DSPRegInitSize)1152 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT2_DSPRegInitExt, MS_U8 u8DMD_DVBT2_DSPRegInitSize)
1153 {
1154 MS_U16 status = true;
1155
1156 // MS_U8 temp_val;
1157 //MS_U8 cData = 0;
1158 //U8 cal_done;
1159 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Power_On_Initialization\n"));
1160
1161 #if defined(PWS_ENABLE)
1162 Mapi_PWS_Stop_VDMCU();
1163 #endif
1164 // No definition for Mulan
1165 #if 0
1166 // Global demod reset. To fix DVBS -> DVBT2 or DVBS blind scan -> DVBT2 unlock issue.
1167 temp_val=HAL_DMD_RIU_ReadByte(0x101e3a);
1168 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val|0x02);
1169
1170 MsOS_DelayTask(1);
1171
1172 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val&(~0x02));
1173 #endif
1174
1175 INTERN_DVBT2_InitClkgen(bRFAGCTristateEnable);
1176 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1177 //// Firmware download //////////
1178 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Load DSP...\n"));
1179 //MsOS_DelayTask(100);
1180
1181 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1182 {
1183 if (INTERN_DVBT2_LoadDSPCode() == FALSE)
1184 {
1185 printf("DVB-T2 Load DSP Code Fail\n");
1186 return FALSE;
1187 }
1188 else
1189 {
1190 DBG_INTERN_DVBT2(printf("DVB-T2 Load DSP Code OK\n"));
1191 }
1192 }
1193
1194
1195 //// MCU Reset //////////
1196 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Reset...\n"));
1197 if (INTERN_DVBT2_Reset() == FALSE)
1198 {
1199 DBG_INTERN_DVBT2(printf("Fail\n"));
1200 return FALSE;
1201 }
1202 else
1203 {
1204 DBG_INTERN_DVBT2(printf("OK\n"));
1205 }
1206
1207 // SRAM setting, DVB-T use it.
1208 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1209 //MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1210 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1211
1212 status &= INTERN_DVBT2_DSPReg_Init(u8DMD_DVBT2_DSPRegInitExt, u8DMD_DVBT2_DSPRegInitSize);
1213 return status;
1214 }
1215
1216 /************************************************************************************************
1217 Subject: Driving control
1218 Function: INTERN_DVBT2_Driving_Control
1219 Parmeter: bInversionEnable : TRUE For High
1220 Return: void
1221 Remark:
1222 *************************************************************************************************/
INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)1223 void INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)
1224 {
1225 MS_U8 u8Temp;
1226
1227 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1228
1229 if (bEnable)
1230 {
1231 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1232 }
1233 else
1234 {
1235 u8Temp = u8Temp & (~0x01);
1236 }
1237
1238 DBG_INTERN_DVBT2(printf("---> INTERN_DVBT2_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1239 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1240 }
1241 /************************************************************************************************
1242 Subject: Clk Inversion control
1243 Function: INTERN_DVBT2_Clk_Inversion_Control
1244 Parmeter: bInversionEnable : TRUE For Inversion Action
1245 Return: void
1246 Remark:
1247 *************************************************************************************************/
INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)1248 void INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1249 {
1250 MS_U8 u8Temp;
1251
1252 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1253
1254 if (bInversionEnable)
1255 {
1256 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1257 }
1258 else
1259 {
1260 u8Temp = u8Temp & (~0x02);
1261 }
1262
1263 DBG_INTERN_DVBT2(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1264 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1265 }
1266 /************************************************************************************************
1267 Subject: Transport stream serial/parallel control
1268 Function: INTERN_DVBT2_Serial_Control
1269 Parmeter: bEnable : TRUE For serial
1270 Return: MS_BOOL :
1271 Remark:
1272 *************************************************************************************************/
INTERN_DVBT2_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1273 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1274 {
1275 MS_U8 status = true;
1276 MS_U8 temp_val;
1277 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_ts... u8TSClk=%d\n",u8TSClk));
1278
1279 if (u8TSClk == 0xFF) u8TSClk=0x13;
1280 if (bEnable) //Serial mode for TS pad
1281 {
1282 // serial
1283 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1284 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1285
1286 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1287 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1288 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1289
1290 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1291 temp_val|=0x04;
1292 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1293 #else
1294 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1295 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1296 temp_val|=0x07;
1297 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1298 #endif
1299 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1300 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1301 }
1302 else
1303 {
1304 //parallel
1305 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1306 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1307
1308 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1309 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1310 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1311 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1312 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1313 temp_val|=0x05;
1314 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1315 #else
1316 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1317 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1318 temp_val|=0x07;
1319 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1320 #endif
1321
1322 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1323 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1324 }
1325
1326 //DBG_INTERN_DVBT2(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1327
1328 INTERN_DVBT2_Driving_Control(INTERN_DVBT2_DTV_DRIVING_LEVEL);
1329 return status;
1330 }
1331
1332 /************************************************************************************************
1333 Subject: TS1 output control
1334 Function: INTERN_DVBT2_PAD_TS1_Enable
1335 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1336 Return: void
1337 Remark:
1338 *************************************************************************************************/
INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)1339 void INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)
1340 {
1341 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_TS1_Enable... \n"));
1342
1343 if(flag) // PAD_TS1 Enable TS CLK PAD
1344 {
1345 //printf("=== TS1_Enable ===\n");
1346 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1347 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1348 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1349 }
1350 else // PAD_TS1 Disable TS CLK PAD
1351 {
1352 //printf("=== TS1_Disable ===\n");
1353 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1354 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1355 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1356 }
1357 }
1358
1359 /************************************************************************************************
1360 Subject: channel change config
1361 Function: INTERN_DVBT2_Config
1362 Parmeter: BW: bandwidth
1363 Return: MS_BOOL :
1364 Remark:
1365 *************************************************************************************************/
INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U8 u8PlpID)1366 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID)
1367 {
1368 MS_U8 bandwidth;
1369 MS_U8 status = true;
1370 //MS_U8 temp_val;
1371 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_config %d %d %d %ld %d\n", BW, bSerialTS, u8TSClk, u32IFFreq, u8PlpID));
1372 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Config, t = %ld\n",MsOS_GetSystemTime()));
1373
1374 if (u8TSClk == 0xFF) u8TSClk=0x13;
1375 switch(BW)
1376 {
1377 case E_DMD_T2_RF_BAND_5MHz:
1378 bandwidth = 1;
1379 break;
1380 case E_DMD_T2_RF_BAND_6MHz:
1381 bandwidth = 2;
1382 break;
1383 case E_DMD_T2_RF_BAND_7MHz:
1384 bandwidth = 3;
1385 break;
1386 case E_DMD_T2_RF_BAND_10MHz:
1387 bandwidth = 5;
1388 break;
1389 case E_DMD_T2_RF_BAND_1p7MHz:
1390 bandwidth = 0;
1391 break;
1392 case E_DMD_T2_RF_BAND_8MHz:
1393 default:
1394 bandwidth = 4;
1395 break;
1396 }
1397
1398 status &= INTERN_DVBT2_Reset();
1399
1400 // BW mode
1401 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_BW, BW);
1402 // TS mode
1403 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_T2_TS_SERIAL, bSerialTS? 0x01:0x00);
1404 // FC
1405 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_L, u32IFFreq&0xff);
1406 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_H, (u32IFFreq>>8)&0xff);
1407 // PLP_ID
1408 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
1409
1410 /*
1411 if(bSerialTS)
1412 {
1413 // serial
1414 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1415 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1416
1417 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1418 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1419 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1420 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1421 temp_val|=0x04;
1422 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1423 #else
1424 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1425 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1426 temp_val|=0x07;
1427 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1428 #endif
1429 }
1430 else
1431 {
1432 //parallel
1433 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1434 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1435
1436 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1437 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1438 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1439 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1440 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1441 temp_val|=0x05;
1442 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1443 #else
1444 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1445 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1446 temp_val|=0x07;
1447 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1448 #endif
1449 }
1450 */
1451 return status;
1452 }
1453 /************************************************************************************************
1454 Subject: enable hw to lock channel
1455 Function: INTERN_DVBT2_Active
1456 Parmeter: bEnable
1457 Return: MS_BOOL
1458 Remark:
1459 *************************************************************************************************/
INTERN_DVBT2_Active(MS_BOOL bEnable)1460 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable)
1461 {
1462 MS_U8 status = true;
1463
1464 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_active\n"));
1465
1466 //// INTERN_DVBT2 Finite State Machine on/off //////////
1467 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1468
1469 INTERN_DVBT2_SignalQualityReset();
1470
1471 //printf("++++++++++++++++++Active! While(1)+++++++++++++++++++++\n");
1472 //while(1);
1473
1474 return status;
1475 }
1476 /************************************************************************************************
1477 Subject: Return lock status
1478 Function: INTERN_DVBT2_Lock
1479 Parmeter: eStatus :
1480 Return: MS_BOOL
1481 Remark:
1482 *************************************************************************************************/
INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout,MS_U16 u16DMD_DVBT2_FEC_Timeout)1483 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout)
1484 {
1485 float fBER=0.0f;
1486
1487 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK))
1488 {
1489 // copy from msb1240 >>>>>
1490 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1491 {
1492 if ((fBerFilteredDVBT2 <= 0.0) || ((fBerFilteredDVBT2/fBER) > 30.0 || (fBerFilteredDVBT2/fBER) < 0.03))
1493 fBerFilteredDVBT2 = fBER;
1494 else
1495 fBerFilteredDVBT2 = 0.9f*fBerFilteredDVBT2+0.1f*fBER;
1496 }
1497 // <<<<< copy from msb1240
1498
1499 if (bFECLock == FALSE)
1500 {
1501 u32FecFirstLockTime = MsOS_GetSystemTime();
1502 DBG_INTERN_DVBT2(printf("++++++++[utopia]dvbt2 lock\n"));
1503 }
1504 #if 0
1505 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1506 {
1507 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1508 {
1509 if(fLDPCBerFiltered <= 0.0)
1510 fLDPCBerFiltered = fBER;
1511 else
1512 fLDPCBerFiltered = 0.9f*fLDPCBerFiltered+0.1f*fBER;
1513 }
1514 DBG_INTERN_DVBT2(printf("[dvbt2]f_ber=%8.3e, g_ldpc_ber=%8.3e\n",fBER,fLDPCBerFiltered));
1515 }
1516 #endif
1517 u32FecLastLockTime = MsOS_GetSystemTime();
1518 bFECLock = TRUE;
1519 return E_DMD_T2_LOCK;
1520 }
1521 else
1522 {
1523 #if 0
1524 INTERN_DVBT2_SignalQualityReset();
1525 #endif
1526 if (bFECLock == TRUE)
1527 {
1528 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1529 {
1530 return E_DMD_T2_LOCK;
1531 }
1532 }
1533 bFECLock = FALSE;
1534 }
1535 /*
1536 #ifdef CHIP_KRITI
1537 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_NO_CHANNEL))
1538 {
1539 // DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- E_DMD_DVBT2_NO_CHANNEL \n"););
1540 return E_DMD_T2_UNLOCK;
1541 }
1542 #endif
1543 */
1544 if(!bP1Lock)
1545 {
1546 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_EVER_LOCK))
1547 {
1548 DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- P1Lock \n"));
1549 bP1Lock = TRUE;
1550 }
1551 }
1552 if(bP1Lock)
1553 {
1554 DBG_INTERN_DVBT2(printf("P1Lock %ld\n",MsOS_GetSystemTime()));
1555 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_FEC_Timeout)
1556 {
1557 return E_DMD_T2_CHECKING;
1558 }
1559 }
1560 else
1561 {
1562 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_P1_Timeout)
1563 {
1564 return E_DMD_T2_CHECKING;
1565 }
1566 }
1567 return E_DMD_T2_UNLOCK;
1568
1569 }
1570
1571
INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)1572 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)
1573 {
1574 MS_U16 u16Address = 0;
1575 MS_U8 cData = 0;
1576 MS_U8 cBitMask = 0;
1577 MS_U8 use_dsp_reg = 0;
1578
1579 switch( eStatus )
1580 {
1581 case E_DMD_DVBT2_FEC_LOCK:
1582 use_dsp_reg = 1;
1583 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //FEC lock,
1584 cBitMask = BIT(7);
1585 break;
1586
1587 case E_DMD_DVBT2_P1_LOCK:
1588 u16Address = 0x3082; //P1 HW Lock,
1589 cBitMask = BIT(3);
1590 break;
1591
1592 case E_DMD_DVBT2_DCR_LOCK:
1593 use_dsp_reg = 1;
1594 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //DCR Lock,
1595 cBitMask = BIT(2);
1596 break;
1597
1598 case E_DMD_DVBT2_AGC_LOCK:
1599 use_dsp_reg = 1;
1600 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //AGC Lock,
1601 cBitMask = BIT(0);
1602 break;
1603
1604 case E_DMD_DVBT2_MODE_DET:
1605 u16Address = 0x3082; //Mode CP Detect,
1606 cBitMask = BIT(1);
1607 break;
1608
1609 case E_DMD_DVBT2_P1_EVER_LOCK:
1610 use_dsp_reg = 1;
1611 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //P1 Ever Lock,
1612 cBitMask = BIT(5);
1613 break;
1614
1615 case E_DMD_DVBT2_L1_CRC_LOCK:
1616 u16Address = 0x2B41; //P1 Ever Lock,
1617 cBitMask = BIT(5)|BIT(6)|BIT(7);
1618 break;
1619
1620 case E_DMD_DVBT2_NO_CHANNEL:
1621 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1622 cBitMask = BIT(7);
1623 break;
1624
1625
1626 default:
1627 return FALSE;
1628 }
1629
1630 if (use_dsp_reg == 1)
1631 {
1632 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Address, &cData) == FALSE)
1633 {
1634 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1635 return FALSE;
1636 }
1637 }
1638 else
1639 {
1640 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1641 {
1642 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadReg fail \n"));
1643 return FALSE;
1644 }
1645 }
1646
1647 #ifdef MS_DEBUG
1648 MS_U8 u8tmp;
1649 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20c4, &u8tmp);
1650 DBG_INTERN_DVBT2(printf(">>>>>>>>>> DVBT2 State=%d \n", u8tmp));
1651 #endif
1652
1653 if ((cData & cBitMask) == cBitMask)
1654 {
1655 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is lock \n", eStatus));
1656 return TRUE;
1657 }
1658 else
1659 {
1660 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is unlock \n", eStatus));
1661 return FALSE;
1662 }
1663
1664 }
1665
1666 /****************************************************************************
1667 Subject: To get the Post LDPC BER
1668 Function: INTERN_DVBT2_GetPostLdpcBer
1669 Parmeter: Quility
1670 Return: E_RESULT_SUCCESS
1671 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1672 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1673 We will not read the Period, and have the "/256/8"
1674 *****************************************************************************/
INTERN_DVBT2_GetPostLdpcBer(float * ber)1675 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber)
1676 {
1677 MS_BOOL status = true;
1678 MS_U8 reg=0;
1679 MS_U16 BitErrPeriod;
1680 MS_U32 BitErr;
1681 MS_U16 FecType = 0;
1682
1683 /////////// Post-Viterbi BER /////////////
1684
1685 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1686 {
1687 *ber = (float)-1.0;
1688 return false;
1689 }
1690
1691 /////////// Data BER /////////////
1692 // bank 0x33 0x02 [0] freeze
1693 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1694
1695 // bank 0x33 0x12 Data BER Window[15:0]
1696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1697 BitErrPeriod = reg;
1698 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1699 BitErrPeriod = (BitErrPeriod << 8) | reg;
1700
1701 // bank 0x33 0x34 Data BER count[15:0]
1702 // bank 0x33 0x35 Data BER count[31:16]
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1704 BitErr = reg;
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1706 BitErr = (BitErr << 8) | reg;
1707 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1708 BitErr = (BitErr << 8) | reg;
1709 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1710 BitErr = (BitErr << 8) | reg;
1711
1712 // bank 0x33 0x02 [0] freeze
1713 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1714
1715 if (BitErrPeriod == 0)
1716 //protect 0
1717 BitErrPeriod = 1;
1718
1719 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1720 FecType = reg;
1721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1722 FecType = (FecType << 8) | reg;
1723
1724 if (FecType & 0x0180)
1725 {
1726 if (BitErr == 0)
1727 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1728 else
1729 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1730 }
1731 else
1732 {
1733 if (BitErr == 0)
1734 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1735 else
1736 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1737 }
1738
1739 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1740
1741 if (status == FALSE)
1742 {
1743 printf("INTERN_DVBT2_GetPostLdpcBer Fail!\n");
1744 return FALSE;
1745 }
1746
1747 return status;
1748 }
1749
1750 /****************************************************************************
1751 Subject: To get the Pre LDPC BER
1752 Function: INTERN_DVBT2_GetPreLdpcBer
1753 Parmeter: ber
1754 Return: E_RESULT_SUCCESS
1755 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1756 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1757 We will not read the Period, and have the "/256/8"
1758 *****************************************************************************/
INTERN_DVBT2_GetPreLdpcBer(float * ber)1759 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber)
1760 {
1761 MS_U8 status = true;
1762 MS_U8 reg=0;
1763 MS_U16 BitErrPeriod;
1764 MS_U32 BitErr;
1765 MS_U16 FecType = 0;
1766
1767 /////////// Data BER /////////////
1768 // bank 0x33 0x02 [0] freeze
1769 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1770
1771 // bank 0x33 0x12 Data BER Window[15:0]
1772 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1773 BitErrPeriod = reg;
1774 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1775 BitErrPeriod = (BitErrPeriod << 8) | reg;
1776
1777 // bank 0x33 0x34 Data BER count[15:0]
1778 // bank 0x33 0x35 Data BER count[31:16]
1779 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1780 BitErr = reg;
1781 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1782 BitErr = (BitErr << 8) | reg;
1783 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1784 BitErr = (BitErr << 8) | reg;
1785 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1786 BitErr = (BitErr << 8) | reg;
1787
1788 // bank 0x33 0x02 [0] freeze
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1790
1791 if (BitErrPeriod == 0)
1792 //protect 0
1793 BitErrPeriod = 1;
1794
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1796 FecType = reg;
1797 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1798 FecType = (FecType << 8) | reg;
1799
1800 if (FecType & 0x0180)
1801 {
1802 if (BitErr == 0)
1803 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1804 else
1805 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1806 }
1807 else
1808 {
1809 if (BitErr == 0)
1810 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1811 else
1812 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1813 }
1814
1815 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1816
1817 if (status == FALSE)
1818 {
1819 printf("INTERN_DVBT2_GetPreLdpcBer Fail!\n");
1820 return FALSE;
1821 }
1822
1823 return status;
1824 }
1825
1826 /****************************************************************************
1827 Subject: To get the Packet error
1828 Function: INTERN_DVBT2_GetPacketErr
1829 Parmeter: pktErr
1830 Return: E_RESULT_SUCCESS
1831 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1832 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1833 We will not read the Period, and have the "/256/8"
1834 *****************************************************************************/
INTERN_DVBT2_GetPacketErr(MS_U16 * u16PktErr)1835 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr)
1836 {
1837 MS_BOOL status = true;
1838 MS_U8 reg = 0;
1839 MS_U16 PktErr;
1840
1841 //freeze
1842 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01);
1843 //read packet error
1844 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5B, ®);
1845 PktErr = reg;
1846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5A, ®);
1847 PktErr = (PktErr << 8) | reg;
1848
1849 *u16PktErr = PktErr;
1850 //release
1851 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00);
1852
1853 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PktErr = %d \n ", (int)PktErr));
1854
1855 *u16PktErr = PktErr;
1856
1857 return status;
1858 }
1859
1860 /****************************************************************************
1861 Subject: To get the DVBT2 parameter
1862 Function: INTERN_DVBT2_Get_L1_Info
1863 Parmeter: point to return parameter
1864 Return: TRUE
1865 FALSE
1866 Remark: The TPS parameters will be available after TPS lock
1867 *****************************************************************************/
INTERN_DVBT2_Get_L1_Parameter(MS_U16 * pu16L1_parameter,DMD_DVBT2_SIGNAL_INFO eSignalType)1868 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType)
1869 {
1870 MS_U8 u8Data = 0;
1871 MS_U16 FecType = 0;
1872 MS_U16 u16Data = 0;
1873 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
1874 {
1875 if (eSignalType == T2_MODUL_MODE)
1876 {
1877 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1878 return FALSE;
1879
1880 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(5) | BIT(4) | BIT(3))) >> 3;
1881 }
1882 else if (eSignalType == T2_FFT_VALUE)
1883 {
1884 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1885 {
1886 return FALSE;
1887 }
1888 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1889 }
1890 else if (eSignalType == T2_GUARD_INTERVAL)
1891 {
1892 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1893 {
1894 return FALSE;
1895 }
1896 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(6) | BIT(5) | BIT(4))) >> 4;
1897 }
1898 else if (eSignalType == T2_CODE_RATE)
1899 {
1900 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1901 {
1902 return FALSE;
1903 }
1904 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1905 }
1906 else if (eSignalType == T2_PREAMBLE)
1907 {
1908 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1909 {
1910 return FALSE;
1911 }
1912 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(4))) >> 4;
1913 }
1914 else if (eSignalType == T2_S1_SIGNALLING)
1915 {
1916 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1917 {
1918 return FALSE;
1919 }
1920 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(3) | BIT(2) | BIT(1))) >> 1;
1921 }
1922 else if (eSignalType == T2_PILOT_PATTERN)
1923 {
1924 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE)
1925 {
1926 return FALSE;
1927 }
1928 *pu16L1_parameter = (((MS_U16) u8Data) & 0x0F);
1929 }
1930 else if (eSignalType == T2_BW_EXT)
1931 {
1932 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
1933 {
1934 return FALSE;
1935 }
1936 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(0)));
1937 }
1938 else if (eSignalType == T2_PAPR_REDUCTION)
1939 {
1940 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2), &u8Data) == FALSE)
1941 {
1942 return FALSE;
1943 }
1944 *pu16L1_parameter = (((MS_U16) u8Data) & 0xF0) >> 4;
1945 }
1946 else if (eSignalType == T2_OFDM_SYMBOLS_PER_FRAME)
1947 {
1948 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2), &u8Data) == FALSE)
1949 {
1950 return FALSE;
1951 }
1952 *pu16L1_parameter = (MS_U16) u8Data;
1953 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2) + 1, &u8Data) == FALSE)
1954 {
1955 return FALSE;
1956 }
1957 *pu16L1_parameter |= (((MS_U16) u8Data) & 0x0F) << 8;
1958 }
1959 else if (eSignalType == T2_PLP_ROTATION)
1960 {
1961 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1962 {
1963 return FALSE;
1964 }
1965 *pu16L1_parameter = (((MS_U16) u8Data) & BIT(6)) >> 6;
1966 }
1967 else if (eSignalType == T2_PLP_FEC_TYPE)
1968 {
1969 //FEC Type[8:7]
1970 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8f, &u8Data) == FALSE) return FALSE;
1971 FecType = u8Data;
1972 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8e, &u8Data) == FALSE) return FALSE;
1973 FecType = (FecType << 8) | u8Data;
1974
1975 *pu16L1_parameter = (FecType & 0x0180) >> 7;
1976 }
1977 else if (eSignalType == T2_NUM_PLP)
1978 {
1979 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x42 * 2), &u8Data) == FALSE)
1980 {
1981 return FALSE;
1982 }
1983 *pu16L1_parameter = (MS_U16)u8Data;
1984 }
1985 else if (eSignalType == T2_PLP_TYPE)
1986 {
1987 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x45 * 2) + 1, &u8Data) == FALSE)
1988 {
1989 return FALSE;
1990 }
1991 *pu16L1_parameter = ((MS_U16) u8Data) & 0x07;
1992 }
1993 else if (eSignalType == T2_PLP_TIME_IL_TYPE)
1994 {
1995 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x48 * 2) + 1, &u8Data) == FALSE)
1996 {
1997 return FALSE;
1998 }
1999 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2000 }
2001 else if (eSignalType == T2_PLP_TIME_IL_LENGTH)
2002 {
2003 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x49 * 2) + 1, &u8Data) == FALSE)
2004 {
2005 return FALSE;
2006 }
2007 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2008 }
2009 else if (eSignalType == T2_DAT_ISSY)
2010 {
2011 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2012 {
2013 return FALSE;
2014 }
2015 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2016 }
2017 else if (eSignalType == T2_PLP_MODE)
2018 {
2019 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE)
2020 {
2021 return FALSE;
2022 }
2023 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE)
2024 {
2025 return FALSE;
2026 }
2027 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2028 {
2029 return FALSE;
2030 }
2031 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE)
2032 {
2033 return FALSE;
2034 }
2035 *pu16L1_parameter = ((MS_U16) u8Data) & 0x03;
2036 }
2037 else if (eSignalType == T2_L1_MODULATION)
2038 {
2039 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2) + 1, &u8Data) == FALSE)
2040 {
2041 return FALSE;
2042 }
2043 *pu16L1_parameter = ((MS_U16) u8Data) & 0x0F;
2044 }
2045 else if (eSignalType == T2_NUM_T2_FRAMES)
2046 {
2047 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3b * 2), &u8Data) == FALSE)
2048 {
2049 return FALSE;
2050 }
2051 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2052 }
2053 else if (eSignalType == T2_PLP_NUM_BLOCKS_MAX)
2054 {
2055 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2) + 1, &u8Data) == FALSE) return FALSE;
2056 u16Data = u8Data & 0x03;
2057 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2), &u8Data) == FALSE) return FALSE;
2058 u16Data = (u16Data << 8) | u8Data;
2059
2060 *pu16L1_parameter = u16Data;
2061 }
2062 else if (eSignalType == T2_FEF_ENABLE)
2063 {
2064
2065 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(0x00F1, &u8Data) == FALSE)
2066 {
2067 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2068 return FALSE;
2069 }
2070 *pu16L1_parameter = ((MS_U16) u8Data) & 0x01;
2071 }
2072 else
2073 {
2074 return FALSE;
2075 }
2076
2077 return TRUE;
2078
2079 }
2080
2081 return FALSE;
2082 }
2083
2084
2085 /****************************************************************************
2086 Subject: Read the signal to noise ratio (SNR)
2087 Function: INTERN_DVBT2_GetSNR
2088 Parmeter: None
2089 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2090 Remark:
2091 *****************************************************************************/
INTERN_DVBT2_GetSNR(void)2092 float INTERN_DVBT2_GetSNR (void)
2093 {
2094 MS_U8 status = true;
2095 MS_U8 reg=0, reg_frz=0;
2096 MS_U16 u16_snr100 = 0;
2097 float f_snr;
2098 MS_U8 u8_win = 0;
2099 MS_U8 u8_gi = 0;
2100
2101 // freeze
2102 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2103 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2104
2105 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2106 u16_snr100 = reg;
2107 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2108 u16_snr100 = (u16_snr100<<8)|reg;
2109
2110 // unfreeze
2111 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2112
2113 f_snr = (float)u16_snr100/100.0;
2114
2115 // snr cali
2116 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2117 u8_win = (reg>>2)&0x01;
2118
2119 if (u8_win == 1)
2120 {
2121 float snr_offset = 0.0;
2122 float snr_cali = 0.0;
2123
2124 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2125 u8_gi = (reg>>1)&0x07;
2126
2127 if (u8_gi == 0) snr_offset = 0.157;
2128 else if(u8_gi == 1) snr_offset = 0.317;
2129 else if(u8_gi == 2) snr_offset = 0.645;
2130 else if(u8_gi == 3) snr_offset = 1.335;
2131 else if(u8_gi == 4) snr_offset = 0.039;
2132 else if(u8_gi == 5) snr_offset = 0.771;
2133 else if(u8_gi == 6) snr_offset = 0.378;
2134
2135 snr_cali = f_snr - snr_offset;
2136 if (snr_cali > 0.0) f_snr = snr_cali;
2137 }
2138 //use Polynomial curve fitting to fix snr
2139 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2140 //f_snr = f_snr + snr_poly;
2141
2142 if (status == true)
2143 return f_snr;
2144 else
2145 return -1;
2146
2147 }
2148
INTERN_DVBT2_GetSignalStrength(MS_U16 * strength,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2149 MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength,const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2150 {
2151 MS_U8 status = true;
2152 float ch_power_db = 0.0f;
2153 float ch_power_ref = 11.0f;
2154 float ch_power_rel = 0.0f;
2155 //MS_U8 u8_index = 0;
2156 MS_U16 L1_info_qam, L1_info_cr;
2157 // MS_U8 demodState = 0;
2158
2159 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2160 {
2161 *strength = 0;
2162 return TRUE;
2163 }
2164 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2165
2166 // if (INTERN_DVBT2_Lock(COFDM_TPS_LOCK))
2167 //if (INTERN_DVBT2_Lock(COFDM_AGC_LOCK))
2168 /* Actually, it's more reasonable, that signal level depended on cable input power level
2169 * thougth the signal isn't dvb-t signal.
2170 */
2171
2172 #if 0
2173 // use pointer of IFAGC table to identify
2174 // case 1: RFAGC from SAR, IFAGC controlled by demod
2175 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2176 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2177 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
2178 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2179 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2180 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
2181 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
2182 #endif
2183
2184 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2185 printf("[dvbt2] QAM parameter retrieve failure\n");
2186
2187 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2188 printf("[dvbt2]code rate parameter retrieve failure\n");
2189
2190 /*
2191 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2192 {
2193 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
2194 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
2195 {
2196 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2197 break;
2198 }
2199 else
2200 {
2201 u8_index++;
2202 }
2203 }
2204 */
2205 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
2206
2207 // status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + (0x62*2), &demodState);
2208
2209 if (ch_power_ref > 10.0f)
2210 *strength = 0;
2211 else
2212 {
2213 // For Nordig's SSI test items
2214 if ( (L1_info_qam == 3) //256qam
2215 && (L1_info_cr > 0 && L1_info_cr < 4) // CR 3/5,2/3,3/4
2216 )
2217 {
2218 MS_U8 u8_x = L1_info_cr - 1;
2219 float f_ssi = 0.0;
2220
2221 if(ch_power_db >= -45)f_ssi = 100;
2222 else if (ch_power_db >= -50) f_ssi = fT2_SSI_formula[u8_x][0]*(ch_power_db + 50) + fT2_SSI_formula[u8_x][1];
2223 else if (ch_power_db >= -60) f_ssi = fT2_SSI_formula[u8_x][2]*(ch_power_db + 60) + fT2_SSI_formula[u8_x][3];
2224 else if (ch_power_db >= -70) f_ssi = fT2_SSI_formula[u8_x][4]*(ch_power_db + 70) + fT2_SSI_formula[u8_x][5];
2225 else if (ch_power_db >= -80) f_ssi = fT2_SSI_formula[u8_x][6]*(ch_power_db + 80) + fT2_SSI_formula[u8_x][7];
2226 else if (ch_power_db >= -95) f_ssi = fT2_SSI_formula[u8_x][8]*(ch_power_db + 95) + fT2_SSI_formula[u8_x][9];
2227 else if (ch_power_db >= -100) f_ssi = fT2_SSI_formula[u8_x][10]*(ch_power_db + 100) + fT2_SSI_formula[u8_x][11];
2228
2229 if (f_ssi > 100) *strength = 100;
2230 else if (f_ssi < 0) *strength = 0;
2231 else *strength = (MS_U16)(f_ssi+0.5);
2232
2233 DBG_GET_SIGNAL(printf(">>> SSI... RF_level=%d, f_ssi=%d, ssi=%d, cr=%d, mod=%d\n", (MS_S16)ch_power_db, (MS_S16)f_ssi, (MS_S16)(*strength), L1_info_cr, L1_info_qam));
2234 }
2235 else
2236 {
2237 ch_power_rel = ch_power_db - ch_power_ref;
2238 /*
2239 if (demodState != 0x09)
2240 {
2241 ch_power_rel = ch_power_db - (-50.0f);
2242 }
2243 else
2244 {
2245 ch_power_rel = ch_power_db - ch_power_ref;
2246 }
2247 */
2248 if ( ch_power_rel < -15.0f )
2249 {
2250 *strength = 0;
2251 }
2252 else if ( ch_power_rel < 0.0f )
2253 {
2254 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2255 }
2256 else if ( ch_power_rel < 20 )
2257 {
2258 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2259 }
2260 else if ( ch_power_rel < 35.0f )
2261 {
2262 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2263 }
2264 else
2265 {
2266 *strength = 100;
2267 }
2268 }
2269 }
2270
2271 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2272 {
2273 *strength = 0;
2274 return TRUE;
2275 }
2276
2277 DBG_GET_SIGNAL(printf(">>> ch_power_ref(dB) = %d , ch_power_db(dB) = %d, ch_power_rel(dB) = %d<<<\n", (MS_S16)ch_power_ref, (MS_S16)ch_power_db, (MS_S16)ch_power_rel));
2278 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %d , Score = %d<<<\n", (MS_S16)ch_power_db, *strength));
2279 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2280
2281 return status;
2282 }
2283
2284 /****************************************************************************
2285 Subject: To get the DVT Signal quility
2286 Function: INTERN_DVBT2_GetSignalQuality
2287 Parmeter: Quility
2288 Return: E_RESULT_SUCCESS
2289 E_RESULT_FAILURE
2290 Remark: Here we have 4 level range
2291 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
2292 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
2293 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
2294 <4>.4th Range => Quality <10
2295 *****************************************************************************/
INTERN_DVBT2_GetSignalQuality(MS_U16 * quality,const DMD_DVBT2_InitData * sDMD_DVBT2_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2296 MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2297 {
2298 // float ber_sqi, SQI;
2299 float fber;
2300 float cn_rec = 0;
2301 float cn_ref = 0;
2302 float cn_rel = 0;
2303 float fBerTH1[] = {1E-4, 1E-4*(1.0-DVBT2_BER_TH_HY), 1E-4*(1.0+DVBT2_BER_TH_HY), 1E-4};
2304 float fBerTH2[] = {3E-7, 3E-7, 3E-7*(1.0-DVBT2_BER_TH_HY), 3E-7*(1.0+DVBT2_BER_TH_HY)};
2305 float BER_SQI = (float)0.0;
2306 float SQI = (float)0.0;
2307 static MS_U8 u8SQIState = 0;
2308
2309 MS_U8 status = true;
2310 MS_U16 L1_info_qam = 0, L1_info_cr = 0, i = 0;
2311
2312 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2313
2314 if (TRUE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_LOCK) )
2315 {
2316 #if 1 // copy from msb1240
2317 if (fBerFilteredDVBT2 < 0.0)
2318 {
2319 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2320 {
2321 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2322 return FALSE;
2323 }
2324 fBerFilteredDVBT2 = fber;
2325 }
2326 else
2327 {
2328 fber = fBerFilteredDVBT2;
2329 }
2330
2331 if (fber > fBerTH1[u8SQIState])
2332 {
2333 BER_SQI = 0.0;
2334 u8SQIState = 1;
2335 }
2336 else if (fber >=fBerTH2[u8SQIState])
2337 {
2338 BER_SQI = 100.0/15;
2339 u8SQIState = 2;
2340 }
2341 else
2342 {
2343 BER_SQI = 100.0/6;
2344 u8SQIState = 3;
2345 }
2346
2347 cn_rec = INTERN_DVBT2_GetSNR();
2348 if (cn_rec < 0.0)
2349 return FALSE;
2350
2351 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2352 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2353 L1_info_qam = 0xff;
2354 L1_info_cr = 0xff;
2355
2356 cn_ref = (float)-1.0;
2357 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2358 printf("[dvbt2] QAM parameter retrieve failure\n");
2359
2360 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2361 printf("[dvbt2]code rate parameter retrieve failure\n");
2362
2363 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2364 {
2365 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2366 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2367 {
2368 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2369 break;
2370 }
2371 }
2372
2373 if (cn_ref < 0.0)
2374 {
2375 SQI = (float)0.0;
2376 printf("SQI is zero, 1\n");
2377 }
2378 else
2379 {
2380 // 0.7, snr offset
2381 cn_rel = cn_rec - cn_ref + 0.7f;
2382 if (cn_rel > 3.0)
2383 SQI = 100;
2384 else if (cn_rel >= -3)
2385 {
2386 SQI = (cn_rel+3)*BER_SQI;
2387 if (SQI > 100.0) SQI = 100.0;
2388 else if (SQI < 0.0) SQI = 0.0;
2389 }
2390 else
2391 {
2392 SQI = (float)0.0;
2393 printf("SQI is zero, 2\n");
2394 }
2395 }
2396
2397 *quality = (MS_U16)SQI;
2398 #else
2399 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2400 {
2401 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2402 }
2403 ///////// Get Pre-BCH (Post-LDPC) BER to determine BER_SQI //////////
2404 if(fLDPCBerFiltered<= 0.0)
2405 {
2406 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2407 {
2408 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2409 return FALSE;
2410 }
2411 fLDPCBerFiltered = fber;
2412 }
2413 else
2414 {
2415 fber = fLDPCBerFiltered;
2416 }
2417 /*
2418 if (fber > 1.0E-3)
2419 ber_sqi = 0.0;
2420 else if (fber > 8.5E-7)
2421 #ifdef MSOS_TYPE_LINUX
2422 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2423 #else
2424 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2425 #endif
2426 else
2427 ber_sqi = 100.0;
2428 */
2429 if (fber > 1E-4)
2430 ber_sqi = 0.0;
2431 else if (fber >= 1E-7)
2432 ber_sqi = 100.0 / 15;
2433 else
2434 ber_sqi = 100.0 / 6;
2435
2436 cn_rec = INTERN_DVBT2_GetSNR();
2437
2438 if (cn_rec == -1) //get SNR return fail
2439 status = false;
2440
2441 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2442 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2443 L1_info_qam = 0xff;
2444 L1_info_cr = 0xff;
2445
2446 cn_ref = (float)-1.0;
2447 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2448 printf("[dvbt2] QAM parameter retrieve failure\n");
2449
2450 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2451 printf("[dvbt2]code rate parameter retrieve failure\n");
2452
2453 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2454 {
2455 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2456 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2457 {
2458 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2459 break;
2460 }
2461 }
2462
2463 if (cn_ref == -1.0)
2464 SQI = (float)0.0;
2465 else
2466 {
2467 cn_rel = cn_rec - cn_ref;
2468 if (cn_rel > 3.0)
2469 SQI = 100;
2470 else if (cn_rel >= -3)
2471 {
2472 SQI = (cn_rel+3)*ber_sqi;
2473 if (SQI > 100.0) SQI = 100.0;
2474 else if (SQI < 0.0) SQI = 0.0;
2475 }
2476 else
2477 SQI = (float)0.0;
2478 }
2479
2480 // SQI patch, 256qam, R3/4 CN=20.8, SQI=0~13
2481 if ((L1_info_qam==_T2_256QAM) && (L1_info_cr==_T2_CR3Y4))
2482 {
2483 if ( (cn_rec > 20.6) && (cn_rec < 20.9))
2484 {
2485 if (SQI > 3) SQI -= 3;
2486 }
2487 else if ( (cn_rec >= 20.9) && (cn_rec < 21.2))
2488 {
2489 if (SQI > 9) SQI -= 9;
2490 }
2491 }
2492
2493 *quality = (MS_U16)SQI;
2494 #endif
2495 }
2496 else
2497 {
2498 *quality = 0;
2499 }
2500
2501 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
2502 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2503 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2504 return status;
2505 }
2506
2507 /****************************************************************************
2508 Subject: To get the DVBT Carrier Freq Offset
2509 Function: INTERN_DVBT2_Get_FreqOffset
2510 Parmeter: Frequency offset (in KHz), bandwidth
2511 Return: E_RESULT_SUCCESS
2512 E_RESULT_FAILURE
2513 Remark:
2514 *****************************************************************************/
INTERN_DVBT2_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2515 MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2516 {
2517 float N, FreqB;
2518 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2519 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2520 MS_U8 reg_frz=0, reg=0;
2521 MS_U8 status;
2522
2523 FreqB = (float)u8BW * 8 / 7;
2524
2525 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2526
2527 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2528
2529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2530 RegCfoTd = reg;
2531
2532 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2533 RegCfoTd = (RegCfoTd << 8)|reg;
2534
2535 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2536 RegCfoTd = (RegCfoTd << 8)|reg;
2537
2538 FreqCfoTd = (float)RegCfoTd;
2539
2540 if (RegCfoTd & 0x800000)
2541 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2542
2543 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2544
2545 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2546
2547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2548 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2549
2550 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2551
2552 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2553 RegCfoFd = reg;
2554
2555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2556 RegCfoFd = (RegCfoFd << 8)|reg;
2557
2558 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2559 RegCfoFd = (RegCfoFd << 8)|reg;
2560
2561 FreqCfoFd = (float)RegCfoFd;
2562
2563 if (RegCfoFd & 0x800000)
2564 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2565
2566 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2567
2568 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2569 RegIcfo = reg & 0x07;
2570
2571 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2572 RegIcfo = (RegIcfo << 8)|reg;
2573
2574 FreqIcfo = (float)RegIcfo;
2575
2576 if (RegIcfo & 0x400)
2577 FreqIcfo = FreqIcfo - (float)0x800;
2578
2579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2580 reg = reg & 0x30;
2581
2582 switch (reg)
2583 {
2584 case 0x00: N = 2048; break;
2585 case 0x20: N = 4096; break;
2586 case 0x10:
2587 default: N = 8192; break;
2588 }
2589
2590 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2591 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2592 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2593 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2594 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2595 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2596 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2597 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2598 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2599 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2600
2601 if (status == TRUE)
2602 return TRUE;
2603 else
2604 return FALSE;
2605 }
2606
2607
INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)2608 void INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)
2609 {
2610
2611 bPowerOn = bPowerOn;
2612 }
2613
INTERN_DVBT2_Power_Save(void)2614 MS_BOOL INTERN_DVBT2_Power_Save(void)
2615 {
2616
2617 return TRUE;
2618 }
2619
INTERN_DVBT2_Version(MS_U16 * ver)2620 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver)
2621 {
2622
2623 MS_U8 status = true;
2624 MS_U8 tmp = 0;
2625 MS_U16 u16_INTERN_DVBT2_Version;
2626
2627 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2628 u16_INTERN_DVBT2_Version = tmp;
2629 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2630 u16_INTERN_DVBT2_Version = u16_INTERN_DVBT2_Version<<8|tmp;
2631 *ver = u16_INTERN_DVBT2_Version;
2632
2633 return status;
2634 }
2635
INTERN_DVBT2_Version_minor(MS_U8 * ver2)2636 MS_BOOL INTERN_DVBT2_Version_minor(MS_U8 *ver2)
2637 {
2638
2639 MS_U8 status = true;
2640
2641 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2642
2643 return status;
2644 }
2645
2646
INTERN_DVBT2_Show_Demod_Version(void)2647 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void)
2648 {
2649
2650 MS_BOOL status = true;
2651 MS_U16 u16_INTERN_DVBT2_Version = 0;
2652 MS_U8 u8_minor_ver = 0;
2653
2654 status &= INTERN_DVBT2_Version(&u16_INTERN_DVBT2_Version);
2655 status &= INTERN_DVBT2_Version_minor(&u8_minor_ver);
2656 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT2_Version,u8_minor_ver);
2657
2658 return status;
2659 }
2660
INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float write_value)2661 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
2662 {
2663 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
2664 return TRUE;
2665 /*
2666 MS_U8 u8_index = 0;
2667 MS_BOOL bRet = false;
2668
2669 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2670 {
2671 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2672 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2673 {
2674 dvbt2_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2675 bRet = true;
2676 break;
2677 }
2678 else
2679 {
2680 u8_index++;
2681 }
2682 }
2683 return bRet;
2684 */
2685 }
2686
INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float * read_value)2687 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
2688 {
2689 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
2690 return TRUE;
2691 /*
2692 MS_U8 u8_index = 0;
2693 MS_BOOL bRet = false;
2694
2695 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2696 {
2697 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2698 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2699 {
2700 *read_value = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2701 bRet = true;
2702 break;
2703 }
2704 else
2705 {
2706 u8_index++;
2707 }
2708 }
2709 return bRet;
2710 */
2711 }
2712
INTERN_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)2713 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
2714 {
2715 MS_BOOL status = TRUE;
2716 MS_U8 u8Data = 0;
2717 MS_U8 indx = 0;
2718
2719 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_GetPlpBitMap\n"));
2720
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2722 if (u8Data != 0x30)
2723 {
2724 DBG_INTERN_DVBT2(printf("\n[INTERN_DVBT2_GetPlpBitMap] Check L1 NOT Ready !! E_DMD_T2_L1_FLAG = 0x%x\n", u8Data));
2725 return FALSE;
2726 }
2727 while (indx < 32)
2728 {
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_PLP_ID_ARR + indx, &u8Data);
2730 u8PlpBitMap[indx] = u8Data;
2731 indx++;
2732 }
2733
2734 if (status)
2735 {
2736 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap data+++++++++++++++\n"));
2737 for (indx = 0; indx < 32; indx++)
2738 DBG_INTERN_DVBT2(printf("[%d] ", u8PlpBitMap[indx]));
2739 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap end+++++++++++++++\n"));
2740 }
2741 return status;
2742 }
2743
INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)2744 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
2745 {
2746 MS_BOOL status = TRUE;
2747 MS_U8 u8Data = 0;
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
2749 if (u8Data != 0x30)
2750 {
2751 printf(">>>dvbt2 L1 not ready yet\n");
2752 return FALSE;
2753 }
2754 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_DVBT2_LOCK_HIS, &u8Data);
2755
2756 if ((u8Data & BIT(7)) == 0x00)
2757 {
2758 printf(">>>dvbt2 is un-lock\n");
2759 return FALSE;
2760 }
2761 // assign PLP-ID value
2762 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x78) * 2, u8PlpID);
2763 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x01); // MEM_EN
2764 MsOS_DelayTask(1);
2765 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x79) * 2, u8GroupID);
2766 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x00); // ~MEM_EN
2767
2768 return status;
2769 }
2770
INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID,MS_U8 u8GroupID)2771 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID)
2772 {
2773 MS_BOOL status = TRUE;
2774
2775 // assign Group-ID and PLP-ID value (must be written in order)
2776 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_GROUP_ID, u8GroupID);
2777 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
2778
2779 return status;
2780 }
2781
2782 #if (INTERN_DVBT2_INTERNAL_DEBUG == 1)
INTERN_DVBT2_get_demod_state(MS_U8 * state)2783 void INTERN_DVBT2_get_demod_state(MS_U8* state)
2784 {
2785 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2786 return;
2787 }
2788
INTERN_DVBT2_Show_ChannelLength(void)2789 MS_BOOL INTERN_DVBT2_Show_ChannelLength(void)
2790 {
2791 MS_U8 status = true;
2792 MS_U8 tmp = 0;
2793 MS_U16 len = 0;
2794 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2795 len = tmp;
2796 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2797 len = (len<<8)|tmp;
2798 printf("[dvbt]Hw_channel=%d\n",len);
2799 return status;
2800 }
2801
INTERN_DVBT2_Show_SW_ChannelLength(void)2802 MS_BOOL INTERN_DVBT2_Show_SW_ChannelLength(void)
2803 {
2804 MS_U8 status = true;
2805 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2806 MS_U16 sw_len = 0;
2807 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2808 sw_len = tmp;
2809 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2810 sw_len = (sw_len<<8)|tmp;
2811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2812 peak_num = tmp;
2813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2814 insideGI = tmp&0x01;
2815 stoptracking = (tmp&0x02)>>1;
2816 flag_short_echo = (tmp&0x0C)>>2;
2817 fsa_mode = (tmp&0x30)>>4;
2818
2819 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2820 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2821
2822 return status;
2823 }
2824
INTERN_DVBT2_Show_ACI_CI(void)2825 MS_BOOL INTERN_DVBT2_Show_ACI_CI(void)
2826 {
2827
2828 #define BIT4 0x10
2829 MS_U8 status = true;
2830 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2831
2832 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2833 digACI = (tmp&BIT4)>>4;
2834
2835 // get flag_CI
2836 // 0: No interference
2837 // 1: CCI
2838 // 2: in-band ACI
2839 // 3: N+1 ACI
2840 // flag_ci = (tmp&0xc0)>>6;
2841 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2842 flag_CI = (tmp&0xC0)>>6;
2843 td_coef = (tmp&0x0C)>>2;
2844
2845 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2846
2847 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2848
2849 return status;
2850 }
2851
INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)2852 MS_BOOL INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)
2853 {
2854 MS_U8 status = true;
2855 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2856 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2857 fd = tmp;
2858 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2859 ch_len = tmp;
2860 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2861 snr_sel = (tmp>>4)&0x03;
2862 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2863 pertone_num = tmp;
2864
2865 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2866
2867 return status;
2868 }
2869
INTERN_DVBT2_Get_CFO(void)2870 MS_BOOL INTERN_DVBT2_Get_CFO(void)
2871 {
2872
2873 float N = 0, FreqB = 0;
2874 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2875 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2876 MS_U8 reg_frz = 0, reg = 0;
2877 MS_U8 status = 0;
2878 MS_U8 u8BW = 8;
2879
2880 FreqB = (float)u8BW * 8 / 7;
2881
2882 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2883
2884 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2885
2886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2887 RegCfoTd = reg;
2888
2889 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2890 RegCfoTd = (RegCfoTd << 8)|reg;
2891
2892 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2893 RegCfoTd = (RegCfoTd << 8)|reg;
2894
2895 FreqCfoTd = (float)RegCfoTd;
2896
2897 if (RegCfoTd & 0x800000)
2898 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2899
2900 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2901
2902 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2903
2904 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2905 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2906
2907 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2908
2909 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2910 RegCfoFd = reg;
2911
2912 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2913 RegCfoFd = (RegCfoFd << 8)|reg;
2914
2915 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2916 RegCfoFd = (RegCfoFd << 8)|reg;
2917
2918 FreqCfoFd = (float)RegCfoFd;
2919
2920 if (RegCfoFd & 0x800000)
2921 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2922
2923 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2924
2925 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2926 RegIcfo = reg & 0x07;
2927
2928 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2929 RegIcfo = (RegIcfo << 8)|reg;
2930
2931 FreqIcfo = (float)RegIcfo;
2932
2933 if (RegIcfo & 0x400)
2934 FreqIcfo = FreqIcfo - (float)0x800;
2935
2936 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2937 reg = reg & 0x30;
2938
2939 switch (reg)
2940 {
2941 case 0x00: N = 2048; break;
2942 case 0x20: N = 4096; break;
2943 case 0x10:
2944 default: N = 8192; break;
2945 }
2946
2947 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2948 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2949 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2950 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2951 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2952
2953 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2954
2955 return status;
2956
2957 }
INTERN_DVBT2_Get_SFO(void)2958 MS_BOOL INTERN_DVBT2_Get_SFO(void)
2959 {
2960 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2961 MS_BOOL status = true;
2962 MS_U8 reg = 0;
2963 float FreqB = 9.143, FreqS = 45.473; //20.48
2964 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2965 float sfo_value = 0;
2966
2967 // get Reg_TDP_SFO,
2968 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2969 Reg_TDP_SFO = reg;
2970 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2971 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2972 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2973 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2974
2975 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2976
2977 // get Reg_FDP_SFO,
2978 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2979 Reg_FDP_SFO = reg;
2980 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2981 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2982 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2983 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2984
2985 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2986
2987 // get Reg_FSA_SFO,
2988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2989 Reg_FSA_SFO = reg;
2990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2991 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2993 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2994
2995 // get Reg_FSA_IN,
2996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2997 Reg_FSA_IN = reg;
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2999 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
3000 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
3001
3002 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
3003 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
3004
3005 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
3006 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
3007 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
3008
3009
3010 return status;
3011 }
3012
INTERN_DVBT2_Get_SYA_status(void)3013 void INTERN_DVBT2_Get_SYA_status(void)
3014 {
3015 MS_U8 status = true;
3016 MS_U8 sya_k = 0,reg = 0;
3017 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
3018
3019 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
3020 sya_k = reg;
3021
3022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
3023 sya_th = reg;
3024 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
3025 sya_th = (sya_th<<8)|reg;
3026
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
3028 sya_offset = reg;
3029 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
3030 sya_offset = (sya_offset<<8)|reg;
3031
3032 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
3033 len_m = reg;
3034 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
3035 len_m = (len_m<<8)|reg;
3036
3037 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
3038 len_b = reg;
3039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
3040 len_b = (len_b<<8)|reg;
3041
3042
3043 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
3044 len_a = reg;
3045 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
3046 len_a = (len_a<<8)|reg;
3047
3048
3049 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
3050 tracking_reg = reg;
3051
3052
3053 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
3054 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
3055
3056 return;
3057 }
3058
INTERN_DVBT2_Get_cci_status(void)3059 void INTERN_DVBT2_Get_cci_status(void)
3060 {
3061 MS_U8 status = true;
3062 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
3063
3064 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
3065 cci_fsweep = reg;
3066
3067 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
3068 cci_kp = reg;
3069
3070 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
3071
3072 return;
3073 }
3074
INTERN_DVBT2_Show_PRESFO_Info(void)3075 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void)
3076 {
3077 MS_U8 tmp = 0;
3078 MS_BOOL status = TRUE;
3079 printf("\n[SFO]");
3080 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
3081 printf("[%x]",tmp);
3082 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
3083 printf("[%x]",tmp);
3084 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
3085 printf("[%x]",tmp);
3086 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
3087 printf("[%x]",tmp);
3088 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
3089 printf("[%x]",tmp);
3090 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
3091 printf("[%x]",tmp);
3092 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
3093 printf("[%x]",tmp);
3094 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
3095 printf("[%x][End]",tmp);
3096
3097 return status;
3098 }
3099
INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 * locktime)3100 MS_BOOL INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 *locktime)
3101 {
3102 MS_BOOL status = true;
3103
3104 *locktime = 0xffff;
3105 printf("[dvbt]INTERN_DVBT2_Get_Lock_Time_Info not implement\n");
3106
3107 status = false;
3108 return status;
3109 }
3110
3111
INTERN_DVBT2_Show_Lock_Time_Info(void)3112 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void)
3113 {
3114 MS_U16 locktime = 0;
3115 MS_BOOL status = TRUE;
3116 status &= INTERN_DVBT2_Get_Lock_Time_Info(&locktime);
3117 printf("[DVBT]lock_time = %d ms\n",locktime);
3118 return status;
3119 }
3120
INTERN_DVBT2_Show_BER_Info(void)3121 MS_BOOL INTERN_DVBT2_Show_BER_Info(void)
3122 {
3123 MS_U8 tmp = 0;
3124 MS_BOOL status = TRUE;
3125 printf("\n[BER]");
3126 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
3127 printf("[%x,",tmp);
3128 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
3129 printf("%x]",tmp);
3130 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
3131 printf("[%x,",tmp);
3132 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
3133 printf("%x]",tmp);
3134 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
3135 printf("[%x,",tmp);
3136 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
3137 printf("%x][End]",tmp);
3138
3139 return status;
3140
3141 }
3142
3143
INTERN_DVBT2_Show_AGC_Info(void)3144 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void)
3145 {
3146 MS_U8 tmp = 0;
3147 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3148 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3149 MS_U16 if_agc_err = 0;
3150 MS_BOOL status = TRUE;
3151 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
3152
3153 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
3154 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
3155 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
3156 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
3157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
3158 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3159
3160
3161 // select IF gain to read
3162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3163 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3164
3165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3166 if_agc_gain = tmp;
3167 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3168 if_agc_gain = (if_agc_gain<<8)|tmp;
3169
3170
3171 // select d1 gain to read.
3172 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3173 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3174
3175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3176 d1_gain = tmp;
3177 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3178 d1_gain = (d1_gain<<8)|tmp;
3179
3180 // select d2 gain to read.
3181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3182 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3183
3184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3185 d2_gain = tmp;
3186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3187 d2_gain = (d2_gain<<8)|tmp;
3188
3189 // select IF gain err to read
3190 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3191 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3192
3193 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3194 if_agc_err = tmp;
3195 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3196 if_agc_err = (if_agc_err<<8)|tmp;
3197
3198 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3199 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3200 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3201
3202
3203
3204 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3205 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3206
3207 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3208 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3209
3210 return status;
3211
3212 }
3213
INTERN_DVBT2_Show_WIN_Info(void)3214 MS_BOOL INTERN_DVBT2_Show_WIN_Info(void)
3215 {
3216 MS_U8 tmp = 0;
3217 MS_U8 trigger = 0;
3218 MS_U16 win_len = 0;
3219
3220 MS_BOOL status = TRUE;
3221
3222 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3223 win_len = tmp;
3224 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3225 win_len = (win_len<<8)|tmp;
3226
3227 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3228
3229 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3230
3231 return status;
3232 }
3233
INTERN_DVBT2_Show_td_coeff(void)3234 void INTERN_DVBT2_Show_td_coeff(void)
3235 {
3236 MS_U8 status = true;
3237 MS_U8 w1 = 0,w2 = 0,reg = 0;
3238
3239 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3240 w1 = reg;
3241
3242 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3243 w2 = reg;
3244
3245 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3246
3247 return;
3248 }
3249
3250 /********************************************************
3251 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM
3252 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
3253 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256
3254 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE
3255 *Preamble(b12) : 0~1 => mixed, not_mixed
3256 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved
3257 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8
3258 *BW_Extend(b19) : 0~1 => normal, extension
3259 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved
3260 ********************************/
INTERN_DVBT2_Show_Modulation_info(void)3261 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void)
3262 {
3263 MS_BOOL bRet = TRUE;
3264 MS_U16 u16Data = 0;
3265
3266 char* cConStr[] = {"qpsk", "16qam", "64qam", "256qam"};
3267 char* cCRStr[] = {"1_2", "3_5", "2_3", "3_4", "4_5", "5_6"};
3268 char* cGIStr[] = {"1_32", "1_16", "1_8", "1_4", "1_128", "19_128", "19_256"};
3269 char* cFFTStr[] = {"2k", "8k", "4k", "1k", "16k", "32k", "8k", "32k"};
3270 char* cPreAStr[] = {"mixed", "not_mixed"};
3271 char* cS1SStr[] = {"t2_siso", "t2_miso", "non_t2", "reserved"};
3272 char* cPPSStr[] = {"PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", "PP8", "reserved"};
3273 char* cBWStr[] = {"normal", "extension"};
3274 char* cPAPRStr[] = {"none", "ace", "tr", "tr_and_ace", "reserved"};
3275
3276 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
3277 {
3278
3279 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_MODUL_MODE) == FALSE)
3280 {
3281 printf("T2_MODUL_MODE Error!\n");
3282 bRet = FALSE;
3283 }
3284 u16Data &= 0x07;
3285 //*L1_Info = (MS_U64)(u16Data);
3286 printf("T2 Constellation:%s\n", cConStr[u16Data]);
3287
3288 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_CODE_RATE) == FALSE)
3289 {
3290 printf(("T2_CODE_RATE Error!\n"));
3291 bRet = FALSE;
3292 }
3293 u16Data &= 0x07;
3294 //*L1_Info |= (MS_U64)(u16Data << 3);
3295 printf("T2 Code Rate:%s\n", cCRStr[u16Data]);
3296
3297 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_GUARD_INTERVAL) == FALSE)
3298 {
3299 printf("T2_GUARD_INTERVAL Error!\n");
3300 bRet = FALSE;
3301 }
3302 u16Data &= 0x07;
3303 //*L1_Info |= (MS_U64)(u16Data << 6);
3304 printf("T2 GI:%s\n", cGIStr[u16Data]);
3305
3306 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_FFT_VALUE) == FALSE)
3307 {
3308 printf("T2_FFT_VALUE Error!\n");
3309 bRet = FALSE;
3310 }
3311 u16Data &= 0x07;
3312 //*L1_Info |= (MS_U64)(u16Data << 9);
3313 printf("T2 FFT:%s\n", cFFTStr[u16Data]);
3314
3315 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PREAMBLE) == FALSE)
3316 {
3317 printf("T2_PREAMBLE Error!\n");
3318 bRet = FALSE;
3319 }
3320 u16Data &= 0x01;
3321 //*L1_Info |= (MS_U64)(u16Data << 12);
3322 printf("Preamble:%s\n", cPreAStr[u16Data]);
3323
3324 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_S1_SIGNALLING) == FALSE)
3325 {
3326 printf("T2_S1_SIGNALLING Error!\n");
3327 bRet = FALSE;
3328 }
3329 u16Data &= 0x03;
3330 if (u16Data > 2)
3331 u16Data = 3;
3332 //*L1_Info |= (MS_U64)(u16Data << 13);
3333 printf("S1 Signalling:%s\n", cS1SStr[u16Data]);
3334
3335 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PILOT_PATTERN) == FALSE)
3336 {
3337 printf("T2_PILOT_PATTERN Error!\n");
3338 bRet = FALSE;
3339 }
3340 u16Data &= 0x0F;
3341 if (u16Data > 7)
3342 u16Data = 8;
3343 //*L1_Info |= (MS_U64)(u16Data << 15);
3344 printf("PilotPattern:%s\n", cPPSStr[u16Data]);
3345
3346 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_BW_EXT) == FALSE)
3347 {
3348 printf("T2_BW_EXT Error!\n");
3349 bRet = FALSE;
3350 }
3351 u16Data &= 0x01;
3352 //*L1_Info |= (MS_U64)(u16Data << 19);
3353 printf("BW EXT:%s\n", cBWStr[u16Data]);
3354
3355 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PAPR_REDUCTION) == FALSE)
3356 {
3357 printf("T2_PAPR_REDUCTION Error!\n");
3358 bRet = FALSE;
3359 }
3360 u16Data &= 0x07;
3361 if (u16Data > 3)
3362 u16Data = 4;
3363 //*L1_Info |= (MS_U64)(u16Data << 20);
3364 printf("T2 PAPR:%s\n", cPAPRStr[u16Data]);
3365
3366 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_OFDM_SYMBOLS_PER_FRAME) == FALSE)
3367 {
3368 printf("T2_OFDM_SYMBOLS_PER_FRAME Error!\n");
3369 bRet = FALSE;
3370 }
3371 u16Data &= 0xFFF;
3372 //*L1_Info |= (MS_U64)(u16Data << 23);
3373 printf("T2 OFDM Symbols:%u\n", u16Data);
3374 }
3375 else
3376 {
3377 printf("INVALID\n");
3378 return FALSE;
3379 }
3380
3381 return bRet;
3382
3383 }
3384
3385
INTERN_DVBT2_Show_BER_PacketErr(void)3386 void INTERN_DVBT2_Show_BER_PacketErr(void)
3387 {
3388 float f_ber = 0;
3389 MS_U16 packetErr = 0;
3390 INTERN_DVBT2_GetPostLdpcBer(&f_ber);
3391 INTERN_DVBT2_GetPacketErr(&packetErr);
3392
3393 printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3394 return;
3395 }
3396
INTERN_DVBT2_Show_Lock_Info(void)3397 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void)
3398 {
3399
3400 printf("[dvbt]INTERN_DVBT2_Show_Lock_Info not implement!!!\n");
3401 return false;
3402 }
3403
3404
INTERN_DVBT2_Show_Demod_Info(void)3405 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void)
3406 {
3407 MS_U8 demod_state = 0;
3408 MS_BOOL status = true;
3409 static MS_U8 counter = 0;
3410
3411 INTERN_DVBT2_get_demod_state(&demod_state);
3412
3413 printf("==========[dvbt]state=%d\n",demod_state);
3414 if (demod_state < 5)
3415 {
3416 INTERN_DVBT2_Show_Demod_Version();
3417 INTERN_DVBT2_Show_AGC_Info();
3418 INTERN_DVBT2_Show_ACI_CI();
3419 }
3420 else if(demod_state < 8)
3421 {
3422 INTERN_DVBT2_Show_Demod_Version();
3423 INTERN_DVBT2_Show_AGC_Info();
3424 INTERN_DVBT2_Show_ACI_CI();
3425 INTERN_DVBT2_Show_ChannelLength();
3426 INTERN_DVBT2_Get_CFO();
3427 INTERN_DVBT2_Get_SFO();
3428 INTERN_DVBT2_Show_td_coeff();
3429 }
3430 else if(demod_state < 11)
3431 {
3432 INTERN_DVBT2_Show_Demod_Version();
3433 INTERN_DVBT2_Show_AGC_Info();
3434 INTERN_DVBT2_Show_ACI_CI();
3435 INTERN_DVBT2_Show_ChannelLength();
3436 INTERN_DVBT2_Get_CFO();
3437 INTERN_DVBT2_Get_SFO();
3438 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3439 INTERN_DVBT2_Get_SYA_status();
3440 INTERN_DVBT2_Show_td_coeff();
3441 }
3442 else if((demod_state == 11) && ((counter%4) == 0))
3443 {
3444 INTERN_DVBT2_Show_Demod_Version();
3445 INTERN_DVBT2_Show_AGC_Info();
3446 INTERN_DVBT2_Show_ACI_CI();
3447 INTERN_DVBT2_Show_ChannelLength();
3448 INTERN_DVBT2_Get_CFO();
3449 INTERN_DVBT2_Get_SFO();
3450 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3451 INTERN_DVBT2_Get_SYA_status();
3452 INTERN_DVBT2_Show_td_coeff();
3453 INTERN_DVBT2_Show_Modulation_info();
3454 INTERN_DVBT2_Show_BER_PacketErr();
3455 }
3456 else
3457 status = false;
3458
3459 printf("===========================\n");
3460 counter++;
3461
3462 return status;
3463 }
3464 #endif
3465
3466