1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #include <stdio.h>
101 #include <math.h>
102
103 #include "drvDMD_ISDBT.h"
104
105 #include "MsTypes.h"
106 #if DMD_ISDBT_UTOPIA_EN || DMD_ISDBT_UTOPIA2_EN
107 #include "drvDMD_common.h"
108 #include "halDMD_INTERN_common.h"
109 #endif
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114
115 #define DMD_ISDBT_CHIP_EULER 0x00
116 #define DMD_ISDBT_CHIP_NUGGET 0x01
117 #define DMD_ISDBT_CHIP_KAPPA 0x02
118 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
119 #define DMD_ISDBT_CHIP_NAPOLI 0x04
120 #define DMD_ISDBT_CHIP_MONACO 0x05
121 #define DMD_ISDBT_CHIP_MIAMI 0x06
122 #define DMD_ISDBT_CHIP_MUJI 0x07
123
124 #if defined(euler)
125 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
126 #elif defined(nugget)
127 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
128 #elif defined(kappa)
129 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
130 #elif defined(einstein)
131 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
132 #elif defined(napoli)
133 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
134 #elif defined(miami)
135 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
136 #elif defined(muji)
137 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
138 #else
139 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
140 #endif
141
142 //-------------------------------------------------------------------------------------------------
143 // Local Defines
144 //-------------------------------------------------------------------------------------------------
145
146 #define HAL_INTERN_ISDBT_DBINFO(y) //y
147 #ifndef MBRegBase
148 #define MBRegBase 0x112600UL
149 #endif
150 #ifndef DMDMcuBase
151 #define DMDMcuBase 0x103480UL
152 #endif
153
154 #define REG_ISDBT_LOCK_STATUS 0x36F5
155 #define ISDBT_TDP_REG_BASE 0x3700
156 #define ISDBT_FDP_REG_BASE 0x3800
157 #define ISDBT_FDPEXT_REG_BASE 0x3900
158 #define ISDBT_OUTER_REG_BASE 0x3A00
159
160 #define ISDBT_ACI_COEF_SIZE 92
161
162 //-------------------------------------------------------------------------------------------------
163 // Local Variables
164 //-------------------------------------------------------------------------------------------------
165
166 const MS_U8 INTERN_ISDBT_table[] = {
167 #include "DMD_INTERN_ISDBT.dat"
168 };
169
170 //-------------------------------------------------------------------------------------------------
171 // Global Variables
172 //-------------------------------------------------------------------------------------------------
173
174 extern MS_U8 u8DMD_ISDBT_DMD_ID;
175
176 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
177
178 //-------------------------------------------------------------------------------------------------
179 // Local Functions
180 //-------------------------------------------------------------------------------------------------
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)181 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
182 {
183 MS_U8 u8CheckCount;
184 MS_U8 u8CheckFlag;
185
186 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
187 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
188 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
189 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
190
191 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
192 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
193
194 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
195 {
196 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
197 if ((u8CheckFlag&0x01)==0)
198 break;
199 MsOS_DelayTask(1);
200 }
201
202 if (u8CheckFlag&0x01)
203 {
204 printf("ERROR: ISDBT INTERN DEMOD MBX WRITE TIME OUT!\n");
205 return FALSE;
206 }
207
208 return TRUE;
209 }
210
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)211 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
212 {
213 MS_U8 u8CheckCount;
214 MS_U8 u8CheckFlag;
215
216 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
217 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
218 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
219
220 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
221 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
222
223 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
224 {
225 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
226 if ((u8CheckFlag&0x02)==0)
227 {
228 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
229 }
230 MsOS_DelayTask(1);
231 }
232
233 if (u8CheckFlag&0x02)
234 {
235 printf("ERROR: ISDBT INTERN DEMOD MBX READ TIME OUT!\n");
236 return FALSE;
237 }
238
239 return TRUE;
240 }
241
_CALCULATE_SQI(float fber)242 static MS_U16 _CALCULATE_SQI(float fber)
243 {
244 float flog_ber;
245 MS_U16 u16SQI;
246
247 #ifdef MSOS_TYPE_LINUX
248 flog_ber = (float)log10((double)fber);
249 #else
250 if (fber != 0.0)
251 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
252 else
253 flog_ber = -8.0;//when fber=0 means u16SQI=100
254 #endif
255
256 //printf("dan fber = %f\n", fber);
257 //printf("dan flog_ber = %f\n", flog_ber);
258 // Part 2: transfer ber value to u16SQI value.
259 if (flog_ber <= ( - 7.0))
260 {
261 u16SQI = 100; //*quality = 100;
262 }
263 else if (flog_ber < -6.0)
264 {
265 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
266 }
267 else if (flog_ber < -5.5)
268 {
269 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
270 }
271 else if (flog_ber < -5.0)
272 {
273 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
274 }
275 else if (flog_ber < -4.5)
276 {
277 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
278 }
279 else if (flog_ber < -4.0)
280 {
281 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
282 }
283 else if (flog_ber < -3.5)
284 {
285 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
286 }
287 else if (flog_ber < -3.0)
288 {
289 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
290 }
291 else if (flog_ber < -2.5)
292 {
293 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
294 }
295 else if (flog_ber < -2.0)
296 {
297 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
298 }
299 else
300 {
301 u16SQI = 0;
302 }
303
304 return u16SQI;
305 }
306
307 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)308 static void _HAL_INTERN_ISDBT_InitClk(void)
309 {
310 printf("--------------DMD_ISDBT_CHIP_EULER--------------\n");
311
312 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
313
314 // Init by HKMCU
315 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
316 HAL_DMD_RIU_WriteByte(0x103301, 0x06);
317 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
318 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
319 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
320 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
321 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
322
323 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
324 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
325 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
326 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
327 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
328 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
329 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
330 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
331 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
332 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
333 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
334 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
335 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
336 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
337 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
338 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
339 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
340 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
341 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
342 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
343 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
344 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
345 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
346
347 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
348 }
349 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)350 static void _HAL_INTERN_ISDBT_InitClk(void)
351 {
352 MS_U8 u8Val = 0;
353
354 printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n");
355
356 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
357
358 // Init by HKMCU
359 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
360 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
361 HAL_DMD_RIU_WriteByte(0x103301, 0x06);
362 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
363 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
364 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
365 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
366 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
367 HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
368
369 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
370 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
371 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
372 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
373 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
374 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
375 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
376 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
377 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
378 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
379 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
380 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
381 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
382 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
383 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
384 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
385 HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
386 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
387 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
388 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
389 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
390 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
391 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
392 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
393
394 u8Val = HAL_DMD_RIU_ReadByte(0x1006F5);
395 HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
396
397 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
398 }
399 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)400 static void _HAL_INTERN_ISDBT_InitClk(void)
401 {
402 printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n");
403
404 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
405
406 // Init by HKMCU
407 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
408 HAL_DMD_RIU_WriteByte(0x103301, 0x06);
409 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
410 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
411 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
412 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
413 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
414
415 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
416 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
417 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
418 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
419 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
420 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
421 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
422 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
423 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
424 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
425 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
426 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
427 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
428 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
429 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
430 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
431 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
432 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
433 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
434 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
435 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
436 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
437 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
438
439 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
440 }
441 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)442 static void _HAL_INTERN_ISDBT_InitClk(void)
443 {
444 MS_U8 u8Val = 0;
445
446 printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n");
447
448 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
449
450 // Init by HKMCU
451 u8Val = HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
452 u8Val &= ~0x01;
453 HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
454
455 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
456 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
457 HAL_DMD_RIU_WriteByte(0x103301, 0x06);
458 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
459 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
460 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
461 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
462 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
463 HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
464
465 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
466 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
467 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
468 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
469 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
470 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
471 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
472 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
473 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
474 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
475 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
476 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
477 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
478 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
479 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
480 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
481 HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
482 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
483 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
484 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
485 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
486 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
487 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
488 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
489
490 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
491 }
492 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)493 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
494 {
495 MS_U8 u8Val = 0;
496
497 printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n");
498
499 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
500
501 // Init by HKMCU
502 u8Val = HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
503 u8Val &= ~0x01;
504 HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
505
506 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
507 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
508 HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
509 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
510 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
511 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
512 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
513 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
514 HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
515
516 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
517 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
518 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
519 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
520 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
521 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
522 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
523 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
524 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
525 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
526 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
527 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
528 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
529 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
530 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
531 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
532 HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
533 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
534 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
535 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
536 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
537 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
538 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
539 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
540
541 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
542 }
543 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)544 static void _HAL_INTERN_ISDBT_InitClk(void)
545 {
546 MS_U8 u8Val = 0;
547
548 printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n");
549
550 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
551
552 // Init by HKMCU
553 u8Val = HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
554 u8Val &= ~0x01;
555 HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
556
557 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
558 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
559 HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
560 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
561 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
562 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
563 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
564 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
565
566 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
567 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
568 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
569 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
570 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
571 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
572 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
573 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
574 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
575 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
576 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
577 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
578 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
579 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
580 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
581 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
582 HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
583 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
584 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
585 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
586 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
587 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
588 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
589 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
590 HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
591 HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
592 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
593 HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
594
595 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
596 }
597 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)598 static void _HAL_INTERN_ISDBT_InitClk(void)
599 {
600 printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n");
601
602 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
603
604 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
605 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
606 HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
607 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
608 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
609 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
610 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
611 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
612
613 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
614 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
615 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
616 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
617 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
618 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
619 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
620 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
621 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
622 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
623 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
624 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
625 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
626 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
627 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
628 HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
629 HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
630 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
631 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
632 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
633 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
634 HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
635 HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
636 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
637 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
638 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
639 HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
640 HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
641
642 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
643 }
644 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)645 static void _HAL_INTERN_ISDBT_InitClk(void)
646 {
647 printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n");
648
649 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
650
651 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
652 HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
653 HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
654 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
655 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
656 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
657 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
658 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
659 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
660
661 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
662 HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
663 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
664 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
665 HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
666 HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
667 HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
668 HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
669 HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
670 HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
671 HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
672 HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
673 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
674 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
675 HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
676 HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
677 HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
678 HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
679 HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
680 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
681 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
682 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
683 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
684 HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
685 HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
686 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
687 HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
688 HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
689 HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
690 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
691 HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
692 HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
693 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
694 HAL_DMD_RIU_WriteByte(0x112091, 0x46);
695 HAL_DMD_RIU_WriteByte(0x112090, 0x00);
696
697 HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
698 }
699
700 #else
_HAL_INTERN_ISDBT_InitClk(void)701 static void _HAL_INTERN_ISDBT_InitClk(void)
702 {
703 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
704 }
705 #endif
706
_HAL_INTERN_ISDBT_Ready(void)707 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
708 {
709 MS_U8 udata = 0x00;
710
711 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
712
713 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
714 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
715
716 MsOS_DelayTask(1);
717
718 udata = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
719
720 if (udata) return FALSE;
721
722 return TRUE;
723 }
724
_HAL_INTERN_ISDBT_Download(void)725 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
726 {
727 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
728
729 MS_U8 udata = 0x00;
730 MS_U16 i = 0;
731 MS_U16 fail_cnt = 0;
732 MS_U8 u8TmpData;
733 MS_U16 u16AddressOffset;
734 const MS_U8 *ISDBT_table;
735 MS_U16 u16Lib_size;
736
737 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
738 {
739 if (_HAL_INTERN_ISDBT_Ready())
740 {
741 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
742 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
743 MsOS_DelayTask(20);
744 return TRUE;
745 }
746 }
747
748 ISDBT_table = &INTERN_ISDBT_table[0];
749 u16Lib_size = sizeof(INTERN_ISDBT_table);
750
751 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
752 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
753
754 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
755
756 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
757 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
758 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
759 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
760
761 //// Load code thru VDMCU_IF ////
762 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
763
764 for (i = 0; i < u16Lib_size; i++)
765 {
766 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
767 }
768
769 //// Content verification ////
770 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
771
772 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
773 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
774
775 for (i = 0; i < u16Lib_size; i++)
776 {
777 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
778
779 if (udata != ISDBT_table[i])
780 {
781 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
782 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
783 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
784
785 if (fail_cnt++ > 10)
786 {
787 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
788 return FALSE;
789 }
790 }
791 }
792
793 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
794
795 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
796 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
797
798 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
799 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
800 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
801 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
802 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
803 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
804 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
805 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
806 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
807 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
808 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
809 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
810 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
811 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
812 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
813 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
814 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
815 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
816
817 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
818 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
819
820 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
821
822 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
823 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
824
825 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
826
827 MsOS_DelayTask(20);
828
829 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
830
831 return TRUE;
832 }
833
_HAL_INTERN_ISDBT_FWVERSION(void)834 static void _HAL_INTERN_ISDBT_FWVERSION(void)
835 {
836 MS_U8 data1,data2,data3;
837
838 _MBX_ReadReg(0x20C4, &data1);
839 _MBX_ReadReg(0x20C5, &data2);
840 _MBX_ReadReg(0x20C6, &data3);
841
842 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
843 }
844
_HAL_INTERN_ISDBT_Exit(void)845 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
846 {
847 MS_U8 u8CheckCount = 0;
848
849 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
850
851 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
852 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
853
854 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
855 {
856 MsOS_DelayTaskUs(10);
857
858 if (u8CheckCount++ == 0xFF)
859 {
860 printf(">> ISDBT Exit Fail!\n");
861 return FALSE;
862 }
863 }
864
865 printf(">> ISDBT Exit Ok!\n");
866
867 return TRUE;
868 }
869
_HAL_INTERN_ISDBT_SoftReset(void)870 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
871 {
872 MS_U8 u8Data = 0;
873
874 //Reset FSM
875 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
876
877 while (u8Data!=0x02)
878 {
879 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
880 }
881
882 return TRUE;
883 }
884
_HAL_INTERN_ISDBT_SetACICoef(void)885 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
886 {
887 return TRUE;
888 }
889
_HAL_INTERN_ISDBT_SetIsdbtMode(void)890 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
891 {
892 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
893 return _MBX_WriteReg(0x20C0, 0x04);
894 }
895
_HAL_INTERN_ISDBT_SetModeClean(void)896 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
897 {
898 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
899 return _MBX_WriteReg(0x20C0, 0x00);
900 }
901
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)902 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
903 {
904 MS_BOOL bCheckPass = FALSE;
905 MS_U8 u8Data;
906
907 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
908
909 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
910 bCheckPass = TRUE;
911
912 return bCheckPass;
913 }
914
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)915 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
916 {
917 MS_BOOL bCheckPass = FALSE;
918 MS_U8 u8Data;
919
920 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
921
922 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
923 bCheckPass = TRUE;
924
925 return bCheckPass;
926 }
927
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)928 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
929 {
930 MS_BOOL bCheckPass = FALSE;
931 MS_U8 u8Data;
932
933 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
934
935 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
936 bCheckPass = TRUE;
937
938 return bCheckPass;
939 }
940
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)941 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
942 {
943 MS_BOOL bCheckPass = FALSE;
944 MS_U8 u8Data;
945
946 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
947
948 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
949 bCheckPass = TRUE;
950
951 return bCheckPass;
952 }
953
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)954 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
955 {
956 MS_BOOL bRet = TRUE;
957 MS_U8 u8Data, u8CodeRate;
958
959 switch (eLayerIndex)
960 {
961 case E_ISDBT_Layer_A:
962 // [10:8] reg_tmcc_cur_convolution_code_rate_a
963 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
964 u8CodeRate = u8Data & 0x07;
965 break;
966 case E_ISDBT_Layer_B:
967 // [10:8] reg_tmcc_cur_convolution_code_rate_b
968 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
969 u8CodeRate = u8Data & 0x07;
970 break;
971 case E_ISDBT_Layer_C:
972 // [10:8] reg_tmcc_cur_convolution_code_rate_c
973 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
974 u8CodeRate = u8Data & 0x07;
975 break;
976 default:
977 u8CodeRate = 15;
978 break;
979 }
980
981 switch (u8CodeRate)
982 {
983 case 0:
984 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
985 break;
986 case 1:
987 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
988 break;
989 case 2:
990 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
991 break;
992 case 3:
993 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
994 break;
995 case 4:
996 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
997 break;
998 default:
999 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
1000 break;
1001 }
1002
1003 return bRet;
1004 }
1005
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)1006 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
1007 {
1008 MS_BOOL bRet = TRUE;
1009 MS_U8 u8Data, u8CP;
1010
1011 // [7:6] reg_mcd_out_cp
1012 // output cp -> 00: 1/4
1013 // 01: 1/8
1014 // 10: 1/16
1015 // 11: 1/32
1016 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1017
1018 u8CP = (u8Data >> 6) & 0x03;
1019
1020 switch (u8CP)
1021 {
1022 case 0:
1023 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
1024 break;
1025 case 1:
1026 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
1027 break;
1028 case 2:
1029 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
1030 break;
1031 case 3:
1032 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
1033 break;
1034 default:
1035 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_INVALID;
1036 break;
1037 }
1038
1039 return bRet;
1040 }
1041
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)1042 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
1043 {
1044 MS_BOOL bRet = TRUE;
1045 MS_U8 u8Data, u8Mode, u8Tdi;
1046
1047 // [5:4] reg_mcd_out_mode
1048 // output mode -> 00: 2k
1049 // 01: 4k
1050 // 10: 8k
1051 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1052
1053 u8Mode = (u8Data >> 4) & 0x03;
1054
1055 switch (eLayerIndex)
1056 {
1057 case E_ISDBT_Layer_A:
1058 // [14:12] reg_tmcc_cur_interleaving_length_a
1059 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1060 u8Tdi = (u8Data >> 4) & 0x07;
1061 break;
1062 case E_ISDBT_Layer_B:
1063 // [14:12] reg_tmcc_cur_interleaving_length_b
1064 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1065 u8Tdi = (u8Data >> 4) & 0x07;
1066 break;
1067 case E_ISDBT_Layer_C:
1068 // [14:12] reg_tmcc_cur_interleaving_length_c
1069 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1070 u8Tdi = (u8Data >> 4) & 0x07;
1071 break;
1072 default:
1073 u8Tdi = 15;
1074 break;
1075 }
1076
1077 // u8Tdi+u8Mode*4
1078 // => 0~3: 2K
1079 // => 4~7: 4K
1080 // => 8~11:8K
1081 switch (u8Tdi+u8Mode*4)
1082 {
1083 case 0:
1084 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
1085 break;
1086 case 1:
1087 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
1088 break;
1089 case 2:
1090 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
1091 break;
1092 case 3:
1093 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
1094 break;
1095 case 4:
1096 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
1097 break;
1098 case 5:
1099 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
1100 break;
1101 case 6:
1102 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
1103 break;
1104 case 7:
1105 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
1106 break;
1107 case 8:
1108 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
1109 break;
1110 case 9:
1111 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
1112 break;
1113 case 10:
1114 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
1115 break;
1116 case 11:
1117 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
1118 break;
1119 default:
1120 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
1121 break;
1122 }
1123
1124 return bRet;
1125 }
1126
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)1127 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
1128 {
1129 MS_BOOL bRet = TRUE;
1130 MS_U8 u8Data, u8Mode;
1131
1132 // [5:4] reg_mcd_out_mode
1133 // output mode -> 00: 2k
1134 // 01: 4k
1135 // 10: 8k
1136 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1137
1138 u8Mode = (u8Data >> 4) & 0x03;
1139
1140 switch (u8Mode)
1141 {
1142 case 0:
1143 *peIsdbtFFT = E_ISDBT_FFT_2K;
1144 break;
1145 case 1:
1146 *peIsdbtFFT = E_ISDBT_FFT_4K;
1147 break;
1148 case 2:
1149 *peIsdbtFFT = E_ISDBT_FFT_8K;
1150 break;
1151 default:
1152 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
1153 break;
1154 }
1155
1156 return bRet;
1157 }
1158
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)1159 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
1160 {
1161 MS_BOOL bRet = TRUE;
1162 MS_U8 u8Data, u8QAM;
1163
1164 switch(eLayerIndex)
1165 {
1166 case E_ISDBT_Layer_A:
1167 // [6:4] reg_tmcc_cur_carrier_modulation_a
1168 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
1169 u8QAM = (u8Data >> 4) & 0x07;
1170 break;
1171 case E_ISDBT_Layer_B:
1172 // [6:4] reg_tmcc_cur_carrier_modulation_b
1173 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
1174 u8QAM = (u8Data >> 4) & 0x07;
1175 break;
1176 case E_ISDBT_Layer_C:
1177 // [6:4] reg_tmcc_cur_carrier_modulation_c
1178 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
1179 u8QAM = (u8Data >> 4) & 0x07;
1180 break;
1181 default:
1182 u8QAM = 15;
1183 break;
1184 }
1185
1186 switch(u8QAM)
1187 {
1188 case 0:
1189 *peIsdbtConstellation = E_ISDBT_DQPSK;
1190 break;
1191 case 1:
1192 *peIsdbtConstellation = E_ISDBT_QPSK;
1193 break;
1194 case 2:
1195 *peIsdbtConstellation = E_ISDBT_16QAM;
1196 break;
1197 case 3:
1198 *peIsdbtConstellation = E_ISDBT_64QAM;
1199 break;
1200 default:
1201 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
1202 break;
1203 }
1204
1205 return bRet;
1206 }
1207
_HAL_INTERN_ISDBT_ReadIFAGC(void)1208 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
1209 {
1210 MS_U8 data = 0;
1211
1212 _MBX_ReadReg(0x28FD, &data);
1213
1214 return data;
1215 }
1216
_HAL_INTERN_ISDBT_GetFreqOffset(float * pFreqOff)1217 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
1218 {
1219 MS_BOOL bRet = TRUE;
1220 MS_U8 u8Data;
1221 MS_S32 s32TdCfoRegValue = 0;
1222 float fTdCfoFreq = 0.0;
1223 MS_S32 s32FdCfoRegValue = 0;
1224 float fFdCfoFreq = 0.0;
1225 MS_S16 s16IcfoRegValue = 0.0;
1226 float fICfoFreq = 0.0;
1227
1228 //Get TD CFO
1229 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
1230 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
1231
1232 //read td_freq_error
1233 //Read <29,38>
1234 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
1235 s32TdCfoRegValue = u8Data;
1236 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
1237 s32TdCfoRegValue |= u8Data << 8;
1238 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
1239 s32TdCfoRegValue = u8Data << 16;
1240 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
1241 s32TdCfoRegValue |= u8Data << 24;
1242
1243 if (u8Data >= 0x10)
1244 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
1245
1246 s32TdCfoRegValue >>=4;
1247
1248 //TD_cfo_Hz = RegCfoTd * fb
1249 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
1250 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
1251
1252 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
1253 fTdCfoFreq = fTdCfoFreq * 8126980.0;
1254
1255 //Get FD CFO
1256 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1257 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
1258 //load
1259 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1260 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1261
1262 //read CFO_KI
1263 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
1264 s32FdCfoRegValue = u8Data;
1265 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
1266 s32FdCfoRegValue |= u8Data << 8;
1267 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
1268 s32FdCfoRegValue |= u8Data << 16;
1269 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
1270 s32FdCfoRegValue |= u8Data << 24;
1271
1272 if(u8Data >= 0x01)
1273 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
1274
1275 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1276 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
1277 //load
1278 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1279 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1280
1281 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
1282 fFdCfoFreq = fFdCfoFreq * 8126980.0;
1283
1284 //Get ICFO
1285 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
1286 s16IcfoRegValue = u8Data;
1287 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
1288 s16IcfoRegValue |= u8Data << 8;
1289 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
1290
1291 if(s16IcfoRegValue >= 0x400)
1292 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
1293
1294 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
1295
1296 if((u8Data & 0x30) == 0x0000) // 2k
1297 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
1298 else if((u8Data & 0x0030) == 0x0010) // 4k
1299 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
1300 else //if(u16data & 0x0030 == 0x0020) // 8k
1301 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
1302
1303 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
1304
1305 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
1306
1307 return bRet;
1308 }
1309
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,float * pfber)1310 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
1311 {
1312 MS_BOOL bRet = TRUE;
1313 MS_U8 u8Data;
1314 MS_U16 u16BerValue = 0;
1315 MS_U32 u32BerPeriod = 0;
1316
1317 // reg_rd_freezeber
1318 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
1319 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
1320
1321 if (eLayerIndex == E_ISDBT_Layer_A)
1322 {
1323 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
1324 u16BerValue=u8Data;
1325 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
1326 u16BerValue |= (u8Data << 8);
1327 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
1328 u32BerPeriod = (u8Data&0x3F);
1329 u32BerPeriod <<= 16;
1330 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
1331 u32BerPeriod |= u8Data;
1332 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
1333 u32BerPeriod |= (u8Data << 8);
1334 }
1335 else if (eLayerIndex == E_ISDBT_Layer_B)
1336 {
1337 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
1338 u16BerValue=u8Data;
1339 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
1340 u16BerValue |= (u8Data << 8);
1341 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
1342 u32BerPeriod = (u8Data&0x3F);
1343 u32BerPeriod <<= 16;
1344 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
1345 u32BerPeriod |= u8Data;
1346 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
1347 u32BerPeriod |= (u8Data << 8);
1348 }
1349 else if (eLayerIndex == E_ISDBT_Layer_C)
1350 {
1351 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
1352 u16BerValue=u8Data;
1353 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
1354 u16BerValue |= (u8Data << 8);
1355 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
1356 u32BerPeriod = (u8Data&0x003F);
1357 u32BerPeriod <<= 16;
1358 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
1359 u32BerPeriod |= u8Data;
1360 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
1361 u32BerPeriod |= (u8Data << 8);
1362 }
1363 else
1364 {
1365 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
1366 bRet = FALSE;
1367 }
1368
1369 // reg_rd_freezeber
1370 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
1371 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
1372
1373 u32BerPeriod <<= 8; // *256
1374
1375 if(u32BerPeriod == 0) u32BerPeriod = 1;
1376
1377 *pfber = (float)u16BerValue/u32BerPeriod;
1378
1379 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
1380
1381 return bRet;
1382 }
1383
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,float * pfber)1384 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
1385 {
1386 MS_BOOL bRet = TRUE;
1387 MS_U8 u8Data, u8FrzData;
1388 MS_U32 u32BerValue = 0;
1389 MS_U16 u16BerPeriod = 0;
1390
1391 // reg_rd_freezeber
1392 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
1393 u8Data = u8FrzData | 0x01;
1394 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
1395
1396 if (eLayerIndex == E_ISDBT_Layer_A)
1397 {
1398 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
1399 u32BerValue = u8Data;
1400 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
1401 u32BerValue |= u8Data << 8;
1402 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
1403 u32BerValue |= u8Data << 16;
1404 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
1405 u32BerValue |= u8Data << 24;
1406
1407 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
1408 u16BerPeriod = u8Data;
1409 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
1410 u16BerPeriod |= u8Data << 8;
1411 }
1412 else if (eLayerIndex == E_ISDBT_Layer_B)
1413 {
1414 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
1415 u32BerValue = u8Data;
1416 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
1417 u32BerValue |= u8Data << 8;
1418 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
1419 u32BerValue |= u8Data << 16;
1420 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
1421 u32BerValue |= u8Data << 24;
1422
1423 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
1424 u16BerPeriod = u8Data;
1425 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
1426 u16BerPeriod |= u8Data << 8;
1427 }
1428 else if (eLayerIndex == E_ISDBT_Layer_C)
1429 {
1430 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
1431 u32BerValue = u8Data;
1432 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
1433 u32BerValue |= u8Data << 8;
1434 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
1435 u32BerValue |= u8Data << 16;
1436 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
1437 u32BerValue |= u8Data << 24;
1438
1439 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
1440 u16BerPeriod = u8Data;
1441 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
1442 u16BerPeriod |= u8Data << 8;
1443 }
1444 else
1445 {
1446 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
1447 bRet = FALSE;
1448 }
1449
1450 // reg_rd_freezeber
1451 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
1452
1453 if(u16BerPeriod == 0) u16BerPeriod = 1;
1454
1455 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
1456
1457 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
1458
1459 return bRet;
1460 }
1461
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)1462 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
1463 {
1464 float fber;
1465 MS_BOOL bRet = TRUE;
1466 EN_ISDBT_Layer eLayerIndex;
1467 MS_U16 u16SQI;
1468
1469 // Tmp solution
1470 eLayerIndex = E_ISDBT_Layer_A;
1471
1472 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
1473 {
1474 //printf("Dan Demod unlock!!!\n");
1475 u16SQI = 0;
1476 }
1477 else
1478 {
1479 // Part 1: get ber value from demod.
1480 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
1481
1482 u16SQI = _CALCULATE_SQI(fber);
1483 }
1484
1485 //printf("dan SQI = %d\n", SQI);
1486 return u16SQI;
1487 }
1488
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)1489 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
1490 {
1491 float fber;
1492 MS_BOOL bRet = TRUE;
1493 EN_ISDBT_Layer eLayerIndex;
1494 MS_U16 u16SQI;
1495
1496 // Tmp solution
1497 eLayerIndex = E_ISDBT_Layer_B;
1498
1499 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
1500 {
1501 //printf("Dan Demod unlock!!!\n");
1502 u16SQI = 0;
1503 }
1504 else
1505 {
1506 // Part 1: get ber value from demod.
1507 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
1508
1509 u16SQI = _CALCULATE_SQI(fber);
1510 }
1511
1512 //printf("dan SQI = %d\n", SQI);
1513 return u16SQI;
1514 }
1515
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)1516 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
1517 {
1518 float fber;
1519 MS_BOOL bRet = TRUE;
1520 EN_ISDBT_Layer eLayerIndex;
1521 MS_U16 u16SQI;
1522
1523 // Tmp solution
1524 eLayerIndex = E_ISDBT_Layer_C;
1525
1526 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
1527 {
1528 //printf("Dan Demod unlock!!!\n");
1529 u16SQI = 0;
1530 }
1531 else
1532 {
1533 // Part 1: get ber value from demod.
1534 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
1535
1536 u16SQI = _CALCULATE_SQI(fber);
1537 }
1538
1539 //printf("dan SQI = %d\n", SQI);
1540 return u16SQI;
1541 }
1542
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)1543 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
1544 {
1545 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
1546 MS_U16 u16SQI;
1547 EN_ISDBT_Layer eLayerIndex;
1548 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
1549
1550 //Get modulation of each layer
1551 eLayerIndex = E_ISDBT_Layer_A;
1552 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
1553 eLayerIndex = E_ISDBT_Layer_B;
1554 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
1555 eLayerIndex = E_ISDBT_Layer_C;
1556 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
1557
1558 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
1559 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
1560 else
1561 s8LayerAValue = -1;
1562
1563 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
1564 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
1565 else
1566 s8LayerBValue = -1;
1567
1568 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
1569 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
1570 else
1571 s8LayerCValue = -1;
1572
1573 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
1574 if (s8LayerAValue >= s8LayerBValue)
1575 {
1576 if (s8LayerCValue >= s8LayerAValue)
1577 {
1578 //Get Layer C u16SQI
1579 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
1580 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
1581 }
1582 else //A>C
1583 {
1584 //Get Layer A u16SQI
1585 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
1586 //printf("dan u16SQI Layer A: %d\n", u16SQI);
1587 }
1588 }
1589 else // B >= A
1590 {
1591 if (s8LayerCValue >= s8LayerBValue)
1592 {
1593 //Get Layer C u16SQI
1594 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
1595 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
1596 }
1597 else //B>C
1598 {
1599 //Get Layer B u16SQI
1600 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
1601 //printf("dan u16SQI Layer B: %d\n", u16SQI);
1602 }
1603 }
1604
1605 return u16SQI;
1606 }
1607
_HAL_INTERN_ISDBT_GetSNR(float * pf_snr)1608 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
1609 {
1610 MS_BOOL bRet = TRUE;
1611 MS_U8 u8Data;
1612 MS_U32 u32RegSNR = 0;
1613 MS_U16 u16RegSnrObsNum = 0;
1614 float fSNRAvg = 0.0;
1615
1616 //set freeze
1617 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1618 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
1619 //load
1620 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1621 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1622
1623 // ==============Average SNR===============//
1624 // [26:0] reg_snr_accu
1625 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
1626 u32RegSNR = u8Data&0x07;
1627 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
1628 u32RegSNR = (u32RegSNR<<8) | u8Data;
1629 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
1630 u32RegSNR = (u32RegSNR<<8) | u8Data;
1631 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
1632 u32RegSNR = (u32RegSNR<<8) | u8Data;
1633
1634 // [12:0] reg_snr_observe_sum_num
1635 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
1636 u16RegSnrObsNum = u8Data&0x1f;
1637 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
1638 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
1639
1640 //release freeze
1641 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1642 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
1643 //load
1644 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1645 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1646
1647 if (u16RegSnrObsNum == 0)
1648 u16RegSnrObsNum = 1;
1649
1650 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
1651
1652 if (fSNRAvg == 0) //protect value 0
1653 fSNRAvg = 0.01;
1654
1655 #ifdef MSOS_TYPE_LINUX
1656 *pf_snr = 10*(float)log10f((double)fSNRAvg/2);
1657 #else
1658 *pf_snr = 10*(float)Log10Approx((double)fSNRAvg/2);
1659 #endif
1660
1661 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
1662
1663 return bRet;
1664 }
1665
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)1666 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
1667 {
1668 MS_U8 bRet = true;
1669 MS_U8 u8Data, u8FrzData;
1670 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
1671
1672 // Read packet errors of three layers
1673 // OUTER_FUNCTION_ENABLE
1674 // [8] reg_biterr_num_pcktprd_freeze
1675 // Freeze Packet error
1676 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
1677 u8Data = u8FrzData | 0x01;
1678 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
1679
1680 switch(eLayerIndex)
1681 {
1682 case E_ISDBT_Layer_A:
1683 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
1684 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
1685 u16PacketErrA = u8Data << 8;
1686 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
1687 u16PacketErrA = u16PacketErrA | u8Data;
1688 *pu16PacketErr = u16PacketErrA;
1689 break;
1690 case E_ISDBT_Layer_B:
1691 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
1692 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
1693 u16PacketErrB = u8Data << 8;
1694 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
1695 u16PacketErrB = u16PacketErrB | u8Data;
1696 *pu16PacketErr = u16PacketErrB;
1697 break;
1698 case E_ISDBT_Layer_C:
1699 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
1700 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
1701 u16PacketErrC = u8Data << 8;
1702 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
1703 u16PacketErrC = u16PacketErrC | u8Data;
1704 *pu16PacketErr = u16PacketErrC;
1705 break;
1706 default:
1707 *pu16PacketErr = 0xFFFF;
1708 break;
1709 }
1710
1711 // Unfreeze Packet error
1712 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
1713
1714 return bRet;
1715 }
1716
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)1717 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
1718 {
1719 return _MBX_ReadReg(u16Addr, pu8Data);
1720 }
1721
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)1722 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
1723 {
1724 return _MBX_WriteReg(u16Addr, u8Data);
1725 }
1726
1727 //-------------------------------------------------------------------------------------------------
1728 // Global Functions
1729 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)1730 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
1731 {
1732 MS_BOOL bResult = TRUE;
1733
1734 switch(eCmd)
1735 {
1736 case DMD_ISDBT_HAL_CMD_Exit:
1737 bResult = _HAL_INTERN_ISDBT_Exit();
1738 break;
1739 case DMD_ISDBT_HAL_CMD_InitClk:
1740 _HAL_INTERN_ISDBT_InitClk();
1741 break;
1742 case DMD_ISDBT_HAL_CMD_Download:
1743 bResult = _HAL_INTERN_ISDBT_Download();
1744 break;
1745 case DMD_ISDBT_HAL_CMD_FWVERSION:
1746 _HAL_INTERN_ISDBT_FWVERSION();
1747 break;
1748 case DMD_ISDBT_HAL_CMD_SoftReset:
1749 bResult = _HAL_INTERN_ISDBT_SoftReset();
1750 break;
1751 case DMD_ISDBT_HAL_CMD_SetACICoef:
1752 bResult = _HAL_INTERN_ISDBT_SetACICoef();
1753 break;
1754 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
1755 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
1756 break;
1757 case DMD_ISDBT_HAL_CMD_SetModeClean:
1758 bResult = _HAL_INTERN_ISDBT_SetModeClean();
1759 break;
1760 case DMD_ISDBT_HAL_CMD_Active:
1761 break;
1762 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
1763 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
1764 break;
1765 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
1766 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
1767 break;
1768 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
1769 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
1770 break;
1771 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
1772 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
1773 break;
1774 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
1775 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
1776 break;
1777 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
1778 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
1779 break;
1780 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
1781 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
1782 break;
1783 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
1784 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
1785 break;
1786 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
1787 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
1788 break;
1789 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
1790 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
1791 break;
1792 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
1793 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
1794 break;
1795 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
1796 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
1797 break;
1798 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
1799 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
1800 break;
1801 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
1802 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
1803 break;
1804 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
1805 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
1806 break;
1807 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
1808 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
1809 break;
1810 case DMD_ISDBT_HAL_CMD_GetSNR:
1811 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
1812 break;
1813 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
1814 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
1815 break;
1816 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
1817 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
1818 break;
1819 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
1820 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
1821 break;
1822 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
1823 break;
1824 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
1825 break;
1826 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
1827 break;
1828 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
1829 break;
1830 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
1831 break;
1832 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
1833 break;
1834 case DMD_ISDBT_HAL_CMD_GET_REG:
1835 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
1836 break;
1837 case DMD_ISDBT_HAL_CMD_SET_REG:
1838 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
1839 break;
1840 default:
1841 break;
1842 }
1843
1844 return bResult;
1845 }
1846
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)1847 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
1848 {
1849 return TRUE;
1850 }
1851
1852