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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include <math.h>
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 //#include "apiPWS.h"
109
110 #include "MsTypes.h"
111 #include "drvBDMA.h"
112 //#include "drvIIC.h"
113 //#include "msAPI_Tuner.h"
114 //#include "msAPI_MIU.h"
115 //#include "BinInfo.h"
116 //#include "halVif.h"
117 #include "drvDMD_INTERN_DVBC.h"
118 #include "halDMD_INTERN_DVBC.h"
119 #include "halDMD_INTERN_common.h"
120 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
121 #include "InfoBlock.h"
122 #endif
123 #include "drvMMIO.h"
124 //#include "TDAG4D01A_SSI_DVBT.c"
125 #include "drvDMD_VD_MBX.h"
126 #include "ULog.h"
127 #define TEST_EMBEDED_DEMOD 0
128 //U8 load_data_variable=1;
129 //-----------------------------------------------------------------------
130 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
131
132 #define TDE_REG_BASE 0x2400
133 #define INNC_REG_BASE 0x2A00
134 #define EQE_REG_BASE 0x2B00
135 //#define EQE2_REG_BASE 0x2d00
136
137
138
139 #ifdef MS_DEBUG
140 #define DBG_INTERN_DVBC(x) x
141 #define DBG_GET_SIGNAL_DVBC(x) x
142 #define DBG_INTERN_DVBC_TIME(x) x
143 #define DBG_INTERN_DVBC_LOCK(x) x
144 #define INTERN_DVBC_INTERNAL_DEBUG 1
145 #else
146 #define DBG_INTERN_DVBC(x) //x
147 #define DBG_GET_SIGNAL_DVBC(x) //x
148 #define DBG_INTERN_DVBC_TIME(x) //x
149 #define DBG_INTERN_DVBC_LOCK(x) //x
150 #define INTERN_DVBC_INTERNAL_DEBUG 0
151 #endif
152 #define DBG_DUMP_LOAD_DSP_TIME 0
153
154
155 #define SIGNAL_LEVEL_OFFSET 0.00f
156 #define TAKEOVERPOINT -60.0f
157 #define TAKEOVERRANGE 0.5f
158 #define LOG10_OFFSET -0.21f
159 #define INTERN_DVBC_USE_SAR_3_ENABLE 0
160 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
161
162 #define TUNER_IF 5000
163
164 #define TS_SER_C 0x00 //0: parallel 1:serial
165
166 #if (INTERN_DVBC_TS_SERIAL_INVERSION)
167 #define TS_INV_C 0x01
168 #else
169 #define TS_INV_C 0x00
170 #endif
171
172 #define DVBC_FS 45473
173 #define CFG_ZIF 0x00 //For ZIF ,FC=0
174 #define FC_H_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF)>>8)&0xFF) : (((TUNER_IF-DVBC_FS)>>8)&0xFF) )
175 #define FC_L_C ( (DVBC_FS-TUNER_IF)>0 ? (((DVBC_FS-TUNER_IF))&0xFF) : (((TUNER_IF-DVBC_FS))&0xFF) )
176 #define FS_H_C ((DVBC_FS>>8)&0xFF) // FS
177 #define FS_L_C (DVBC_FS&0xFF)
178 #define AUTO_SCAN_C 0x00 // Auto Scan - 0:channel change, 1:auto-scan
179 #define IQ_SWAP_C 0x01
180 #define PAL_I_C 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
181 // Bxko 6875, 6900, 7000, 6125, 4000, 6950
182 // Symbol Rate: 6875 = 0x1ADB
183 // Symbol Rate: 6900 = 0x1AF4
184 // Symbol Rate: 7000 = 0x1B58
185 // Symbol Rate: 4000 = 0x0FA0
186 // Symbol Rate: 6125 = 0x17ED
187 #define SR0_H 0x1A
188 #define SR0_L 0xF4 //6900
189 #define SR1_H 0x1B
190 #define SR1_L 0x58 //7000
191 #define SR2_H 0x17
192 #define SR2_L 0xED //6125
193 #define SR3_H 0x0F
194 #define SR3_L 0xA0 //4000
195 #define SR4_H 0x1B
196 #define SR4_L 0x26 //6950
197 #define SR5_H 0x1A
198 #define SR5_L 0xDB //6875
199 #define SR6_H 0x1C
200 #define SR6_L 0x20 //7200
201 #define SR7_H 0x1C
202 #define SR7_L 0x52 //7250
203 #define SR8_H 0x0B
204 #define SR8_L 0xB8 //3000
205 #define SR9_H 0x03
206 #define SR9_L 0xE8 //1000
207 #define SR10_H 0x07
208 #define SR10_L 0xD0 //2000
209 #define SR11_H 0x00
210 #define SR11_L 0x00 //0000
211
212
213 #define QAM 0x04 // QAM: 0:16, 1:32, 2:64, 3:128, 4:256
214
215 // SAR dependent
216 #define NO_SIGNAL_TH_A 0xA3
217 // Tuner dependent
218 #define NO_SIGNAL_TH_B_L 0xFF //0x00 , Gain
219 #define NO_SIGNAL_TH_B_H 0xFF //0xDD
220 #define NO_SIGNAL_TH_C_L 0xff //0x64 , Err
221 #define NO_SIGNAL_TH_C_H 0xff //0x00
222 #define DAGC1_REF 0x70
223 #define DAGC2_REF 0x30
224 #define AGC_REF_L 0xF0
225 #define AGC_REF_H 0x02
226
227 #define INTERN_AUTO_SR_C 1
228 #define INTERN_AUTO_QAM_C 1
229
230 #define ATV_DET_EN 1
231
232 // Need to update when:
233 // Case#1: New add DSP parameters
234 // Case#2: Use exist DSP parameters to another applications/functions
235 #define UTOPIA_DRIVER_VERSION 0x01 // Update by user.
236
237 #if 0
238 MS_U8 INTERN_DVBC_DSPREG[] =
239 { 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, // 00h ~ 07h
240 INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, NO_SIGNAL_TH_C_H, 0x00, // 08h ~ 0fh
241 0x00, CFG_ZIF, 0x00, FC_L_C, FC_H_C, FS_L_C, FS_H_C, SR0_L, // 10h ~ 17h
242 SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, SR3_H, 0x00, // 18h ~ 1fh
243 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, // 20h ~27h
244 };
245 #else
246 MS_U8 INTERN_DVBC_DSPREG[] =
247 {
248 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, AUTO_SCAN_C, INTERN_AUTO_SR_C, INTERN_AUTO_QAM_C, ATV_DET_EN, 0x00, 0x00, 0x01, 0x00, //00-0F
249 0x00, 0x00, CFG_ZIF, FS_L_C, FS_H_C, 0x88, 0x13, FC_L_C, FC_H_C, SR0_L, SR0_H, SR1_L, SR1_H, SR2_L, SR2_H, SR3_L, //10-1F
250 SR3_H, SR4_L, SR4_H, SR5_L, SR5_H, SR6_L, SR6_H, SR7_L, SR7_H, SR8_L, SR8_H, SR9_L, SR9_H, SR10_L, SR10_H, SR11_L, //20-2F
251 SR11_H, 0x00, QAM, IQ_SWAP_C, PAL_I_C, TS_SER_C, 0x00, TS_INV_C, 0x00, 0x00, AGC_REF_L, AGC_REF_H, 0x90, 0xa0, 0x03, 0x05, //30-3F
252 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, NO_SIGNAL_TH_B_L, NO_SIGNAL_TH_B_H, NO_SIGNAL_TH_C_L, //40-4F
253 NO_SIGNAL_TH_C_H, 0x00, 0x00, 0x00, 0x00, 0x00, DAGC1_REF, DAGC2_REF, 0x73, 0x73, 0x73, 0x73, 0x73, 0x83, 0x83, 0x73, //50-5F
254 0x62, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //60-6C
255 };
256 #endif
257 #define TS_SERIAL_OUTPUT_IF_CI_REMOVED 1 // _UTOPIA
258
259 //-----------------------------------------------------------------------
260 /****************************************************************
261 *Local Variables *
262 ****************************************************************/
263
264 //static MS_BOOL TPSLock = 0;
265 static MS_U32 u32ChkScanTimeStartDVBC = 0;
266 static MS_U8 g_dvbc_lock = 0;
267 static float intern_dvb_c_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
268
269 //Global Variables
270 S_CMDPKTREG gsCmdPacketDVBC;
271 //MS_U8 gCalIdacCh0, gCalIdacCh1;
272 static MS_BOOL bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
273 static MS_U32 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
274 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
275 MS_U8 INTERN_DVBC_table[] = {
276 #include "fwDMD_INTERN_DVBC.dat"
277 };
278
279 #endif
280
281 MS_BOOL INTERN_DVBC_Show_Demod_Version(void);
282 // MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber);
283 // MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr);
284 //MS_BOOL INTERN_DVBC_GetSNR(float *f_snr);
285 // MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff);
286 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode);
287 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate);
288 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData);
289
290 #if (INTERN_DVBC_INTERNAL_DEBUG)
291 void INTERN_DVBC_info(void);
292 MS_BOOL INTERN_DVBC_Show_AGC_Info(void);
293 #endif
294
INTERN_DVBC_DSPReg_Init(const MS_U8 * u8DVBC_DSPReg,MS_U8 u8Size)295 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size)
296 {
297 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
298 MS_U8 status = TRUE;
299 MS_U16 u16DspAddr = 0;
300
301 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init\n");
302
303 #if 0//def MS_DEBUG
304 {
305 MS_U8 u8buffer[256];
306 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init Reset\n");
307 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
308 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
309
310 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
311 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
312 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init ReadBack, should be all 0\n");
313 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
314 ULOGD("Utopia","%x ", u8buffer[idx]);
315 ULOGD("Utopia","\n");
316
317 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init Value\n");
318 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
319 ULOGD("Utopia","%x ", INTERN_DVBC_DSPREG[idx]);
320 ULOGD("Utopia","\n");
321 }
322 #endif
323
324 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
325 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBC_DSPREG[idx]);
326
327 // readback to confirm.
328 #ifdef MS_DEBUG
329 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
330 {
331 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
332 if (u8RegRead != INTERN_DVBC_DSPREG[idx])
333 {
334 ULOGE("DEMOD","[Error]INTERN_DVBC_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBC_DSPREG[idx],u8RegRead);
335 }
336 }
337 #endif
338
339 if (u8DVBC_DSPReg != NULL)
340 {
341 if (1 == u8DVBC_DSPReg[0])
342 {
343 u8DVBC_DSPReg+=2;
344 for (idx = 0; idx<u8Size; idx++)
345 {
346 u16DspAddr = *u8DVBC_DSPReg;
347 u8DVBC_DSPReg++;
348 u16DspAddr = (u16DspAddr) + ((*u8DVBC_DSPReg)<<8);
349 u8DVBC_DSPReg++;
350 u8Mask = *u8DVBC_DSPReg;
351 u8DVBC_DSPReg++;
352 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
353 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBC_DSPReg) & (u8Mask));
354 u8DVBC_DSPReg++;
355 ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite);
356 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
357 }
358 }
359 else
360 {
361 ULOGE("DEMOD","FATAL: parameter version incorrect\n");
362 }
363 }
364
365 #if 0//def MS_DEBUG
366 {
367 MS_U8 u8buffer[256];
368 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
369 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
370 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init ReadBack\n");
371 for (idx = 0; idx<sizeof(INTERN_DVBC_DSPREG); idx++)
372 ULOGD("Utopia","%x ", u8buffer[idx]);
373 ULOGD("Utopia","\n");
374 }
375 #endif
376
377 #if 0//def MS_DEBUG
378 {
379 MS_U8 u8buffer[256];
380 for (idx = 0; idx<128; idx++)
381 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
382 ULOGD("Utopia","INTERN_DVBC_DSPReg_Init ReadReg 0x2000~0x207F\n");
383 for (idx = 0; idx<128; idx++)
384 {
385 ULOGD("Utopia","%x ", u8buffer[idx]);
386 if ((idx & 0xF) == 0xF) ULOGD("Utopia","\n");
387 }
388 ULOGD("Utopia","\n");
389 }
390 #endif
391
392 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_PARAM_VERSION, UTOPIA_DRIVER_VERSION) != TRUE)
393 {
394 ULOGD("DEMOD","INTERN_DVBC_DSPReg_Init NG\n"); return FALSE;
395 }
396
397 return status;
398 }
399
400 /***********************************************************************************
401 Subject: Command Packet Interface
402 Function: INTERN_DVBC_Cmd_Packet_Send
403 Parmeter:
404 Return: MS_BOOL
405 Remark:
406 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)407 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
408 {
409 MS_U8 status = true, indx;
410 MS_U8 reg_val, timeout = 0;
411 return TRUE;
412 // ==== Command Phase ===================
413 ULOGD("DEMOD","--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
414 pCmdPacket->param[0],pCmdPacket->param[1],
415 pCmdPacket->param[2],pCmdPacket->param[3],
416 pCmdPacket->param[4],pCmdPacket->param[5] );
417
418 // wait _BIT_END clear
419 do
420 {
421 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
422 if((reg_val & _BIT_END) != _BIT_END)
423 {
424 break;
425 }
426 MsOS_DelayTask(5);
427 if (timeout > 200)
428 {
429 ULOGE("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
430 return false;
431 }
432 timeout++;
433 } while (1);
434
435 // set cmd_3:0 and _BIT_START
436 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
437 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
438 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
439
440
441 //DBG_INTERN_DVBT(ULOGD("Utopia","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
442 // wait _BIT_START clear
443 do
444 {
445 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
446 if((reg_val & _BIT_START) != _BIT_START)
447 {
448 break;
449 }
450 MsOS_DelayTask(10);
451 if (timeout > 200)
452 {
453 ULOGE("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
454 return false;
455 }
456 timeout++;
457 } while (1);
458
459 // ==== Data Phase ======================
460
461 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
462
463 for (indx = 0; indx < param_cnt; indx++)
464 {
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
466 //DBG_INTERN_DVBT(ULOGD("Utopia","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
467
468 // set param[indx] and _BIT_DRQ
469 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
470 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
471 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
472
473 // wait _BIT_DRQ clear
474 do
475 {
476 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
477 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
478 {
479 break;
480 }
481 MsOS_DelayTask(5);
482 if (timeout > 200)
483 {
484 ULOGE("DEMOD","---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
485 return false;
486 }
487 timeout++;
488 } while (1);
489 }
490
491 // ==== End Phase =======================
492
493 // set _BIT_END to finish command
494 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
495 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
496 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
497 return status;
498 }
499
500
501 /***********************************************************************************
502 Subject: Command Packet Interface
503 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
504 Parmeter:
505 Return: MS_BOOL
506 Remark:
507 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)508 MS_BOOL INTERN_DVBC_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
509 {
510 return TRUE;
511 }
512
513 /***********************************************************************************
514 Subject: SoftStop
515 Function: INTERN_DVBC_SoftStop
516 Parmeter:
517 Return: MS_BOOL
518 Remark:
519 ************************************************************************************/
520
INTERN_DVBC_SoftStop(void)521 MS_BOOL INTERN_DVBC_SoftStop ( void )
522 {
523 #if 1
524 MS_U16 u8WaitCnt=0;
525
526 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
527 {
528 ULOGE("DEMOD",">> MB Busy!\n");
529 return FALSE;
530 }
531
532 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
533
534 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
535 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
536
537 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
538 {
539 #if TEST_EMBEDED_DEMOD
540 MsOS_DelayTask(1); // << Ken 20090629
541 #endif
542 if (u8WaitCnt++ >= 0xFF)
543 {
544 ULOGE("DEMOD",">> DVBT SoftStop Fail!\n");
545 return FALSE;
546 }
547 }
548
549 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
550 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
551 #endif
552 return TRUE;
553 }
554
555
556 /***********************************************************************************
557 Subject: Reset
558 Function: INTERN_DVBC_Reset
559 Parmeter:
560 Return: MS_BOOL
561 Remark:
562 ************************************************************************************/
563 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBC_Reset(void)564 MS_BOOL INTERN_DVBC_Reset ( void )
565 {
566 ULOGD("DEMOD"," @INTERN_DVBC_reset\n");
567
568
569 INTERN_DVBC_SoftStop();
570
571
572 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
573 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
574 MsOS_DelayTask(5);
575 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
576 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
577 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
578 MsOS_DelayTask(5);
579
580 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
581 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
582
583 u32ChkScanTimeStartDVBC = MsOS_GetSystemTime();
584 g_dvbc_lock = 0;
585
586 return TRUE;
587 }
588
589 /***********************************************************************************
590 Subject: Exit
591 Function: INTERN_DVBC_Exit
592 Parmeter:
593 Return: MS_BOOL
594 Remark:
595 ************************************************************************************/
INTERN_DVBC_Exit(void)596 MS_BOOL INTERN_DVBC_Exit ( void )
597 {
598
599 INTERN_DVBC_SoftStop();
600
601
602 //diable clk gen
603 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
604 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
605
606 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
607 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
608
609 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
610 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
611
612 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
613 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
614
615 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
616 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
617
618 HAL_DMD_RIU_WriteByte(0x103312, 0x05); // dvbt_t:0x0000, dvb_c: 0x0004
619 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
620
621 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
622 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
623
624 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
625 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
626
627 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
628 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
629
630 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
631 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
632
633 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
634
635 return TRUE;
636 }
637
638 /***********************************************************************************
639 Subject: Load DSP code to chip
640 Function: INTERN_DVBC_LoadDSPCode
641 Parmeter:
642 Return: MS_BOOL
643 Remark:
644 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)645 static MS_BOOL INTERN_DVBC_LoadDSPCode(void)
646 {
647 MS_U8 udata = 0x00;
648 MS_U16 i;
649 MS_U16 fail_cnt=0;
650
651 #if (DBG_DUMP_LOAD_DSP_TIME==1)
652 MS_U32 u32Time;
653 #endif
654
655
656 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
657 BININFO BinInfo;
658 MS_BOOL bResult;
659 MS_U32 u32GEAddr;
660 MS_U8 Data;
661 MS_S8 op;
662 MS_U32 srcaddr;
663 MS_U32 len;
664 MS_U32 SizeBy4K;
665 MS_U16 u16Counter=0;
666 MS_U8 *pU8Data;
667 #endif
668
669 #if 0
670 if(HAL_DMD_RIU_ReadByte(0x101E3E))
671 {
672 ULOGD("Utopia","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
673 return FALSE;
674 }
675 #endif
676
677 // MDrv_Sys_DisableWatchDog();
678
679
680 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
681 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
682 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
683 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
684 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
685 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
686
687 //// Load code thru VDMCU_IF ////
688 ULOGD("DEMOD",">Load Code.....\n");
689 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
690 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
691 {
692 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
693 }
694 #else
695 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
696 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
697 if ( bResult != PASS )
698 {
699 return FALSE;
700 }
701 //ULOGD("Utopia","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
702
703 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
704 InfoBlock_Flash_2_Checking_Start(&BinInfo);
705 #endif
706
707 #if OBA2
708 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
709 #else
710 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
711 #endif
712
713 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
714 InfoBlock_Flash_2_Checking_End(&BinInfo);
715 #endif
716
717 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
718 SizeBy4K=BinInfo.B_Len/0x1000;
719 //ULOGD("Utopia","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
720
721 #if (DBG_DUMP_LOAD_DSP_TIME==1)
722 u32Time = msAPI_Timer_GetTime0();
723 #endif
724
725 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
726
727 for (i=0;i<=SizeBy4K;i++)
728 {
729 if(i==SizeBy4K)
730 len=BinInfo.B_Len%0x1000;
731 else
732 len=0x1000;
733
734 srcaddr = u32GEAddr+(0x1000*i);
735 //ULOGD("Utopia","\t i = %08X\n", i);
736 //ULOGD("Utopia","\t len = %08X\n", len);
737 op = 1;
738 u16Counter = 0 ;
739 //ULOGD("Utopia","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
740 while(len--)
741 {
742 u16Counter ++ ;
743 //ULOGD("Utopia","file: %s, line: %d\n", __FILE__, __LINE__);
744 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
745 #if OBA2
746 pU8Data = (MS_U8 *)(srcaddr);
747 #else
748 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
749 #endif
750 Data = *pU8Data;
751
752 #if 0
753 if(u16Counter < 0x100)
754 ULOGD("Utopia","0x%bx,", Data);
755 #endif
756 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
757
758 srcaddr += op;
759 }
760 // ULOGD("Utopia","\n\n\n");
761 }
762
763 #if (DBG_DUMP_LOAD_DSP_TIME==1)
764 ULOGD("DEMOD","------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
765 #endif
766
767 #endif
768
769 //// Content verification ////
770 ULOGD("DEMOD",">Verify Code...\n");
771
772 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
773 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
774
775 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
776 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
777 {
778 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
779 if (udata != INTERN_DVBC_table[i])
780 {
781 ULOGE("DEMOD",">fail add = 0x%x\n", i);
782 ULOGE("DEMOD",">code = 0x%x\n", INTERN_DVBC_table[i]);
783 ULOGE("DEMOD",">data = 0x%x\n", udata);
784
785 if (fail_cnt > 10)
786 {
787 ULOGE("DEMOD",">DVB-C DSP Loadcode fail!");
788 return false;
789 }
790 fail_cnt++;
791 }
792 }
793 #else
794 for (i=0;i<=SizeBy4K;i++)
795 {
796 if(i==SizeBy4K)
797 len=BinInfo.B_Len%0x1000;
798 else
799 len=0x1000;
800
801 srcaddr = u32GEAddr+(0x1000*i);
802 //printf("\t i = %08LX\n", i);
803 //printf("\t len = %08LX\n", len);
804 op = 1;
805 u16Counter = 0 ;
806 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
807 while(len--)
808 {
809 u16Counter ++ ;
810 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
811 //pU8Data = (MS_U8 *)(srcaddr|0x80000000);
812 #if OBA2
813 pU8Data = (MS_U8 *)(srcaddr);
814 #else
815 pU8Data = (MS_U8 *)(srcaddr|0x80000000);
816 #endif
817 Data = *pU8Data;
818
819 #if 0
820 if(u16Counter < 0x100)
821 ULOGD("Utopia","0x%bx,", Data);
822 #endif
823 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
824 if (udata != Data)
825 {
826 ULOGE("DEMOD",">fail add = 0x%lx\n", (MS_U32)((i*0x1000)+(0x1000-len)));
827 ULOGE("DEMOD",">code = 0x%x\n", Data);
828 ULOGE("DEMOD",">data = 0x%x\n", udata);
829
830 if (fail_cnt++ > 10)
831 {
832 ULOGE("DEMOD",">DVB-C DSP Loadcode fail!");
833 return false;
834 }
835 }
836
837 srcaddr += op;
838 }
839 // printf("\n\n\n");
840 }
841 #endif
842
843 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
844 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
845 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
846 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
847
848 ULOGD("DEMOD",">DSP Loadcode done.");
849 //while(load_data_variable);
850 #if 0
851 INTERN_DVBC_Config(6875, 128, 36125, 0,1);
852 INTERN_DVBC_Active(ENABLE);
853 while(1);
854 #endif
855 HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
856
857 return TRUE;
858 }
859
860 /***********************************************************************************
861 Subject: DVB-T CLKGEN initialized function
862 Function: INTERN_DVBC_Power_On_Initialization
863 Parmeter:
864 Return: MS_BOOL
865 Remark:
866 ************************************************************************************/
INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)867 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable)
868 {
869 MS_U8 temp_val;
870 //move to drvSYS MS_U8 tmp;
871 // MS_U8 udatatemp = 0x00;
872 /************************************************************************
873 * T10 U01
874 * This bit0 is mux for DMD muc and HK,
875 * bit0: 0:HK can rw bank 0x1120, 1: DMD mcu can rw bank 0x1120;
876 ************************************************************************/
877 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK.
878 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
879 // CLK_DMDMCU clock setting
880 // [0] disable clock
881 // [1] invert clock
882 // [4:2]
883 // 000:170 MHz(MPLL_DIV_BUf)
884 // 001:160MHz
885 // 010:144MHz
886 // 011:123MHz
887 // 100:108MHz
888 // 101:mem_clcok
889 // 110:mem_clock div 2
890 // 111:select XTAL
891 //HAL_DMD_RIU_WriteByte(0x10331f,0x00);
892 HAL_DMD_RIU_WriteByte(0x10331e,0x10);
893
894 // set parallet ts clock
895 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
896 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
897 // wriu 0x103301 0x06
898 // wriu 0x103300 0x19
899
900
901 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0x060b,7.2M
902 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
903 temp_val|=0x07;
904 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
905
906 HAL_DMD_RIU_WriteByte(0x103300,0x13);
907
908 // enable atsc, DVBTC ts clock
909 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
910 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
911 // wriu 0x103309 0x00
912 // wriu 0x103308 0x00
913
914 HAL_DMD_RIU_WriteByte(0x103309,0x00);
915 HAL_DMD_RIU_WriteByte(0x103308,0x00); //Messi 0x00// Nike
916
917 // enable dvbc adc clock
918 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
919 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
920 // wriu 0x103315 0x00
921 // wriu 0x103314 0x00
922
923 HAL_DMD_RIU_WriteByte(0x103315,0x00);
924 HAL_DMD_RIU_WriteByte(0x103314,0x00);
925
926
927 HAL_DMD_RIU_WriteByte(0x103302,0x01);
928 HAL_DMD_RIU_WriteByte(0x103302,0x00);
929
930 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
931 HAL_DMD_RIU_WriteByte(0x111f28,0x04);
932
933 HAL_DMD_RIU_WriteByte(0x111f03,0x04);
934 HAL_DMD_RIU_WriteByte(0x111f02,0x04);
935
936 HAL_DMD_RIU_WriteByte(0x111f07,0x04);
937 HAL_DMD_RIU_WriteByte(0x111f06,0x00);
938 // enable vif DAC clock
939 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
940 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0d, 2'b11, 16'h0000);
941 // wriu 0x10331b 0x00
942 // wriu 0x10331a 0x00
943
944 //HAL_DMD_RIU_WriteByte(0x10331b,0x00);
945 //HAL_DMD_RIU_WriteByte(0x10331a,0x00);
946
947 // Select MPLLDIV2
948 // [0] : reg_atsc_adc_sel_mplldiv2
949 // [1] : reg_atsc_eq_sel_mplldiv2
950 // [2] : reg_eq25_sel_mplldiv3
951 // [3] : reg_p4_cfo_sel_eq25
952 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h14, 2'b01, 16'h0003);
953 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h14, 2'b01, 16'h0003);
954 // wriu 0x112028 0x03
955 // HAL_DMD_RIU_WriteByte(0x111f28,0x04); // Eiffel // Nike MOVE to DMDMCU
956
957
958 // Select MPLLDIV2
959 // [0] : reg_fed_srd_on
960 // [1] : reg_dvbt_new_tdsfo_on
961 // [2] : reg_dvbc_p4_cfo_on
962 // `RIU_W((`RIUBASE_DMD_TOP>>1)+7'h15, 2'b01, 16'h0001);
963 // wriu 0x111f2a 0x01
964 // HAL_DMD_RIU_WriteByte(0x111f2a,0x01); // Eiffel has, Nike mark
965
966
967 // *** Set register at CLKGEN_DMD
968 // enable atsc clock
969 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
970 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h01, 2'b11, 16'h0404);
971 // wriu 0x111f03 0x04
972 // wriu 0x111f02 0x04
973
974 // HAL_DMD_RIU_WriteByte(0x111f03,0x00);
975 // HAL_DMD_RIU_WriteByte(0x111f02,0x00);
976 // HAL_DMD_RIU_WriteByte(0x111f03,0x04); // Eiffle has, Nike mark
977 // HAL_DMD_RIU_WriteByte(0x111f02,0x04); // Eiffle has, Nike mark
978
979 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
980 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h02, 2'b11, 16'h0000);
981 // wriu 0x111f05 0x00
982 // wriu 0x111f04 0x00
983
984 // HAL_DMD_RIU_WriteByte(0x111f05,0x00); // Eiffle has, Nike mark
985 // HAL_DMD_RIU_WriteByte(0x111f04,0x00); // Eiffle has, Nike mark
986 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
987 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h03, 2'b11, 16'h0404);
988 // wriu 0x111f07 0x04
989 // wriu 0x111f06 0x04
990
991 // HAL_DMD_RIU_WriteByte(0x111f07,0x00);
992 // HAL_DMD_RIU_WriteByte(0x111f06,0x00);
993
994 // HAL_DMD_RIU_WriteByte(0x111f07,0x04); // Eiffle has, Nike mark
995 // HAL_DMD_RIU_WriteByte(0x111f06,0x00); // Eiffle has, Nike mark
996
997 // enable clk_atsc_adcd_sync
998 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
999 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
1000 // wriu 0x111f0b 0x00
1001 // wriu 0x111f0a 0x00
1002
1003 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1005
1006 // enable dvbt inner clock
1007 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
1008 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
1009 // wriu 0x111f0d 0x00
1010 // wriu 0x111f0c 0x00
1011
1012 HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1013 HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1014
1015 // enable dvbt inner clock
1016 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
1017 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h07, 2'b11, 16'h0000);
1018 // wriu 0x111f0f 0x00
1019 // wriu 0x111f0e 0x00
1020
1021 HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1022 HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1023
1024 // enable dvbt inner clock
1025 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
1026 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
1027 // wriu 0x111f11 0x00
1028 // wriu 0x111f10 0x00
1029
1030 HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1031 HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1032
1033 // enable dvbc outer clock
1034 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
1035 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
1036 // wriu 0x111f13 0x00
1037 // wriu 0x111f12 0x00
1038
1039 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1040 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1041
1042 // enable dvbc inner-c clock
1043 // [11:8]: reg_ckg_dvbtc_innc
1044 // [0] : disable clock
1045 // [1] : invert clock
1046 // [3:2]: Select clock source
1047 // 00: clk_dmdadc
1048 // 01: reserved
1049 // 10: reserved
1050 // 11: DFT_CLK
1051 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1052
1053 // enable dvbc inner-c clock
1054 // [11:8]: reg_ckg_dvbtc_innc
1055 // [0] : disable clock
1056 // [1] : invert clock
1057 // [3:2]: Select clock source
1058 // 00: clk_dmdadc
1059 // 01: reserved
1060 // 10: reserved
1061 // 11: DFT_CLK
1062 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1063 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0a, 2'b11, 16'h0000);
1064 // wriu 0x111f15 0x00
1065 // wriu 0x111f14 0x00
1066 HAL_DMD_RIU_WriteByte(0x111f15,0x00); // nike has
1067 HAL_DMD_RIU_WriteByte(0x111f14,0x00); // nike has
1068
1069 // enable dvbc eq
1070 // [3:0] : reg_ckg_dvbtc_eq8x
1071 // [0] : disable clock
1072 // [1] : invert clock
1073 // [3:2]: Select clock source
1074 // 00: clk_dmplldiv3_div2
1075 // 01: reserved
1076 // 10: reserved
1077 // 11: DFT_CLK
1078 // [12:8]: reg_ckg_dvbtc_eq
1079 // [0] : disable clock
1080 // [1] : invert clock
1081 // [3:2]: Select clock source
1082 // 00: clk_dmplldiv3_div16
1083 // 01: reserved
1084 // 10: reserved
1085 // 11: DFT_CLK
1086 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1087 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0b, 2'b11, 16'h0000);
1088 // wriu 0x111f17 0x00
1089 // wriu 0x111f16 0x00
1090 HAL_DMD_RIU_WriteByte(0x111f17,0x00); // nike has
1091 HAL_DMD_RIU_WriteByte(0x111f16,0x00); // nike has
1092
1093 HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1094 HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1095
1096
1097 // [9:8] : reg_ckg_adc1x_eq1x
1098 // [13:12] : reg_ckg_adc0p5x_eq0p5x
1099 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h24, 2'b10, 16'h0000);
1100 // wriu 0x111f49 0x00
1101 HAL_DMD_RIU_WriteByte(0x111f49,0x00); // Eiffel for power4CFO open clock
1102 HAL_DMD_RIU_WriteByte(0x111f48,0x00); // Eiffel for power4CFO open clock
1103 // enable sram clock
1104 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1105 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1106 // wriu 0x111f19 0x00
1107 // wriu 0x111f18 0x00
1108
1109 HAL_DMD_RIU_WriteByte(0x111f4b,0x00);
1110 HAL_DMD_RIU_WriteByte(0x111f4a,0x00);
1111
1112 HAL_DMD_RIU_WriteByte(0x111f4c,0x11);
1113 // enable vif clock
1114 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1115 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0e, 2'b11, 16'h0000);
1116 // wriu 0x111f1d 0x00
1117 // wriu 0x111f1c 0x00
1118
1119 //HAL_DMD_RIU_WriteByte(0x111f1d,0x00);
1120 //HAL_DMD_RIU_WriteByte(0x111f1c,0x00);
1121
1122 // enable DEMODE-DMA clock
1123 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1124 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h0000);
1125 // wriu 0x111f21 0x00
1126 // wriu 0x111f20 0x00
1127
1128 //HAL_DMD_RIU_WriteByte(0x111f21,0x00);
1129 //HAL_DMD_RIU_WriteByte(0x111f20,0x00);
1130 // select clock
1131 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1132 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444);
1133 // wriu 0x111f23 0x04
1134 // wriu 0x111f22 0x44
1135 // HAL_DMD_RIU_WriteByte(0x111f23,0x00);
1136 // HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1137
1138 // select clock
1139 // [3:0] : reg_ckg_frontend
1140 // [0] : disable clock
1141 // [1] : invert clock
1142 // [3:2]: Select clock source
1143 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
1144 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1145 // 10: reserved
1146 // 11: select DFT_CLK
1147 // [7:4] : reg_ckg_tr
1148 // [0] : disable clock
1149 // [1] : invert clock
1150 // [3:2]: Select clock source
1151 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
1152 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1153 // 10: reserved
1154 // 11: select DFT_CLK
1155 // [11:8]: reg_ckg_acifir
1156 // [0] : disable clock
1157 // [1] : invert clock
1158 // [3:2]: Select clock source
1159 // 00: select clk_dmplldiv2_div7_div2(24.85 MHz, ATSC)
1160 // 01: select clk_dmdadc (48 MHz, DVBT/C)
1161 // 10: clk_dmplldiv10_div2 (43.2 MHz, VIF)
1162 // 11: select DFT_CLK
1163 // [15:12]: reg_ckg_frontend_d2
1164 // [0] : disable clock
1165 // [1] : invert clock
1166 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0444); // ???
1167 HAL_DMD_RIU_WriteByte(0x111f23,0x04);
1168 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
1169
1170
1171 HAL_DMD_RIU_WriteByte(0x111f71,0x14);
1172 HAL_DMD_RIU_WriteByte(0x111f70,0x41);
1173
1174 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1175 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1176
1177 HAL_DMD_RIU_WriteByte(0x111f4f,0x00);
1178
1179 HAL_DMD_RIU_WriteByte(0x111f81,0x00);
1180 HAL_DMD_RIU_WriteByte(0x111f80,0x00);
1181
1182 HAL_DMD_RIU_WriteByte(0x111f83,0x00);
1183 HAL_DMD_RIU_WriteByte(0x111f82,0x00);
1184
1185 HAL_DMD_RIU_WriteByte(0x111f85,0x00);
1186 HAL_DMD_RIU_WriteByte(0x111f84,0x00);
1187
1188 HAL_DMD_RIU_WriteByte(0x111f87,0x00);
1189 HAL_DMD_RIU_WriteByte(0x111f86,0x00);
1190
1191 HAL_DMD_RIU_WriteByte(0x111f8d,0x11);
1192 HAL_DMD_RIU_WriteByte(0x111f8c,0x01);
1193
1194 HAL_DMD_RIU_WriteByte(0x111f8f,0x00);
1195 HAL_DMD_RIU_WriteByte(0x111f8e,0x41);
1196
1197
1198 // Turn on New symbol rate detection
1199 // [3] : reg_dvbt_new_tdsfo_on
1200 // [2] : reg_fed_srd_on
1201 // `M3_RIU_W( (`RIUBASE_DMD_TOP_M3>>1)+7'h00, 2'b01, 16'h0004);
1202 // `M3_RIU_W( (`RIUBASE_DMD_TOP_M3>>1)+7'h00, 2'b01, 16'h0004);
1203 // HAL_DMD_RIU_WriteByte(0x112000, 0x04); // Eiffel
1204
1205
1206 // ----------------------------------------------
1207 // start demod CLKGEN setting
1208 // ----------------------------------------------
1209 // select DMD MCU
1210 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1211 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1212 // [0] 0:TOP HK; 1:DMDMCU
1213 // [1] 0:DMDANAQ HK; 1:DMDMCU
1214 // begin BY temp patch
1215 //HAL_DMD_RIU_WriteByte(0x1120A0,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1216 //HAL_DMD_RIU_WriteByte(0x1120A1,0x00); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
1217 // end
1218 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1219
1220 // ----------------------------------------------
1221 // Turn TSP
1222 // ----------------------------------------------
1223 // set the ts0_clk from demod
1224 // [3:0]: CLK_TS0 clock setting
1225 // [0] : disable
1226 // [1] : invert clock
1227 // [3:2]: Select clock source
1228 // 00: select TS0_CLK
1229 // 01: select TS1_CLK
1230 // 10: reserved
1231 // 11: clk_demod_ts_p
1232 // `RIU_W((`RIUBASE_CLKGEN0>>1)+7'h28 , 2'b11, 16'h000c);
1233
1234 // PWDN_REF_eco => reg_reserve0[10] = 0
1235 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1236 // `RIU_W( (`RIUBASE_PM_SLEEP>>1)+7'h09, 2'b10, 16'h0100); // 16'bxxxx_x0xx_xxxx_xxxx=> need change channel!!!
1237 // swch 3
1238 // wriu 0x000e13 0x01
1239
1240 //HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1241 }
1242
1243 /***********************************************************************************
1244 Subject: Power on initialized function
1245 Function: INTERN_DVBC_Power_On_Initialization
1246 Parmeter:
1247 Return: MS_BOOL
1248 Remark:
1249 ************************************************************************************/
1250
INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBC_DSPRegInitExt,MS_U8 u8DMD_DVBC_DSPRegInitSize)1251 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize)
1252 {
1253 MS_U8 status = true;
1254 ULOGD("DEMOD","INTERN_DVBC_Power_On_Initialization\n");
1255
1256 #if defined(PWS_ENABLE)
1257 Mapi_PWS_Stop_VDMCU();
1258 #endif
1259
1260 INTERN_DVBC_InitClkgen(bRFAGCTristateEnable);
1261 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1262 //// Firmware download //////////
1263 ULOGD("DEMOD","INTERN_DVBC Load DSP...\n");
1264 //MsOS_DelayTask(100);
1265
1266 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x04) // DVBT = BIT1 -> 0x02
1267 {
1268 if (INTERN_DVBC_LoadDSPCode() == FALSE)
1269 {
1270 ULOGE("DEMOD","DVB-C Load DSP Code Fail\n");
1271 return FALSE;
1272 }
1273 else
1274 {
1275 ULOGD("DEMOD","DVB-C Load DSP Code OK\n");
1276 }
1277 }
1278
1279 status &= INTERN_DVBC_Reset();
1280
1281 status &= INTERN_DVBC_DSPReg_Init(u8DMD_DVBC_DSPRegInitExt, u8DMD_DVBC_DSPRegInitSize);
1282
1283 return status;
1284 }
1285
1286 /************************************************************************************************
1287 Subject: Driving control
1288 Function: INTERN_DVBC_Driving_Control
1289 Parmeter: bInversionEnable : TRUE For High
1290 Return: void
1291 Remark:
1292 *************************************************************************************************/
INTERN_DVBC_Driving_Control(MS_BOOL bEnable)1293 void INTERN_DVBC_Driving_Control(MS_BOOL bEnable)
1294 {
1295 MS_U8 u8Temp;
1296
1297 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1298
1299 if (bEnable)
1300 {
1301 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1302 }
1303 else
1304 {
1305 u8Temp = u8Temp & (~0x01);
1306 }
1307
1308 ULOGD("DEMOD","---> INTERN_DVBC_Driving_Control(Bit0) = 0x%x \n",u8Temp);
1309 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1310 }
1311 /************************************************************************************************
1312 Subject: Clk Inversion control
1313 Function: INTERN_DVBC_Clk_Inversion_Control
1314 Parmeter: bInversionEnable : TRUE For Inversion Action
1315 Return: void
1316 Remark:
1317 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)1318 void INTERN_DVBC_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1319 {
1320 MS_U8 u8Temp;
1321
1322 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1323
1324 if (bInversionEnable)
1325 {
1326 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1327 }
1328 else
1329 {
1330 u8Temp = u8Temp & (~0x02);
1331 }
1332
1333 ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp);
1334 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1335 }
1336 /************************************************************************************************
1337 Subject: Transport stream serial/parallel control
1338 Function: INTERN_DVBC_Serial_Control
1339 Parmeter: bEnable : TRUE For serial
1340 Return: MS_BOOL :
1341 Remark:
1342 *************************************************************************************************/
INTERN_DVBC_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1343 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1344 {
1345 MS_U8 status = true;
1346 MS_U8 temp_val;
1347 ULOGD("DEMOD"," @INTERN_DVBC_ts... u8TSClk=%d\n", u8TSClk);
1348
1349 if (u8TSClk == 0xFF) u8TSClk=0x13;
1350 if (bEnable) //Serial mode for TS pad
1351 {
1352 // serial
1353 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1354 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1355
1356 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1357 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1358 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1359 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1360 temp_val|=0x04;
1361 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1362 #else
1363 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1364 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1365 temp_val|=0x07;
1366 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1367 #endif
1368 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1369 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1370
1371 //// INTERN_DVBC TS Control: Serial //////////
1372
1373 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_SERIAL);
1374
1375 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1376 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1377 #else
1378 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1379 #endif
1380 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1381
1382 gsCmdPacketDVBC.param[0] = TS_SERIAL;
1383 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1384 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1385 #else
1386 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1387 #endif
1388 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1389 }
1390 else
1391 {
1392 //parallel
1393 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1394 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1395
1396 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1397 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1398 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1399 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1400 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1401 temp_val|=0x05;
1402 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1403 #else
1404 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1405 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1406 temp_val|=0x07;
1407 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1408 #endif
1409
1410 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1411 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1412
1413 //// INTERN_DVBC TS Control: Parallel //////////
1414
1415 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, TS_PARALLEL);
1416
1417 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1418 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 0);
1419 #else
1420 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_CLK_INV, 1);
1421 #endif
1422 //// INTERN_DVBC TS Control: Parallel //////////
1423 gsCmdPacketDVBC.cmd_code = CMD_TS_CTRL;
1424
1425 gsCmdPacketDVBC.param[0] = TS_PARALLEL;
1426 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1427 gsCmdPacketDVBC.param[1] = 0;//TS_CLK_NO_INV;
1428 #else
1429 gsCmdPacketDVBC.param[1] = 1;//TS_CLK_INVERSE;
1430 #endif
1431 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 2);
1432 }
1433
1434 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1435 ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",0 );
1436 #else
1437 ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",1 );
1438 #endif
1439
1440 INTERN_DVBC_Driving_Control(INTERN_DVBC_DTV_DRIVING_LEVEL);
1441 return status;
1442 }
1443
1444 /************************************************************************************************
1445 Subject: TS1 output control
1446 Function: INTERN_DVBC_PAD_TS1_Enable
1447 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1448 Return: void
1449 Remark:
1450 *************************************************************************************************/
INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)1451 void INTERN_DVBC_PAD_TS1_Enable(MS_BOOL flag)
1452 {
1453 ULOGD("DEMOD"," @INTERN_DVBC_TS1_Enable... \n");
1454
1455 if(flag) // PAD_TS1 Enable TS CLK PAD
1456 {
1457 //printf("=== TS1_Enable ===\n");
1458 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1459 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1460 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1461 }
1462 else // PAD_TS1 Disable TS CLK PAD
1463 {
1464 //printf("=== TS1_Disable ===\n");
1465 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1466 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1467 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1468 }
1469 }
1470
1471 /************************************************************************************************
1472 Subject: channel change config
1473 Function: INTERN_DVBC_Config
1474 Parmeter: BW: bandwidth
1475 Return: MS_BOOL :
1476 Remark:
1477 *************************************************************************************************/
INTERN_DVBC_Config(MS_U16 u16SymbolRate,DMD_DVBC_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)1478 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
1479 {
1480
1481 MS_U8 status = true;
1482 MS_U8 reg_symrate_l, reg_symrate_h;
1483 //MS_U16 u16Fc = 0;
1484 MS_U8 temp_val;
1485 // force
1486 // u16SymbolRate = 0;
1487 // eQamMode = DMD_DVBC_QAMAUTO;
1488
1489 //pu16_symbol_rate_list = pu16_symbol_rate_list;
1490 //u8_symbol_rate_list_num = u8_symbol_rate_list_num;
1491
1492 //ULOGD("DEMOD"," @INTERN_DVBC_config, SR=%d, QAM=%d, u32IFFreq=%ld, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n",u16SymbolRate,eQamMode,u32IFFreq,bSpecInv,bSerialTS, u8TSClk);
1493 //ULOGD("DEMOD","INTERN_DVBC_Config, t = %ld\n",MsOS_GetSystemTime());
1494
1495 if (u8TSClk == 0xFF) u8TSClk=0x13;
1496
1497 /*
1498 switch(u32IFFreq)
1499 {
1500 case 36125:
1501 case 36167:
1502 case 36000:
1503 case 6000:
1504 case 4560:
1505 //u16Fc = DVBC_FS - u32IFFreq;
1506 DBG_INTERN_DVBC(ULOGD("Utopia","Fc freq = %ld\n", DVBC_FS - u32IFFreq));
1507 break;
1508 case 44000:
1509 default:
1510 ULOGE("Utopia","IF frequency not supported\n");
1511 status = false;
1512 break;
1513 }
1514 */
1515
1516 reg_symrate_l = (MS_U8) (u16SymbolRate & 0xff);
1517 reg_symrate_h = (MS_U8) (u16SymbolRate >> 8);
1518
1519 status &= INTERN_DVBC_Reset();
1520
1521 if (eQamMode == DMD_DVBC_QAMAUTO)
1522 {
1523 ULOGD("DEMOD","DMD_DVBC_QAMAUTO\n");
1524 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x01);
1525 // give default value.
1526 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, QAM);
1527 }
1528 else
1529 {
1530 ULOGD("DEMOD","DMD_DVBC_QAM %d\n", eQamMode);
1531 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_QAM, 0x00);
1532 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_QAM, eQamMode);
1533 }
1534 // auto symbol rate enable/disable
1535 if (u16SymbolRate == 0)
1536 {
1537 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x01);
1538 }
1539 else
1540 {
1541 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1542 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1543 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1544 MS_U8 indx = 0;
1545 MS_U8 max_len = (E_DMD_DVBC_CFG_BW11_H - E_DMD_DVBC_CFG_BW0_L + 1)/2;
1546
1547 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_AUTO_SCAN_SYM_RATE, 0x00);
1548
1549 if (max_len < u8_symbol_rate_list_num)
1550 {
1551 ULOGE("DEMOD","[a1_dvbc]Error!!! %s, %s, %d, max_len < u8_symbol_rate_list_num\n",__FILE__,__FUNCTION__,__LINE__);
1552
1553 // Force dvbc unlock.
1554 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, 0x01);
1555 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, 0x00);
1556 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW1_L, 0x00);
1557 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW1_H, 0x00);
1558 }
1559 else if (u8_symbol_rate_list_num == 0)
1560 {
1561 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L, reg_symrate_l);
1562 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_H, reg_symrate_h);
1563 }
1564 else
1565 {
1566 for (indx = 0; indx < max_len ; indx++)
1567 {
1568 if (indx < u8_symbol_rate_list_num)
1569 {
1570 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2, (MS_U8)pu16_symbol_rate_list[indx]);
1571 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2 + 1, (MS_U8)(pu16_symbol_rate_list[indx]>>8));
1572 }
1573 else
1574 {
1575 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2, 0x00);
1576 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_BW0_L + indx*2 + 1, 0x00);
1577 }
1578 }
1579 }
1580 }
1581 // TS mode
1582 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1583
1584 // IQ Swap
1585 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_IQ_SWAP, bSpecInv? 0x01:0x00);
1586
1587 // Fc
1588 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_L, (abs(DVBC_FS-u32IFFreq))&0xff);
1589 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FC_H, (abs((DVBC_FS-u32IFFreq))>>8)&0xff);
1590 // Lif
1591 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_OP_LIF_EN, (u32IFFreq < 10000) ? 1 : 0);
1592 // Fif
1593 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_L, (u32IFFreq)&0xff);
1594 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBC_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1595
1596 //// INTERN_DVBC system init: DVB-C //////////
1597 // gsCmdPacketDVBC.cmd_code = CMD_SYSTEM_INIT;
1598
1599 // gsCmdPacketDVBC.param[0] = E_SYS_DVBC;
1600 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1601
1602 if (bSerialTS)
1603 {
1604 // serial
1605 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1606 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1607
1608 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1609 #if(INTERN_DVBC_TS_SERIAL_INVERSION == 0)
1610 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1611 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1612 temp_val|=0x04;
1613 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1614 #else
1615 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1616 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1617 temp_val|=0x07;
1618 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1619 #endif
1620 }
1621 else
1622 {
1623 //parallel
1624 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1625 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1626
1627 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1628 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1629 #if(INTERN_DVBC_TS_PARALLEL_INVERSION == 0)
1630 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1631 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1632 temp_val|=0x05;
1633 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1634 #else
1635 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1636 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1637 temp_val|=0x07;
1638 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1639 #endif
1640 }
1641 #if (INTERN_DVBC_INTERNAL_DEBUG == 1)
1642 INTERN_DVBC_Show_Demod_Version();
1643 #endif
1644
1645 return status;
1646 }
1647 /************************************************************************************************
1648 Subject: enable hw to lock channel
1649 Function: INTERN_DVBC_Active
1650 Parmeter: bEnable
1651 Return: MS_BOOL
1652 Remark:
1653 *************************************************************************************************/
INTERN_DVBC_Active(MS_BOOL bEnable)1654 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable)
1655 {
1656 MS_U8 status = true;
1657 MS_U8 reg_frz = 0, reg_frza = 0;
1658
1659 ULOGD("DEMOD"," @INTERN_DVBC_active\n");
1660
1661 //// INTERN_DVBC Finite State Machine on/off //////////
1662 #if 0
1663 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
1664
1665 gsCmdPacketDVBC.param[0] = (MS_U8)bEnable;
1666 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacketDVBC, 1);
1667 #else
1668 HAL_DMD_RIU_WriteByte(0x112600 + (0x0e)*2, 0x01); // FSM_EN
1669 #endif
1670
1671 #if (1)//vesion check here
1672 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_PARAM_VERSION, ®_frz);
1673 ULOGD("DEMOD","##########DVBC------>(Driver) = 0x%x #########\n",reg_frz);
1674 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_OP_RFAGC_EN, ®_frza);
1675 ULOGD("DEMOD","##########DVBC------>(FW) = 0x%x #########\n",reg_frza);
1676 if (reg_frz < reg_frza)
1677 {
1678 while(1)
1679 ULOGD("DEMOD","##########--------->Abnormal case, please update demod utopia driver version!!! #########\n");
1680 }
1681 else{
1682 ULOGD("DEMOD","##########--------->Normal case! #########\n");
1683 }
1684 #endif
1685
1686 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1687 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1688 return status;
1689 }
1690
1691
INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType,float fCurrRFPowerDbm,float fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)1692 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
1693 {
1694 MS_U16 u16Address = 0;
1695 MS_U8 cData = 0;
1696 MS_U8 cBitMask = 0;
1697
1698 if (fCurrRFPowerDbm < 100.0f)
1699 {
1700 if (eType == DMD_DVBC_GETLOCK_NO_CHANNEL)
1701 {
1702 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1703 if (cData > 5)
1704 {
1705 bDMD_DVBC_NoChannelDetectedWithRFPower = FALSE;
1706 u32DMD_DVBC_NoChannelTimeAccWithRFPower = 0;
1707 }
1708 else
1709 {
1710 if ((fCurrRFPowerDbm<fNoChannelRFPowerDbm) && (u32DMD_DVBC_NoChannelTimeAccWithRFPower<10000))
1711 {
1712 u32DMD_DVBC_NoChannelTimeAccWithRFPower+=u32TimeInterval;
1713 }
1714 if (u32DMD_DVBC_NoChannelTimeAccWithRFPower>1500)
1715 {
1716 bDMD_DVBC_NoChannelDetectedWithRFPower=1;
1717 #ifdef MS_DEBUG
1718 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL Detected Detected Detected!!\n");
1719 #endif
1720 return TRUE;
1721 }
1722 }
1723 #ifdef MS_DEBUG
1724 ULOGD("DEMOD","INTERN_DVBC_GetLock:DMD_DVBC_GETLOCK_NO_CHANNEL FSM:%d InputPower:%f Threshold:%f Interval:%ld TimeAcc:%ld NoChannelDetection:%d\n",cData, fCurrRFPowerDbm, fNoChannelRFPowerDbm, u32TimeInterval, u32DMD_DVBC_NoChannelTimeAccWithRFPower, bDMD_DVBC_NoChannelDetectedWithRFPower);
1725 #endif
1726 }
1727 }
1728
1729 {
1730 switch( eType )
1731 {
1732 case DMD_DVBC_GETLOCK_FEC_LOCK:
1733 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &cData);
1734 #if (INTERN_DVBC_INTERNAL_DEBUG)
1735 INTERN_DVBC_info();
1736 #endif
1737 ULOGD("DEMOD"," @INTERN_DVBC_GetLock FSM 0x%x\n",cData);
1738 if (cData == 0x0C)
1739 {
1740 if(g_dvbc_lock == 0)
1741 {
1742 g_dvbc_lock = 1;
1743 ULOGD("DEMOD","[T12][DVBC]lock++++\n");
1744
1745 }
1746 return TRUE;
1747 }
1748 else
1749 {
1750 if(g_dvbc_lock == 1)
1751 {
1752 g_dvbc_lock = 0;
1753 ULOGD("DEMOD","[T12][DVBC]unlock----\n");
1754 }
1755 return FALSE;
1756 }
1757 break;
1758
1759 case DMD_DVBC_GETLOCK_PSYNC_LOCK:
1760 u16Address = FEC_REG_BASE + 0x2C; //FEC: P-sync Lock,
1761 cBitMask = BIT(1);
1762 break;
1763
1764 case DMD_DVBC_GETLOCK_DCR_LOCK:
1765 u16Address = TDP_REG_BASE + 0x45; //DCR Lock,
1766 cBitMask = BIT(0);
1767 break;
1768
1769 case DMD_DVBC_GETLOCK_AGC_LOCK:
1770 u16Address = TDP_REG_BASE + 0x2F; //AGC Lock,
1771 cBitMask = BIT(0);
1772 break;
1773
1774 case DMD_DVBC_GETLOCK_NO_CHANNEL:
1775 u16Address = TOP_REG_BASE + 0xC3; //no channel,
1776 cBitMask = BIT(2)|BIT(3)|BIT(4);
1777 #ifdef MS_DEBUG
1778 {
1779 MS_U8 reg_frz=0, FSM=0;
1780 MS_U16 u16Timer=0;
1781 MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0xE0, &FSM);
1782 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
1783 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
1784 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
1785 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData);
1786 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
1787 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DF, ®_frz);
1788 u16Timer=(u16Timer<<8)+reg_frz;
1789 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20DE, ®_frz);
1790 u16Timer=(u16Timer<<8)+reg_frz;
1791 ULOGD("DEMOD","DMD_DVBC_GETLOCK_NO_CHANNEL %d %d %x\n",FSM,u16Timer,cData);
1792 }
1793 #endif
1794 break;
1795
1796 case DMD_DVBC_GETLOCK_ATV_DETECT:
1797 u16Address = TOP_REG_BASE + 0xC4; //ATV detection,
1798 cBitMask = BIT(1); // check atv
1799 break;
1800
1801 case DMD_DVBC_GETLOCK_TR_LOCK:
1802 #if 0 // 20111108 temporarily solution
1803 u16Address = INNC_REG_BASE + 0x50; //TR lock indicator,
1804 cBitMask = BIT(0);
1805 break;
1806 #endif
1807 case DMD_DVBC_GETLOCK_TR_EVER_LOCK:
1808 u16Address = TOP_REG_BASE + 0xC4; //TR lock indicator,
1809 cBitMask = BIT(4);
1810 break;
1811
1812 default:
1813 return FALSE;
1814 }
1815
1816 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1817 return FALSE;
1818
1819 if ((cData & cBitMask) != 0)
1820 {
1821 return TRUE;
1822 }
1823
1824 return FALSE;
1825 }
1826
1827 return FALSE;
1828 }
1829
1830
1831 /****************************************************************************
1832 Subject: To get the Post viterbi BER
1833 Function: INTERN_DVBC_GetPostViterbiBer
1834 Parmeter: Quility
1835 Return: E_RESULT_SUCCESS
1836 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1837 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1838 We will not read the Period, and have the "/256/8"
1839 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1840 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber)
1841 {
1842 MS_BOOL status = true;
1843 MS_U8 reg = 0, reg_frz = 0;
1844 MS_U16 BitErrPeriod;
1845 MS_U32 BitErr;
1846 MS_U16 PktErr;
1847
1848 /////////// Post-Viterbi BER /////////////
1849
1850 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1852 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1853
1854 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1855 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1856 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1857 BitErrPeriod = reg;
1858
1859 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1860 BitErrPeriod = (BitErrPeriod << 8)|reg;
1861
1862 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1863 // 0x6b [15:8] reg_bit_err_num_15_8
1864 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1865 // 0x6d [15:8] reg_bit_err_num_31_24
1866 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1867 BitErr = reg;
1868
1869 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1870 BitErr = (BitErr << 8)|reg;
1871
1872 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1873 BitErr = (BitErr << 8)|reg;
1874
1875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1876 BitErr = (BitErr << 8)|reg;
1877
1878 INTERN_DVBC_GetPacketErr(&PktErr);
1879
1880 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1881 reg_frz=reg_frz&(~0x03);
1882 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1883
1884 if (BitErrPeriod == 0 ) //protect 0
1885 BitErrPeriod = 1;
1886
1887 if (BitErr <=0 )
1888 *ber = 0.5f / ((float)BitErrPeriod*128*188*8);
1889 else
1890 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1891
1892 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1893
1894 return status;
1895 }
1896
1897
1898 /****************************************************************************
1899 Subject: To get the Packet error
1900 Function: INTERN_DVBC_GetPacketErr
1901 Parmeter: pktErr
1902 Return: E_RESULT_SUCCESS
1903 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1904 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1905 We will not read the Period, and have the "/256/8"
1906 *****************************************************************************/
INTERN_DVBC_GetPacketErr(MS_U16 * pktErr)1907 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr)
1908 {
1909 MS_BOOL status = true;
1910 MS_U8 reg = 0, reg_frz = 0;
1911 MS_U16 PktErr;
1912
1913 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1914 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1915 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1916
1917 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1918 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1919 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1920 PktErr = reg;
1921
1922 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1923 PktErr = (PktErr << 8)|reg;
1924
1925 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1926 reg_frz=reg_frz&(~0x03);
1927 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1928
1929 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1930
1931 *pktErr = PktErr;
1932
1933 return status;
1934 }
1935
1936 /****************************************************************************
1937 Subject: Read the signal to noise ratio (SNR)
1938 Function: INTERN_DVBC_GetSNR
1939 Parmeter: None
1940 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1941 Remark:
1942 *****************************************************************************/
INTERN_DVBC_GetSNR(float * f_snr)1943 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr)
1944 {
1945 MS_BOOL status = true;
1946 MS_U8 u8Data = 0;
1947 // MS_U8 freeze = 0;
1948 MS_U16 noisepower = 0;
1949
1950 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0) )
1951 {
1952 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1953 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x20);
1954 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80);
1955 // read vk
1956 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x45, &u8Data);
1957 noisepower = u8Data;
1958 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x44, &u8Data);
1959 noisepower = (noisepower<<8)|u8Data;
1960
1961 // bank 2c 0x3d [0] reg_bit_err_num_freeze
1962 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3a, 0x00);
1963 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00);
1964
1965 if(noisepower == 0x0000)
1966 noisepower = 0x0001;
1967
1968 #ifdef MSOS_TYPE_LINUX
1969 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
1970 #else
1971 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
1972 #endif
1973
1974 }
1975 else
1976 {
1977 *f_snr = 0.0f;
1978 }
1979 return status;
1980
1981
1982 }
1983
INTERN_DVBC_GetSignalStrength(MS_U16 * strength,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1984 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1985 {
1986 MS_BOOL status = true;
1987 float ch_power_db=0.0f, ch_power_db_rel=0.0f;
1988 DMD_DVBC_MODULATION_TYPE Qam_mode;
1989
1990 //ULOGD("DEMOD","INTERN_DVBC_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBC_InitData->pTuner_RfagcSsi));
1991
1992 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
1993 //if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
1994 /* Actually, it's more reasonable, that signal level depended on cable input power level
1995 * thougth the signal isn't dvb-t signal.
1996 */
1997 // use pointer of IFAGC table to identify
1998 // case 1: RFAGC from SAR, IFAGC controlled by demod
1999 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2000 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2001 sDMD_DVBC_InitData->pTuner_RfagcSsi, sDMD_DVBC_InitData->u16Tuner_RfagcSsi_Size,
2002 sDMD_DVBC_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2003 sDMD_DVBC_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2004 sDMD_DVBC_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_HiRef_Size,
2005 sDMD_DVBC_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBC_InitData->u16Tuner_IfagcErr_LoRef_Size);
2006
2007 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2008
2009 if( (MS_U8)Qam_mode <= (MS_U8)DMD_DVBC_QAM256)
2010 {
2011 ch_power_db_rel = ch_power_db + intern_dvb_c_qam_ref[(MS_U8)Qam_mode];
2012 }
2013 else
2014 {
2015 ch_power_db_rel = -100.0f;
2016 }
2017
2018 if(ch_power_db_rel <= -85.0f)
2019 {*strength = 0;}
2020 else if (ch_power_db_rel <= -80.0f)
2021 {*strength = (MS_U16)(0.0f + (ch_power_db_rel+85.0f)*10.0f/5.0f);}
2022 else if (ch_power_db_rel <= -75.0f)
2023 {*strength = (MS_U16)(10.0f + (ch_power_db_rel+80.0f)*20.0f/5.0f);}
2024 else if (ch_power_db_rel <= -70.0f)
2025 {*strength = (MS_U16)(30.0f + (ch_power_db_rel+75.0f)*30.0f/5.0f);}
2026 else if (ch_power_db_rel <= -65.0f)
2027 {*strength = (MS_U16)(60.0f + (ch_power_db_rel+70.0f)*10.0f/5.0f);}
2028 else if (ch_power_db_rel <= -55.0f)
2029 {*strength = (MS_U16)(70.0f + (ch_power_db_rel+65.0f)*20.0f/10.0f);}
2030 else if (ch_power_db_rel <= -45.0f)
2031 {*strength = (MS_U16)(90.0f + (ch_power_db_rel+55.0f)*10.0f/10.0f);}
2032 else
2033 {*strength = 100;}
2034
2035 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
2036 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength));
2037
2038 return status;
2039 }
2040
2041 /****************************************************************************
2042 Subject: To get the DVT Signal quility
2043 Function: INTERN_DVBC_GetSignalQuality
2044 Parmeter: Quility
2045 Return: E_RESULT_SUCCESS
2046 E_RESULT_FAILURE
2047 Remark: Here we have 4 level range
2048 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
2049 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
2050 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
2051 <4>.4th Range => Quality <10
2052 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(MS_U16 * quality,const DMD_DVBC_InitData * sDMD_DVBC_InitData,MS_U8 u8SarValue,float fRFPowerDbm)2053 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2054 {
2055
2056 float fber;
2057 float log_ber;
2058 MS_BOOL status = true;
2059 DMD_DVBC_MODULATION_TYPE Qam_mode;
2060 float f_snr;
2061
2062 fRFPowerDbm = fRFPowerDbm;
2063 status &= INTERN_DVBC_GetSNR(&f_snr);
2064 if (TRUE == INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_PSYNC_LOCK, 200.0f, -200.0f, 0))
2065 {
2066 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
2067 {
2068 ULOGE("DEMOD","\nGetPostViterbiBer Fail!");
2069 return FALSE;
2070 }
2071
2072 // log_ber = log10(fber)
2073 log_ber = (-1.0f)*Log10Approx(1.0f/fber); // Log10Approx() provide 1~2^32 input range only
2074
2075 ULOGD("DEMOD","\nLog(BER) = %f",log_ber);
2076 status &= INTERN_DVBC_GetCurrentModulationType(&Qam_mode);
2077 if (Qam_mode == DMD_DVBC_QAM16)
2078 {
2079 if(log_ber <= (-5.5f))
2080 *quality = 100;
2081 else if(log_ber <= (-5.1f))
2082 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.5f)));
2083 else if(log_ber <= (-4.9f))
2084 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2085 else if(log_ber <= (-4.5f))
2086 *quality = (MS_U16)(70.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.9f)));
2087 else if(log_ber <= (-3.7f))
2088 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.5f)));
2089 else if(log_ber <= (-3.2f))
2090 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2091 else if(log_ber <= (-2.9f))
2092 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2093 else if(log_ber <= (-2.5f))
2094 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.9f)));
2095 else if(log_ber <= (-2.2f))
2096 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.5f)));
2097 else if(log_ber <= (-2.0f))
2098 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2099 else
2100 *quality = 0;
2101 }
2102 else if (Qam_mode == DMD_DVBC_QAM32)
2103 {
2104 if(log_ber <= (-5.0f))
2105 *quality = 100;
2106 else if(log_ber <= (-4.7f))
2107 *quality = (MS_U16)(90.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-5.0f)));
2108 else if(log_ber <= (-4.5f))
2109 *quality = (MS_U16)(80.0f + ((-4.5f)-log_ber)*10.0f/((-4.5f)-(-4.7f)));
2110 else if(log_ber <= (-3.8f))
2111 *quality = (MS_U16)(70.0f + ((-3.8f)-log_ber)*10.0f/((-3.8f)-(-4.5f)));
2112 else if(log_ber <= (-3.5f))
2113 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-3.8f)));
2114 else if(log_ber <= (-3.0f))
2115 *quality = (MS_U16)(50.0f + ((-3.0f)-log_ber)*10.0f/((-3.0f)-(-3.5f)));
2116 else if(log_ber <= (-2.7f))
2117 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.0f)));
2118 else if(log_ber <= (-2.4f))
2119 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2120 else if(log_ber <= (-2.2f))
2121 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2122 else if(log_ber <= (-2.0f))
2123 *quality = (MS_U16)(0.0f + ((-2.0f)-log_ber)*10.0f/((-2.0f)-(-2.2f)));
2124 else
2125 *quality = 0;
2126 }
2127 else if (Qam_mode == DMD_DVBC_QAM64)
2128 {
2129 if(log_ber <= (-5.4f))
2130 *quality = 100;
2131 else if(log_ber <= (-5.1f))
2132 *quality = (MS_U16)(90.0f + ((-5.1f)-log_ber)*10.0f/((-5.1f)-(-5.4f)));
2133 else if(log_ber <= (-4.9f))
2134 *quality = (MS_U16)(80.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2135 else if(log_ber <= (-4.3f))
2136 *quality = (MS_U16)(70.0f + ((-4.3f)-log_ber)*10.0f/((-4.3f)-(-4.9f)));
2137 else if(log_ber <= (-3.7f))
2138 *quality = (MS_U16)(60.0f + ((-3.7f)-log_ber)*10.0f/((-3.7f)-(-4.3f)));
2139 else if(log_ber <= (-3.2f))
2140 *quality = (MS_U16)(50.0f + ((-3.2f)-log_ber)*10.0f/((-3.2f)-(-3.7f)));
2141 else if(log_ber <= (-2.9f))
2142 *quality = (MS_U16)(40.0f + ((-2.9f)-log_ber)*10.0f/((-2.9f)-(-3.2f)));
2143 else if(log_ber <= (-2.4f))
2144 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.9f)));
2145 else if(log_ber <= (-2.2f))
2146 *quality = (MS_U16)(20.0f + ((-2.2f)-log_ber)*10.0f/((-2.2f)-(-2.4f)));
2147 else if(log_ber <= (-2.05f))
2148 *quality = (MS_U16)(0.0f + ((-2.05f)-log_ber)*10.0f/((-2.05f)-(-2.2f)));
2149 else
2150 *quality = 0;
2151 }
2152 else if (Qam_mode == DMD_DVBC_QAM128)
2153 {
2154 if(log_ber <= (-5.1f))
2155 *quality = 100;
2156 else if(log_ber <= (-4.9f))
2157 *quality = (MS_U16)(90.0f + ((-4.9f)-log_ber)*10.0f/((-4.9f)-(-5.1f)));
2158 else if(log_ber <= (-4.7f))
2159 *quality = (MS_U16)(80.0f + ((-4.7f)-log_ber)*10.0f/((-4.7f)-(-4.9f)));
2160 else if(log_ber <= (-4.1f))
2161 *quality = (MS_U16)(70.0f + ((-4.1f)-log_ber)*10.0f/((-4.1f)-(-4.7f)));
2162 else if(log_ber <= (-3.5f))
2163 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.1f)));
2164 else if(log_ber <= (-3.1f))
2165 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2166 else if(log_ber <= (-2.7f))
2167 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2168 else if(log_ber <= (-2.5f))
2169 *quality = (MS_U16)(30.0f + ((-2.5f)-log_ber)*10.0f/((-2.5f)-(-2.7f)));
2170 else if(log_ber <= (-2.06f))
2171 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.5f)));
2172 //else if(log_ber <= (-2.05))
2173 else
2174 {
2175 if (f_snr >= 27.2f)
2176 *quality = 20;
2177 else if (f_snr >= 25.1f)
2178 *quality = (MS_U16)(0.0f + (f_snr - 25.1f)*20.0f/(27.2f-25.1f));
2179 else
2180 *quality = 0;
2181 }
2182 }
2183 else //256QAM
2184 {
2185 if(log_ber <= (-4.8f))
2186 *quality = 100;
2187 else if(log_ber <= (-4.6f))
2188 *quality = (MS_U16)(90.0f + ((-4.6f)-log_ber)*10.0f/((-4.6f)-(-4.8f)));
2189 else if(log_ber <= (-4.4f))
2190 *quality = (MS_U16)(80.0f + ((-4.4f)-log_ber)*10.0f/((-4.4f)-(-4.6f)));
2191 else if(log_ber <= (-4.0f))
2192 *quality = (MS_U16)(70.0f + ((-4.0f)-log_ber)*10.0f/((-4.0f)-(-4.4f)));
2193 else if(log_ber <= (-3.5f))
2194 *quality = (MS_U16)(60.0f + ((-3.5f)-log_ber)*10.0f/((-3.5f)-(-4.0f)));
2195 else if(log_ber <= (-3.1f))
2196 *quality = (MS_U16)(50.0f + ((-3.1f)-log_ber)*10.0f/((-3.1f)-(-3.5f)));
2197 else if(log_ber <= (-2.7f))
2198 *quality = (MS_U16)(40.0f + ((-2.7f)-log_ber)*10.0f/((-2.7f)-(-3.1f)));
2199 else if(log_ber <= (-2.4f))
2200 *quality = (MS_U16)(30.0f + ((-2.4f)-log_ber)*10.0f/((-2.4f)-(-2.7f)));
2201 else if(log_ber <= (-2.06f))
2202 *quality = (MS_U16)(20.0f + ((-2.06f)-log_ber)*10.0f/((-2.06f)-(-2.4f)));
2203 //else if(log_ber <= (-2.05))
2204 else
2205 {
2206 if (f_snr >= 29.6f)
2207 *quality = 20;
2208 else if (f_snr >= 27.3f)
2209 *quality = (MS_U16)(0.0f + (f_snr - 27.3f)*20.0f/(29.6f-27.3f));
2210 else
2211 *quality = 0;
2212 }
2213 }
2214 }
2215 else
2216 {
2217 *quality = 0;
2218 }
2219
2220 //DBG_GET_SIGNAL_DVBC(ULOGD("Utopia","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2221 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","BER = %8.3e\n", fber));
2222 DBG_GET_SIGNAL_DVBC(ULOGD("DEMOD","Signal Quility = %d\n", *quality));
2223 return TRUE;
2224 }
2225
2226 /****************************************************************************
2227 Subject: To get the Cell ID
2228 Function: INTERN_DVBC_Get_CELL_ID
2229 Parmeter: point to return parameter cell_id
2230
2231 Return: TRUE
2232 FALSE
2233 Remark:
2234 *****************************************************************************/
INTERN_DVBC_Get_CELL_ID(MS_U16 * cell_id)2235 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id)
2236 {
2237 MS_BOOL status = true;
2238 MS_U8 value1 = 0;
2239 MS_U8 value2 = 0;
2240
2241 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
2242 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
2243
2244 *cell_id = ((MS_U16)value1<<8)|value2;
2245 return status;
2246 }
2247
2248 /****************************************************************************
2249 Subject: To get the DVBC Carrier Freq Offset
2250 Function: INTERN_DVBC_Get_FreqOffset
2251 Parmeter: Frequency offset (in KHz), bandwidth
2252 Return: E_RESULT_SUCCESS
2253 E_RESULT_FAILURE
2254 Remark:
2255 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2256 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2257 {
2258 MS_U16 FreqB, config_Fc=0;
2259 float FreqCfo_offset,f_Fc;
2260 MS_U32 RegCfo_offset, Reg_Fc_over_Fs;
2261 MS_U8 reg = 0;
2262 MS_BOOL status = TRUE;
2263
2264 // no use.
2265 u8BW = u8BW;
2266 ULOGD("DEMOD","INTERN_DVBC_Get_FreqOffset\n");
2267
2268 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2269 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x20);
2270 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x80);
2271
2272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, ®);
2273 RegCfo_offset = reg;
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, ®);
2275 RegCfo_offset = (RegCfo_offset<<8)|reg;
2276 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, ®);
2277 RegCfo_offset = (RegCfo_offset<<8)|reg;
2278 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, ®);
2279 RegCfo_offset = (RegCfo_offset<<8)|reg;
2280
2281 // bank 2c 0x3d [0] reg_bit_err_num_freeze
2282 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE + 0x3A, 0x00);
2283 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE + 0x05, 0x00);
2284
2285 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, ®);
2286 Reg_Fc_over_Fs = reg;
2287 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, ®);
2288 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2289 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, ®);
2290 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, ®);
2292 Reg_Fc_over_Fs = (Reg_Fc_over_Fs<<8)|reg;
2293
2294 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_H, ®);
2295 config_Fc = reg;
2296 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_DVBC_CFG_FC_L, ®);
2297 config_Fc = (config_Fc<<8)|reg;
2298
2299 f_Fc = (float)Reg_Fc_over_Fs/134217728.0f * 45473.0f;
2300
2301 FreqCfo_offset = (MS_S32)(RegCfo_offset<<4)/16;
2302
2303 FreqCfo_offset = FreqCfo_offset/0x8000000/8.0f;
2304
2305 status &= INTERN_DVBC_GetCurrentSymbolRate(&FreqB);
2306
2307 FreqCfo_offset = FreqCfo_offset * FreqB - (f_Fc-(float)config_Fc);
2308 //ULOGD("DEMOD","[dvbc]Freq_Offset = %f KHz, Reg_offset = 0x%lx, Reg_Fc_over_Fs=0x%lx, SR = %d KS/s, Fc = %f %d\n",
2309 // FreqCfo_offset,RegCfo_offset,Reg_Fc_over_Fs,FreqB,f_Fc,config_Fc);
2310
2311 *pFreqOff = FreqCfo_offset;
2312
2313 return status;
2314 }
2315
2316
2317
INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)2318 void INTERN_DVBC_Power_ON_OFF(MS_U8 bPowerOn)
2319 {
2320
2321 bPowerOn = bPowerOn;
2322 }
2323
INTERN_DVBC_Power_Save(void)2324 MS_BOOL INTERN_DVBC_Power_Save(void)
2325 {
2326
2327 return TRUE;
2328 }
2329
2330 /****************************************************************************
2331 Subject: To get the current modulation type at the DVB-C Demod
2332 Function: INTERN_DVBC_GetCurrentModulationType
2333 Parmeter: pointer for return QAM type
2334
2335 Return: TRUE
2336 FALSE
2337 Remark:
2338 *****************************************************************************/
INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE * pQAMMode)2339 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode)
2340 {
2341 MS_U8 u8Data=0;
2342
2343 ULOGD("DEMOD","INTERN_DVBC_GetCurrentModulationType\n");
2344
2345 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &u8Data);
2346
2347 switch(u8Data&0x07)
2348 {
2349 case 0:
2350 *pQAMMode = DMD_DVBC_QAM16;
2351 ULOGD("DEMOD","[dvbc]QAM=16\n");
2352 return TRUE;
2353 break;
2354 case 1:
2355 *pQAMMode = DMD_DVBC_QAM32;
2356 ULOGD("DEMOD","[dvbc]QAM=32\n");
2357 return TRUE;
2358 break;
2359 case 2:
2360 *pQAMMode = DMD_DVBC_QAM64;
2361 ULOGD("DEMOD","[dvbc]QAM=64\n");
2362 return TRUE;
2363 break;
2364 case 3:
2365 *pQAMMode = DMD_DVBC_QAM128;
2366 ULOGD("DEMOD","[dvbc]QAM=128\n");
2367 return TRUE;
2368 break;
2369 case 4:
2370 *pQAMMode = DMD_DVBC_QAM256;
2371 ULOGD("DEMOD","[dvbc]QAM=256\n");
2372 return TRUE;
2373 break;
2374 default:
2375 *pQAMMode = DMD_DVBC_QAMAUTO;
2376 ULOGD("DEMOD","[dvbc]QAM=invalid\n");
2377 return FALSE;
2378 }
2379 }
2380
2381 /****************************************************************************
2382 Subject: To get the current symbol rate at the DVB-C Demod
2383 Function: INTERN_DVBC_GetCurrentSymbolRate
2384 Parmeter: pointer pData for return Symbolrate
2385
2386 Return: TRUE
2387 FALSE
2388 Remark:
2389 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRate(MS_U16 * u16SymbolRate)2390 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate)
2391 {
2392 MS_U8 tmp = 0;
2393 MS_U16 u16SymbolRateTmp = 0;
2394
2395 // intp
2396 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd2, &tmp);
2397 u16SymbolRateTmp = tmp;
2398 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xd1, &tmp);
2399 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
2400
2401 if (abs(u16SymbolRateTmp-6900)<2)
2402 {
2403 u16SymbolRateTmp=6900;
2404 }
2405
2406 if (abs(u16SymbolRateTmp-6875)<2)
2407 {
2408 u16SymbolRateTmp=6875;
2409 }
2410
2411 *u16SymbolRate = u16SymbolRateTmp;
2412
2413 ULOGD("DEMOD","[dvbc]SR=%d\n",*u16SymbolRate);
2414
2415 return TRUE;
2416 }
2417
2418
2419 /****************************************************************************
2420 Subject: To get the current symbol rate offset at the DVB-C Demod
2421 Function: INTERN_DVBC_GetCurrentSymbolRate
2422 Parmeter: pointer pData for return Symbolrate offset
2423
2424 Return: TRUE
2425 FALSE
2426 Remark:
2427 *****************************************************************************/
INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 * pData)2428 MS_BOOL INTERN_DVBC_GetCurrentSymbolRateOffset(MS_U16 *pData)
2429 {
2430 MS_U8 u8Data = 0;
2431 MS_U32 u32Data = 0;
2432 // MS_S32 s32Data = 0;
2433 MS_BOOL status = TRUE;
2434 MS_U16 u16SymbolRate = 0;
2435 float f_symb_offset = 0.0f;
2436
2437
2438 // bank 26 0x03 [7] reg_bit_err_num_freeze
2439 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(EQE_REG_BASE+0x3A, 0x00);
2440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x4A, 0x00);
2441 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x05, 0x80);
2442
2443 // sel, SFO debug output.
2444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4E, &u8Data);
2445 u32Data = u8Data;
2446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4D, &u8Data);
2447 u32Data = (u32Data<<8)|u8Data;
2448 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE+0x4C, &u8Data);
2449 u32Data = (u32Data<<8)|u8Data;
2450
2451 // bank 26 0x03 [7] reg_bit_err_num_freeze
2452 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(INNC_REG_BASE+0x05, 0x00);
2453 // s32Data = (MS_S32)(u32Data<<8);
2454
2455 ULOGD("DEMOD","[dvbc]u32_symb_offset = 0x%x\n",(unsigned int)u32Data);
2456
2457 status &= INTERN_DVBC_GetCurrentSymbolRate(&u16SymbolRate);
2458 if (u32Data >= 0x800000)
2459 {
2460 u32Data = 0x1000000 - u32Data;
2461 f_symb_offset = -1.0f*(float)u32Data * 0.003725f * (float)u16SymbolRate/(float)DVBC_FS;
2462 }
2463 else
2464 {
2465 f_symb_offset = (float)u32Data * 0.003725f * (float)u16SymbolRate/(float)DVBC_FS;
2466 }
2467
2468 *pData = (MS_U16)(f_symb_offset + 0.5f);
2469
2470 ULOGD("DEMOD","[dvbc]sfo_offset = %d,%f\n",*pData, f_symb_offset);
2471
2472 return status;
2473 }
2474
INTERN_DVBC_Version(MS_U16 * ver)2475 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver)
2476 {
2477
2478 MS_U8 status = true;
2479 MS_U8 tmp = 0;
2480 MS_U16 u16_INTERN_DVBC_Version;
2481
2482 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2483 u16_INTERN_DVBC_Version = tmp;
2484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2485 u16_INTERN_DVBC_Version = u16_INTERN_DVBC_Version<<8|tmp;
2486 *ver = u16_INTERN_DVBC_Version;
2487
2488 return status;
2489 }
2490
2491
INTERN_DVBC_Show_Demod_Version(void)2492 MS_BOOL INTERN_DVBC_Show_Demod_Version(void)
2493 {
2494
2495 MS_BOOL status = true;
2496 MS_U16 u16_INTERN_DVBC_Version;
2497
2498 status &= INTERN_DVBC_Version(&u16_INTERN_DVBC_Version);
2499
2500 ULOGD("DEMOD","[DVBC]Version = %x\n",u16_INTERN_DVBC_Version);
2501
2502 return status;
2503 }
2504
2505
2506
2507
2508
INTERN_DVBC_Show_AGC_Info(void)2509 MS_BOOL INTERN_DVBC_Show_AGC_Info(void)
2510 {
2511 MS_U8 tmp = 0;
2512 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2513 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2514 MS_U16 if_agc_err = 0;
2515 MS_BOOL status = TRUE;
2516
2517 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x11,&agc_k);
2518 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13,&agc_ref);
2519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB0,&d1_k);
2520 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xB1,&d1_ref);
2521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC0,&d2_k);
2522 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xC1,&d2_ref);
2523
2524
2525 // select IF gain to read
2526 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2527 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x03);
2528
2529 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2530 if_agc_gain = tmp;
2531 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2532 if_agc_gain = (if_agc_gain<<8)|tmp;
2533
2534
2535 // select d1 gain to read.
2536 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb6, &tmp);
2537 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xb6, (tmp&0xF0)|0x02);
2538
2539 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb9, &tmp);
2540 d1_gain = tmp;
2541 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xb8, &tmp);
2542 d1_gain = (d1_gain<<8)|tmp;
2543
2544 // select d2 gain to read.
2545 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc6, &tmp);
2546 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0xc6, (tmp&0xF0)|0x02);
2547
2548 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc9, &tmp);
2549 d2_gain = tmp;
2550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xc8, &tmp);
2551 d2_gain = (d2_gain<<8)|tmp;
2552
2553 // select IF gain err to read
2554 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, &tmp);
2555 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (tmp&0xF0)|0x00);
2556
2557 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, &tmp);
2558 if_agc_err = tmp;
2559 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, &tmp);
2560 if_agc_err = (if_agc_err<<8)|tmp;
2561
2562 ULOGD("DEMOD","[dvbc]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2563 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2564
2565 ULOGD("DEMOD","[dvbc]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2566
2567 return status;
2568 }
2569
INTERN_DVBC_info(void)2570 void INTERN_DVBC_info(void)
2571 {
2572 MS_U32 fb_fs = 0, fc_fs = 0, tr_error = 0, crv = 0, intp = 0;
2573 MS_U8 qam,tmp = 0;
2574 MS_U8 fft_u8 = 0;
2575 MS_U16 fft_u16bw = 0;
2576 MS_U16 version = 0,packetErr = 0,quality = 0,symb_rate = 0,symb_offset = 0;
2577 float f_snr = 0,f_freq = 0;
2578 DMD_DVBC_MODULATION_TYPE QAMMode = 0;
2579 MS_U16 f_start = 0,f_end = 0;
2580 MS_U8 s0_count = 0;
2581 MS_U8 sc4 = 0,sc3 = 0;
2582 MS_U8 kp0, kp1, kp2, kp3,kp4, fmax, era_th;
2583 MS_U16 aci_e0,aci_e1,aci_e2,aci_e3;
2584 MS_U16 count = 0;
2585 MS_U16 fb_i_1,fb_q_1;
2586 MS_U8 e0 = 0,e1 = 0,e2 = 0,e3 = 0 ;
2587 MS_S16 reg_freq;
2588 float freq,mag;
2589
2590
2591
2592 INTERN_DVBC_Version(&version);
2593
2594 // fb_fs
2595 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x53, &tmp);
2596 fb_fs = tmp;
2597 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x52, &tmp);
2598 fb_fs = (fb_fs<<8)|tmp;
2599 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x51, &tmp);
2600 fb_fs = (fb_fs<<8)|tmp;
2601 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x50, &tmp);
2602 fb_fs = (fb_fs<<8)|tmp;
2603 // fc_fs
2604 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x57, &tmp);
2605 fc_fs = tmp;
2606 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x56, &tmp);
2607 fc_fs = (fc_fs<<8)|tmp;
2608 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x55, &tmp);
2609 fc_fs = (fc_fs<<8)|tmp;
2610 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x54, &tmp);
2611 fc_fs = (fc_fs<<8)|tmp;
2612 // crv
2613 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x43, &tmp);
2614 crv = tmp;
2615 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x42, &tmp);
2616 crv = (crv<<8)|tmp;
2617 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x41, &tmp);
2618 crv = (crv<<8)|tmp;
2619 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x40, &tmp);
2620 crv = (crv<<8)|tmp;
2621 // tr_error
2622 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4E, &tmp);
2623 tr_error = tmp;
2624 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4D, &tmp);
2625 tr_error = (tr_error<<8)|tmp;
2626 MDrv_SYS_DMD_VD_MBX_ReadReg(INNC_REG_BASE + 0x4C, &tmp);
2627 tr_error = (tr_error<<8)|tmp;
2628
2629 // intp
2630 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD3, &tmp);
2631 intp = tmp;
2632 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD2, &tmp);
2633 intp = (intp<<8)|tmp;
2634 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD1, &tmp);
2635 intp = (intp<<8)|tmp;
2636 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0xD0, &tmp);
2637 intp = (intp<<8)|tmp;
2638
2639 // fft info
2640 // intp
2641 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x93, &tmp);
2642 fft_u16bw = tmp;
2643 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x92, &tmp);
2644 fft_u16bw = (fft_u16bw<<8)|tmp;
2645 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x96, &tmp);
2646 fft_u8 = tmp;
2647
2648
2649 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x02, &tmp);
2650 qam = tmp;
2651
2652 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &tmp);
2653 f_start = tmp;
2654 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &tmp);
2655 f_start = (f_start<<8)|tmp;
2656 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &tmp);
2657 f_end = tmp;
2658 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &tmp);
2659 f_end = (f_end<<8)|tmp;
2660 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE4, &tmp);
2661 s0_count = tmp;
2662
2663 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, &sc3);
2664 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC4, &sc4);
2665
2666 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x04, &kp0);
2667 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x05, &kp1);
2668 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x06, &kp2);
2669 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x07, &kp3);
2670 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x08, &kp4);
2671 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x0B, &fmax);
2672 MDrv_SYS_DMD_VD_MBX_ReadReg(EQE_REG_BASE + 0x49, &era_th);
2673
2674
2675 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x00);
2676
2677 count = 0x400;
2678 while(count--);
2679
2680 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2681 aci_e0 = tmp&0x0f;
2682 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2683 aci_e0 = aci_e0<<8|tmp;
2684
2685 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x01);
2686
2687 count = 0x400;
2688 while(count--);
2689
2690
2691 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2692 aci_e1 = tmp&0x0f;
2693 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2694 aci_e1 = aci_e1<<8|tmp;
2695
2696 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x02);
2697
2698 count = 0x400;
2699 while(count--);
2700
2701 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2702 aci_e2 = tmp&0x0f;
2703 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2704 aci_e2 = aci_e2<<8|tmp;
2705
2706 // read aci coef
2707 MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x81, 0x03);
2708
2709 count = 0x400;
2710 while(count--);
2711
2712 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x85, &tmp);
2713 aci_e3 = tmp&0x0f;
2714 MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x84, &tmp);
2715 aci_e3 = aci_e3<<8|tmp;
2716
2717 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x13, &tmp);
2718 fb_i_1 = tmp;
2719 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x12, &tmp);
2720 fb_i_1 = fb_i_1<<8|tmp;
2721
2722 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x15, &tmp);
2723 fb_q_1 = tmp;
2724 MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x14, &tmp);
2725 fb_q_1 = fb_q_1<<8|tmp;
2726
2727
2728 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE0, &e0);
2729 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE1, &e1);
2730 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE2, &e2);
2731 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xE3, &e3);
2732
2733 reg_freq = (MS_S16)((MS_U16)e1)<<8|e0;
2734 freq = (float)reg_freq*45473.0/65536.0;
2735 mag = (float)(((MS_U16)e3)<<8|e2)/65536.0;
2736
2737
2738 INTERN_DVBC_GetPacketErr(&packetErr);
2739 INTERN_DVBC_GetSNR(&f_snr);
2740 INTERN_DVBC_Show_AGC_Info();
2741 INTERN_DVBC_GetSignalQuality(&quality,NULL,0, 200.0f);
2742 INTERN_DVBC_Get_FreqOffset(&f_freq,8);
2743 INTERN_DVBC_GetCurrentSymbolRate(&symb_rate);
2744 INTERN_DVBC_GetCurrentSymbolRateOffset(&symb_offset);
2745 INTERN_DVBC_GetCurrentModulationType(&QAMMode);
2746
2747 //ULOGD("DEMOD","[MStar_1][1]0x%x,[2]0x%lx,[3]0x%lx,[4]0x%lx,[5]0x%lx,[6]0x%x,[7]%d\n",version,fb_fs,fc_fs,tr_error,crv,qam,packetErr);
2748 //ULOGD("DEMOD","[MStar_2][1]%f,[2]0x%lx,[3]%d,[4]%f,[5]%d,[6]%d,[7]%d\n",f_snr,intp,quality,f_freq,symb_rate,symb_offset,packetErr);
2749 ULOGD("DEMOD","[Mstar_3][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]%d,[6]0x%x,[7]0x%x\n",fft_u16bw,fft_u8,f_end,f_start,s0_count,sc3,sc4);
2750 ULOGD("DEMOD","[Mstar_4][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",kp0,kp1,kp2,kp3,kp4,fmax,era_th);
2751 ULOGD("DEMOD","[Mstar_5][1]0x%x,[2]0x%x,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",aci_e0,aci_e1,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2752 ULOGD("DEMOD","[Mstar_6][1]%f,[2]%f,[3]0x%x,[4]0x%x,[5]0x%x,[6]0x%x,[7]0x%x\n",freq,mag,aci_e2,aci_e3,fb_i_1,fb_q_1,era_th);
2753 return;
2754 }
2755
2756
2757
2758
2759 /***********************************************************************************
2760 Subject: read register
2761 Function: MDrv_1210_IIC_Bypass_Mode
2762 Parmeter:
2763 Return:
2764 Remark:
2765 ************************************************************************************/
2766 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
2767 //{
2768 // UNUSED(enable);
2769 // if (enable)
2770 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
2771 // else
2772 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
2773 //}
2774