1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_DTMB.h"
106
107 #include "MsTypes.h"
108 #if DMD_DTMB_UTOPIA_EN || DMD_DTMB_UTOPIA2_EN
109 #include "drvDMD_common.h"
110 #include "halDMD_INTERN_common.h"
111 #endif
112
113 //-------------------------------------------------------------------------------------------------
114 // Driver Compiler Options
115 //-------------------------------------------------------------------------------------------------
116
117 #define DMD_DTMB_CHIP_NIKON 0x00
118 #define DMD_DTMB_CHIP_NASA 0x01
119 #define DMD_DTMB_CHIP_MADISON 0x02
120 #define DMD_DTMB_CHIP_MONACO 0x03
121 #define DMD_DTMB_CHIP_MUJI 0x04
122 #define DMD_DTMB_CHIP_MONET 0x05
123 #define DMD_DTMB_CHIP_MANHATTAN 0x06
124 #define DMD_DTMB_CHIP_MESSI 0x07
125 #define DMD_DTMB_CHIP_MASERATI 0x08
126 #define DMD_DTMB_CHIP_MACAN 0x09
127
128 #if defined(nikon)
129 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
130 #elif defined(nasa)
131 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NASA
132 #elif defined(madison)
133 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MADISON
134 #elif defined(monaco)
135 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONACO
136 #elif defined(muji)
137 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MUJI
138 #elif defined(monet)
139 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MONET
140 #elif defined(manhattan)
141 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MANHATTAN
142 #elif defined(messi)
143 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MESSI
144 #elif defined(maserati)
145 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MASERATI
146 #elif defined(macan)
147 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_MACAN
148 #else
149 #define DMD_DTMB_CHIP_VERSION DMD_DTMB_CHIP_NIKON
150 #endif
151
152 //-------------------------------------------------------------------------------------------------
153 // Local Defines
154 //-------------------------------------------------------------------------------------------------
155 #if 0
156 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr) ) )
157 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_DTMB_ResData->sDMD_DTMB_PriData.virtDMDBaseAddr + (addr), val) )
158 #endif
159 #define HAL_INTERN_DTMB_DBINFO(y) //y
160
161 //#define MBRegBase 0x112600
162 //#define DMDMcuBase 0x103480
163
164 #define DTMB_REG_BASE 0x2600
165
166 #define DTMB_ACI_COEF_SIZE 112
167
168 #define DMD_DTMB_CHIP_ID_NASA 0x6E
169 #define DMD_DTMB_CHIP_ID_WALTZ 0x9C
170
171 //-------------------------------------------------------------------------------------------------
172 // Local Variables
173 //-------------------------------------------------------------------------------------------------
174
175 const MS_U8 INTERN_DTMB_table[] = {
176 #include "DMD_INTERN_DTMB.dat"
177 };
178
179 const MS_U8 INTERN_DTMB_6M_table[] = {
180 #include "DMD_INTERN_DTMB_6M.dat"
181 };
182
183 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
184 const MS_U8 INTERN_DTMB_table_Waltz[] = {
185 #include "DMD_INTERN_DTMB_Waltz.dat"
186 };
187
188 const MS_U8 INTERN_DTMB_6M_table_Waltz[] = {
189 #include "DMD_INTERN_DTMB_6M_Waltz.dat"
190 };
191 #endif
192
193 static MS_U8 _ACI_COEF_TABLE_FS24M_SR8M[DTMB_ACI_COEF_SIZE] = {
194 0x80, 0x06, 0x9f, 0xf4, 0x9f, 0xe8, 0x9f, 0xf0, 0x80, 0x09, 0x80, 0x1f, 0x80, 0x1d, 0x80, 0x03, 0x9f, 0xe3, 0x9f, 0xdc, 0x9f, 0xf7, 0x80, 0x1d, 0x80, 0x2c, 0x80, 0x12, 0x9f, 0xe2,
195 0x9f, 0xc9, 0x9f, 0xe2, 0x80, 0x1a, 0x80, 0x42, 0x80, 0x2f, 0x9f, 0xeb, 0x9f, 0xb2, 0x9f, 0xbe, 0x80, 0x0c, 0x80, 0x5b, 0x80, 0x5e, 0x80, 0x05, 0x9f, 0x9a, 0x9f, 0x81, 0x9f, 0xdf,
196 0x80, 0x6c, 0x80, 0xa7, 0x80, 0x45, 0x9f, 0x8c, 0x9f, 0x24, 0x9f, 0x84, 0x80, 0x7d, 0x81, 0x38, 0x80, 0xe3, 0x9f, 0x7b, 0x9e, 0x0e, 0x9e, 0x1f, 0x80, 0x87, 0x84, 0xa6, 0x88, 0x8c,
197 0x8a, 0x25, 0x80, 0x08, 0x80, 0x0b, 0x80, 0x0b, 0x80, 0x01, 0x9f, 0xee, 0x9f, 0xdf, 0x9f, 0xdb, 0x9f, 0xe8, 0x9f, 0xfd, 0x80, 0x0a};
198
199 static MS_U8 _ACI_COEF_TABLE_FS24M_SR6M[DTMB_ACI_COEF_SIZE] = {
200 0x9F, 0xF1, 0x9F, 0xFB, 0x80, 0x09, 0x80, 0x15, 0x80, 0x17, 0x80, 0x0D, 0x9F, 0xFB, 0x9F, 0xE9, 0x9F, 0xE2, 0x9F, 0xEC, 0x80, 0x04, 0x80, 0x1D, 0x80, 0x27, 0x80, 0x19, 0x9F, 0xFA,
201 0x9F, 0xD9, 0x9F, 0xCE, 0x9F, 0xE1, 0x80, 0x0C, 0x80, 0x35, 0x80, 0x42, 0x80, 0x24, 0x9F, 0xEA, 0x9F, 0xB6, 0x9F, 0xAA, 0x9F, 0xD6, 0x80, 0x26, 0x80, 0x6A, 0x80, 0x72, 0x80, 0x2E,
202 0x9F, 0xBF, 0x9F, 0x66, 0x9F, 0x65, 0x9F, 0xCE, 0x80, 0x71, 0x80, 0xED, 0x80, 0xE2, 0x80, 0x35, 0x9F, 0x2B, 0x9E, 0x5C, 0x9E, 0x72, 0x9F, 0xCA, 0x82, 0x3B, 0x85, 0x13, 0x87, 0x59,
203 0x88, 0x38, 0x80, 0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x02, 0x80, 0x02, 0x80, 0x00, 0x9F, 0xFC, 0x9F, 0xF6, 0x9F, 0xF0, 0x9F, 0xED};
204
205 //-------------------------------------------------------------------------------------------------
206 // Global Variables
207 //-------------------------------------------------------------------------------------------------
208
209 extern MS_U8 u8DMD_DTMB_DMD_ID;
210
211 extern DMD_DTMB_ResData *psDMD_DTMB_ResData;
212
213 //-------------------------------------------------------------------------------------------------
214 // Local Functions
215 //-------------------------------------------------------------------------------------------------
216 #if 0
217 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
218 {
219 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
220 }
221
222 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
223 {
224 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
225 }
226 #endif
227 //static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
228 //{
229 // _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
230 //}
231
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)232 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
233 {
234 MS_U8 u8CheckCount;
235 MS_U8 u8CheckFlag;
236
237 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
238 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
239 HAL_DMD_RIU_WriteByte(MBRegBase + 0x10, u8Data);
240 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x01);
241
242 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
243 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
244
245 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
246 {
247 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
248 if ((u8CheckFlag&0x01)==0)
249 break;
250 MsOS_DelayTask(1);
251 }
252
253 if (u8CheckFlag&0x01)
254 {
255 printf("ERROR: DTMB INTERN DEMOD MBX WRITE TIME OUT!\n");
256 return FALSE;
257 }
258
259 return TRUE;
260 }
261
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)262 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
263 {
264 MS_U8 u8CheckCount;
265 MS_U8 u8CheckFlag;
266
267 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, (u16Addr&0xff));
268 HAL_DMD_RIU_WriteByte(MBRegBase + 0x01, (u16Addr>>8));
269 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
270
271 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
272 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
273
274 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
275 {
276 u8CheckFlag = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
277 if ((u8CheckFlag&0x02)==0)
278 {
279 *u8Data = HAL_DMD_RIU_ReadByte(MBRegBase + 0x10);
280 break;
281 }
282 MsOS_DelayTask(1);
283 }
284
285 if (u8CheckFlag&0x02)
286 {
287 printf("ERROR: DTMB INTERN DEMOD MBX READ TIME OUT!\n");
288 return FALSE;
289 }
290
291 return TRUE;
292 }
293
294 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NIKON)
_HAL_INTERN_DTMB_InitClk(void)295 static void _HAL_INTERN_DTMB_InitClk(void)
296 {
297 MS_U8 u8Val = 0;
298
299 printf("--------------DMD_DTMB_CHIP_NIKON--------------\n");
300
301 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
302 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
303
304 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
305 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
306 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
307 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
308 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
309 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
310 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
311 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
312
313 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
314 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
315 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
316 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
317 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
318 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
319 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
320 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
321 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
322 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
323 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
324 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
325 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
326 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
327 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
328 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
329 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
330 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
331 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
332 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
333 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
334 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
335 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
336 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
337 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
338 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
339 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
340 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
341 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
342
343 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
344 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
345 }
346 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
_HAL_INTERN_DTMB_InitClk(void)347 static void _HAL_INTERN_DTMB_InitClk(void)
348 {
349 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
350
351 MS_U8 u8Val = 0;
352
353 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
354 {
355 printf("--------------DMD_DTMB_CHIP_WALTZ--------------\n");
356
357 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
358 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
359
360 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
361 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
362
363 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
364 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
365
366 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
367 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
368 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
369 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
370
371 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
372 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
373
374 HAL_DMD_RIU_WriteByte(0x111f49, 0xcc);
375 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
376
377 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
378 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
379 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
380 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
381 HAL_DMD_RIU_WriteByte(0x111f75, 0x00);
382 HAL_DMD_RIU_WriteByte(0x111f74, 0x00);
383 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
384 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
385
386 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
387 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
388 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
389 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
390 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
391 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
392 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
393 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
394
395 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
396 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
397 HAL_DMD_RIU_WriteByte(0x111f7a, 0x00);
398 HAL_DMD_RIU_WriteByte(0x111f7b, 0x00);
399 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
400 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
401
402 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
403 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
404
405 HAL_DMD_RIU_WriteByte(0x111f79, 0x00);
406 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
407
408 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
409 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
410
411 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
412 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
413 }
414 else
415 {
416 printf("--------------DMD_DTMB_CHIP_NASA--------------\n");
417
418 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
419 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
420
421 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
422 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
423 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
424 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
425 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
426 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
427 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
428 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
429
430 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
431 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
432 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
433 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
434 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
435 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
436 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
437 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
438 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
439 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
440 //_HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
441 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
442 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
443 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
444 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
445 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
446 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
447 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
448 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
449 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
450 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
451 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
452 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
453 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
454 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
455 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
456 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
457 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
458 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
459
460 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
461 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
462 }
463 }
464 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
_HAL_INTERN_DTMB_InitClk(void)465 static void _HAL_INTERN_DTMB_InitClk(void)
466 {
467 MS_U8 u8Val = 0;
468
469 printf("--------------DMD_DTMB_CHIP_MADISON--------------\n");
470
471 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
472 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
473
474 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
475 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
476 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
477 HAL_DMD_RIU_WriteByte(0x103300, 0x14);
478 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
479 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
480 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
481 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
482
483 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
484 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
485
486 //carl
487 HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
488 HAL_DMD_RIU_WriteByte(0x111f14, 0x01);
489 HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
490 HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
491
492 HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
493 HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
494 HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
495 HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
496 HAL_DMD_RIU_WriteByte(0x111f4f, 0x00);
497 HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
498 HAL_DMD_RIU_WriteByte(0x111f29, 0x0c);
499 HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
500
501 //carl
502 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
503 HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
504
505 //HAL_DMD_RIU_WriteByte(0x111f28, 0x0c);
506 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
507 HAL_DMD_RIU_WriteByte(0x111f2c, 0x00);
508 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
509 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
510 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
511 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
512 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
513 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
514 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
515 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
516 HAL_DMD_RIU_WriteByte(0x111f43, 0x44);
517 HAL_DMD_RIU_WriteByte(0x111f42, 0x44);
518 HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
519 HAL_DMD_RIU_WriteByte(0x111f44, 0xc4);
520 HAL_DMD_RIU_WriteByte(0x111f47, 0x00);
521 HAL_DMD_RIU_WriteByte(0x111f46, 0x00);
522 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
523 HAL_DMD_RIU_WriteByte(0x111f48, 0x04);
524
525 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
526 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
527 }
528 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO)
_HAL_INTERN_DTMB_InitClk(void)529 static void _HAL_INTERN_DTMB_InitClk(void)
530 {
531 MS_U8 u8Val = 0;
532
533 printf("--------------DMD_DTMB_CHIP_MONACO--------------\n");
534
535 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
536 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
537
538 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
539 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
540
541 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
542 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
543
544 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
545 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
546 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
547 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
548
549 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
550 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
551
552 //carl
553 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
554 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
555
556 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
557 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
558 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
559 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
560 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
561 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
562 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
563 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
564 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
565 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
566
567 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
568 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
569 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
570 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
571
572 //carl
573 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
574 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
575 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
576 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
577
578 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
579 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
580
581 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
582
583 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
584 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
585 }
586 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI)
_HAL_INTERN_DTMB_InitClk(void)587 static void _HAL_INTERN_DTMB_InitClk(void)
588 {
589 MS_U8 u8Val = 0;
590
591 printf("--------------DMD_DTMB_CHIP_MUJI--------------\n");
592
593 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
594 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
595
596 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
597 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
598
599 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
600 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
601
602 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
603 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
604 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
605 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
606 HAL_DMD_RIU_WriteByte(0x103302, 0x01); //MUJI add
607 HAL_DMD_RIU_WriteByte(0x103302, 0x00); //MUJI add
608
609 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
610 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
611
612 //carl
613 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
614 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
615
616 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
617 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
618 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
619 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
620 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
621 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
622 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
623 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
624 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
625 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
626
627 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
628 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
629 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
630 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
631
632 //carl
633 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
634 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
635 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
636 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
637
638 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
639 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
640
641 HAL_DMD_RIU_WriteByte(0x111f78, 0x00);
642
643 HAL_DMD_RIU_WriteByte(0x111f51, 0x04); //MUJI add
644 HAL_DMD_RIU_WriteByte(0x111f50, 0x00); //MuJI add
645
646 HAL_DMD_RIU_WriteByte(0x112091, 0x2f); //SRAM power saving
647 HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
648
649 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
650 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
651 }
652 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONET)
_HAL_INTERN_DTMB_InitClk(void)653 static void _HAL_INTERN_DTMB_InitClk(void)
654 {
655 MS_U8 u8Val = 0;
656
657 printf("--------------DMD_DTMB_CHIP_MONET--------------\n");
658
659 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
660 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
661
662 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
663 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
664
665 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
666 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
667
668 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
669 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
670 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
671 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
672 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
673 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
674
675 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
676 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
677
678 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
679 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
680
681 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
682 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
683 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
684 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
685
686 HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
687 HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
688
689 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
690 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
691 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
692 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
693 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
694 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
695
696 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
697 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
698 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
699 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
700
701 //carl
702 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
703 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
704
705 HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
706 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
707
708
709 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
710 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
711
712 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
713 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
714
715 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
716 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
717
718 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
719 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
720
721 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
722 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
723
724 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
725 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
726 }
727 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MANHATTAN)
_HAL_INTERN_DTMB_InitClk(void)728 static void _HAL_INTERN_DTMB_InitClk(void)
729 {
730 MS_U8 u8Val = 0;
731
732 printf("--------------DMD_DTMB_CHIP_MANHATTAN--------------\n");
733
734 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
735 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
736
737 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
738 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
739
740 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
741 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
742
743 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
744 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
745 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
746 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
747 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
748 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
749
750 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
751 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
752
753 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
754 HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
755
756 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
757 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
758 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
759 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
760
761 // HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
762 // HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
763
764 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
765 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
766 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
767 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
768 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
769 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
770
771 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
772 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
773 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
774 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
775
776 //carl
777 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
778 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
779
780 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
781 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
782
783
784 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
785 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
786
787 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
788 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
789
790 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
791 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
792
793 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
794 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
795
796 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
797 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
798
799 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
800 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
801
802 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
803 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
804
805 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
806 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
807
808 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
809 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
810
811 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
812 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
813
814
815 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
816 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
817
818 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
819 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
820 }
821 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MESSI)
_HAL_INTERN_DTMB_InitClk(void)822 static void _HAL_INTERN_DTMB_InitClk(void)
823 {
824 MS_U8 u8Val = 0;
825
826 printf("--------------DMD_DTMB_CHIP_MESSI--------------\n");
827
828 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
829 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
830
831 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
832 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
833
834 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
835 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
836
837 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
838 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
839 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
840 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
841 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
842 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
843
844 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
845 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
846
847 HAL_DMD_RIU_WriteByte(0x111f49, 0x00);//0xcc?
848 //_HAL_DMD_RIU_WriteByte(0x111f48, 0x11);
849 HAL_DMD_RIU_WriteByte(0x111f48, 0x00);//MESSI only?
850
851 HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
852 HAL_DMD_RIU_WriteByte(0x111f22, 0x14);
853 HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
854 HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
855
856 // _HAL_DMD_RIU_WriteByte(0x111f75, 0x00); //monet add
857 // _HAL_DMD_RIU_WriteByte(0x111f74, 0x00); //monet add
858
859 HAL_DMD_RIU_WriteByte(0x111f77, 0x0c);
860 HAL_DMD_RIU_WriteByte(0x111f76, 0x0c);
861 HAL_DMD_RIU_WriteByte(0x111f61, 0x00);
862 HAL_DMD_RIU_WriteByte(0x111f60, 0x00);
863 HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
864 HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
865
866 HAL_DMD_RIU_WriteByte(0x111f65, 0x00);
867 HAL_DMD_RIU_WriteByte(0x111f64, 0x00);
868 HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
869 HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
870
871 //carl
872 HAL_DMD_RIU_WriteByte(0x111f6B, 0x44);
873 HAL_DMD_RIU_WriteByte(0x111f6A, 0x44);
874
875 // HAL_DMD_RIU_WriteByte(0x111f7B, 0x00); //monet add
876 HAL_DMD_RIU_WriteByte(0x111f7A, 0x00); //monet add
877
878
879 HAL_DMD_RIU_WriteByte(0x111f6D, 0x00);
880 HAL_DMD_RIU_WriteByte(0x111f6C, 0xC4);
881
882 HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
883 HAL_DMD_RIU_WriteByte(0x111f70, 0x04);
884
885 HAL_DMD_RIU_WriteByte(0x111f79, 0x00); //moent add
886 HAL_DMD_RIU_WriteByte(0x111f78, 0x00); //monet add
887
888 HAL_DMD_RIU_WriteByte(0x111f51, 0x04);
889 HAL_DMD_RIU_WriteByte(0x111f50, 0x00);
890
891 HAL_DMD_RIU_WriteByte(0x111f81, 0x88);// manhattan adds
892 HAL_DMD_RIU_WriteByte(0x111f80, 0x88);// manhattan adds
893
894 HAL_DMD_RIU_WriteByte(0x111f83, 0xc8);// manhattan adds
895 HAL_DMD_RIU_WriteByte(0x111f82, 0x88);// manhattan adds
896
897 HAL_DMD_RIU_WriteByte(0x111f85, 0x88);// manhattan adds
898 HAL_DMD_RIU_WriteByte(0x111f84, 0x88);// manhattan adds
899
900 HAL_DMD_RIU_WriteByte(0x111f87, 0x08);// manhattan adds
901 HAL_DMD_RIU_WriteByte(0x111f86, 0x88);// manhattan adds
902
903 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);// manhattan adds
904 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);// manhattan adds
905
906 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);// manhattan adds
907 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);// manhattan adds
908
909
910 // HAL_DMD_RIU_WriteByte(0x112091, 0x10); //SRAM power saving
911 // HAL_DMD_RIU_WriteByte(0x112090, 0x00); //SRAM power saving
912
913 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
914 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
915 }
916 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
_HAL_INTERN_DTMB_InitClk(void)917 static void _HAL_INTERN_DTMB_InitClk(void)
918 {
919 MS_U8 u8Val = 0;
920
921 HAL_INTERN_DTMB_DBINFO(printf("--------------DMD_DTMB_CHIP_MASERATI_MACAN--------------\n"));
922
923 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
924 HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
925
926 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
927 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
928
929 HAL_DMD_RIU_WriteByte(0x103301, 0x07);
930 HAL_DMD_RIU_WriteByte(0x103300, 0x11);
931
932 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
933 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
934
935 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
936 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
937
938 HAL_DMD_RIU_WriteByte(0x103302, 0x01);
939 HAL_DMD_RIU_WriteByte(0x103302, 0x00);
940
941 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
942 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
943
944 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
945 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
946
947 HAL_DMD_RIU_WriteByte(0x111f69, 0xCC);
948 HAL_DMD_RIU_WriteByte(0x111f68, 0x11);
949
950 HAL_DMD_RIU_WriteByte(0x152923, 0x00);
951 HAL_DMD_RIU_WriteByte(0x152922, 0x14);
952
953 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
954 HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
955
956 HAL_DMD_RIU_WriteByte(0x152973, 0x00);
957 HAL_DMD_RIU_WriteByte(0x152972, 0x00);
958
959 HAL_DMD_RIU_WriteByte(0x152975, 0x00);
960 HAL_DMD_RIU_WriteByte(0x152974, 0x00);
961
962 HAL_DMD_RIU_WriteByte(0x152977, 0x0c);
963 HAL_DMD_RIU_WriteByte(0x152976, 0x0c);
964
965 HAL_DMD_RIU_WriteByte(0x152961, 0x00);
966 HAL_DMD_RIU_WriteByte(0x152960, 0x00);
967
968 HAL_DMD_RIU_WriteByte(0x152963, 0x00);
969 HAL_DMD_RIU_WriteByte(0x152962, 0x00);
970
971 HAL_DMD_RIU_WriteByte(0x152965, 0x00);
972 HAL_DMD_RIU_WriteByte(0x152964, 0x00);
973
974 HAL_DMD_RIU_WriteByte(0x152969, 0x00);
975 HAL_DMD_RIU_WriteByte(0x152968, 0x00);
976
977 HAL_DMD_RIU_WriteByte(0x15296B, 0x44);
978 HAL_DMD_RIU_WriteByte(0x15296A, 0x44);
979
980 HAL_DMD_RIU_WriteByte(0x15297a, 0x00);
981
982 HAL_DMD_RIU_WriteByte(0x15296d, 0x00);
983 HAL_DMD_RIU_WriteByte(0x15296c, 0xc4);
984
985 HAL_DMD_RIU_WriteByte(0x152971, 0x00);
986 HAL_DMD_RIU_WriteByte(0x152970, 0x04);
987
988 HAL_DMD_RIU_WriteByte(0x152979, 0x00);
989 HAL_DMD_RIU_WriteByte(0x152978, 0x00);
990
991 HAL_DMD_RIU_WriteByte(0x152951, 0x04);
992 HAL_DMD_RIU_WriteByte(0x152950, 0x00);
993
994 HAL_DMD_RIU_WriteByte(0x152981, 0x88);
995 HAL_DMD_RIU_WriteByte(0x152980, 0x88);
996
997 HAL_DMD_RIU_WriteByte(0x152983, 0xc8);
998 HAL_DMD_RIU_WriteByte(0x152982, 0x88);
999
1000 HAL_DMD_RIU_WriteByte(0x152985, 0x88);
1001 HAL_DMD_RIU_WriteByte(0x152984, 0x88);
1002
1003 HAL_DMD_RIU_WriteByte(0x152987, 0x08);
1004 HAL_DMD_RIU_WriteByte(0x152986, 0x8c);
1005
1006 HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
1007 HAL_DMD_RIU_WriteByte(0x111f74, 0x81);
1008
1009 HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
1010 HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
1011
1012 HAL_DMD_RIU_WriteByte(0x15298d, 0x44);
1013 HAL_DMD_RIU_WriteByte(0x15298c, 0x00);
1014
1015 HAL_DMD_RIU_WriteByte(0x15298f, 0x88);
1016 HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
1017
1018 HAL_DMD_RIU_WriteByte(0x152991, 0xc8);
1019 HAL_DMD_RIU_WriteByte(0x152990, 0x88);
1020
1021 HAL_DMD_RIU_WriteByte(0x152993, 0x11);
1022 HAL_DMD_RIU_WriteByte(0x152992, 0x18);
1023
1024 HAL_DMD_RIU_WriteByte(0x111f7b, 0x18);
1025 HAL_DMD_RIU_WriteByte(0x111f7a, 0x11);
1026
1027 HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
1028 HAL_DMD_RIU_WriteByte(0x111f78, 0x88);
1029
1030 HAL_DMD_RIU_WriteByte(0x111f7d, 0x18);
1031 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1032
1033 HAL_DMD_RIU_WriteByte(0x111f89, 0x00);
1034 HAL_DMD_RIU_WriteByte(0x111f88, 0x00);
1035
1036 HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1037 HAL_DMD_RIU_WriteByte(0x111f8a, 0x00);
1038
1039 HAL_DMD_RIU_WriteByte(0x111f31, 0x18);
1040
1041 u8Val = HAL_DMD_RIU_ReadByte(0x101e39);
1042 HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1043 }
1044 #else
_HAL_INTERN_DTMB_InitClk(void)1045 static void _HAL_INTERN_DTMB_InitClk(void)
1046 {
1047 printf("--------------DMD_DTMB_CHIP_NONE--------------\n");
1048 }
1049 #endif
1050
_HAL_INTERN_DTMB_Ready(void)1051 static MS_BOOL _HAL_INTERN_DTMB_Ready(void)
1052 {
1053 MS_U8 udata = 0x00;
1054
1055 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1056
1057 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1058 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1059
1060 MsOS_DelayTask(1);
1061
1062 udata = HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1063
1064 if (udata) return FALSE;
1065
1066 return TRUE;
1067 }
1068
_HAL_INTERN_DTMB_Download(void)1069 static MS_BOOL _HAL_INTERN_DTMB_Download(void)
1070 {
1071 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1072 MS_U8 udata = 0x00;
1073 MS_U16 i = 0;
1074 MS_U16 fail_cnt = 0;
1075 MS_U8 u8TmpData;
1076 MS_U16 u16AddressOffset;
1077 const MS_U8 *DTMB_table;
1078 MS_U16 u16Lib_size;
1079
1080 if (pRes->sDMD_DTMB_PriData.bDownloaded)
1081 {
1082 if (_HAL_INTERN_DTMB_Ready())
1083 {
1084 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1085 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
1086 MsOS_DelayTask(20);
1087 return TRUE;
1088 }
1089 }
1090
1091 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1092 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1093 {
1094 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1095 {
1096 DTMB_table = &INTERN_DTMB_6M_table_Waltz[0];
1097 u16Lib_size = sizeof(INTERN_DTMB_6M_table_Waltz);
1098 }
1099 else
1100 {
1101 DTMB_table = &INTERN_DTMB_table_Waltz[0];
1102 u16Lib_size = sizeof(INTERN_DTMB_table_Waltz);
1103 }
1104 }
1105 else
1106 {
1107 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1108 {
1109 DTMB_table = &INTERN_DTMB_6M_table[0];
1110 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1111 }
1112 else
1113 {
1114 DTMB_table = &INTERN_DTMB_table[0];
1115 u16Lib_size = sizeof(INTERN_DTMB_table);
1116 }
1117 }
1118 #else
1119 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1120 {
1121 DTMB_table = &INTERN_DTMB_6M_table[0];
1122 u16Lib_size = sizeof(INTERN_DTMB_6M_table);
1123 }
1124 else
1125 {
1126 DTMB_table = &INTERN_DTMB_table[0];
1127 u16Lib_size = sizeof(INTERN_DTMB_table);
1128 }
1129 #endif
1130
1131 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1132 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1133
1134 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1135
1136 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1137 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1138 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1139 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1140
1141 //// Load code thru VDMCU_IF ////
1142 HAL_INTERN_DTMB_DBINFO(printf(">Load Code...\n"));
1143
1144 for (i = 0; i < u16Lib_size; i++)
1145 {
1146 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, DTMB_table[i]); // write data to VD MCU 51 code sram
1147 }
1148
1149 //// Content verification ////
1150 HAL_INTERN_DTMB_DBINFO(printf(">Verify Code...\n"));
1151
1152 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1153 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1154
1155 for (i = 0; i < u16Lib_size; i++)
1156 {
1157 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1158
1159 if (udata != DTMB_table[i])
1160 {
1161 HAL_INTERN_DTMB_DBINFO(printf(">fail add = 0x%x\n", i));
1162 HAL_INTERN_DTMB_DBINFO(printf(">code = 0x%x\n", DTMB_table[i]));
1163 HAL_INTERN_DTMB_DBINFO(printf(">data = 0x%x\n", udata));
1164
1165 if (fail_cnt++ > 10)
1166 {
1167 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode fail!"));
1168 return FALSE;
1169 }
1170 }
1171 }
1172
1173 u16AddressOffset = (DTMB_table[0x400] << 8)|DTMB_table[0x401];
1174
1175 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1176 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1177
1178 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16IF_KHZ;
1179 HAL_INTERN_DTMB_DBINFO(printf("u16IF_KHZ=%d\n",pRes->sDMD_DTMB_InitData.u16IF_KHZ));
1180 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1181 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16IF_KHZ >> 8);
1182 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1183 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.bIQSwap;
1184 HAL_INTERN_DTMB_DBINFO(printf("bIQSwap=%d\n",pRes->sDMD_DTMB_InitData.bIQSwap));
1185 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1186 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE;
1187 HAL_INTERN_DTMB_DBINFO(printf("u16AGC_REFERENCE=%X\n",pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE));
1188 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1189 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u16AGC_REFERENCE >> 8);
1190 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1191 u8TmpData = (MS_U8)pRes->sDMD_DTMB_InitData.u32TdiStartAddr;
1192 HAL_INTERN_DTMB_DBINFO(printf("u32TdiStartAddr=%X\n",pRes->sDMD_DTMB_InitData.u32TdiStartAddr));
1193 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1194 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 8);
1195 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1196 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 16);
1197 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1198 u8TmpData = (MS_U8)(pRes->sDMD_DTMB_InitData.u32TdiStartAddr >> 24);
1199 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1200 u8TmpData = (MS_U8)pRes->sDMD_DTMB_PriData.eLastType;
1201 HAL_INTERN_DTMB_DBINFO(printf("eLastType=%d\n",pRes->sDMD_DTMB_PriData.eLastType));
1202 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1203
1204 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1205 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1206
1207 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1208
1209 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1210 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1211
1212 pRes->sDMD_DTMB_PriData.bDownloaded = true;
1213
1214 MsOS_DelayTask(20);
1215
1216 HAL_INTERN_DTMB_DBINFO(printf(">DSP Loadcode done."));
1217
1218 return TRUE;
1219 }
1220
_HAL_INTERN_DTMB_FWVERSION(void)1221 static void _HAL_INTERN_DTMB_FWVERSION(void)
1222 {
1223 MS_U8 data1,data2,data3;
1224
1225 _MBX_ReadReg(0x20C4, &data1);
1226 _MBX_ReadReg(0x20C5, &data2);
1227 _MBX_ReadReg(0x20C6, &data3);
1228
1229 HAL_INTERN_DTMB_DBINFO(printf("INTERN_DTMB_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
1230 }
1231
_HAL_INTERN_DTMB_Exit(void)1232 static MS_BOOL _HAL_INTERN_DTMB_Exit(void)
1233 {
1234 MS_U8 u8CheckCount = 0;
1235
1236 HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1237
1238 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1239 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1240
1241 while ((HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1242 {
1243 MsOS_DelayTaskUs(10);
1244
1245 if (u8CheckCount++ == 0xFF)
1246 {
1247 printf(">> DTMB Exit Fail!\n");
1248 return FALSE;
1249 }
1250 }
1251
1252 printf(">> DTMB Exit Ok!\n");
1253
1254 return TRUE;
1255 }
1256
_HAL_INTERN_DTMB_SoftReset(void)1257 static MS_BOOL _HAL_INTERN_DTMB_SoftReset(void)
1258 {
1259 MS_U8 u8Data = 0;
1260
1261 //Reset FSM
1262 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1263
1264 while (u8Data!=0x02)
1265 {
1266 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1267 }
1268
1269 return TRUE;
1270 }
1271
_HAL_INTERN_DTMB_SetACICoef(void)1272 static MS_BOOL _HAL_INTERN_DTMB_SetACICoef(void)
1273 {
1274 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1275
1276 MS_U8 *ACI_table;
1277 MS_U8 i;
1278 MS_U16 u16AddressOffset;
1279
1280 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB)
1281 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1282 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M)
1283 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1284 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1285 ACI_table = &_ACI_COEF_TABLE_FS24M_SR6M[0];
1286 else if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1287 ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1288 else ACI_table = &_ACI_COEF_TABLE_FS24M_SR8M[0];
1289
1290 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
1291 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1292
1293 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release MCU, madison patch
1294
1295 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1296 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1297 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1298 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1299
1300 //SET SR value
1301 u16AddressOffset = ((INTERN_DTMB_table[0x400] << 8)|INTERN_DTMB_table[0x401]) + 10;
1302 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1303 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1304 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)pRes->sDMD_DTMB_PriData.eLastType);
1305
1306 //set ACI coefficient
1307 u16AddressOffset = ((INTERN_DTMB_table[0x40A] << 8)|INTERN_DTMB_table[0x40B]);
1308 u16AddressOffset = ((INTERN_DTMB_table[u16AddressOffset] << 8)|INTERN_DTMB_table[u16AddressOffset+1]);
1309 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1310 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1311 for (i = 0; i < DTMB_ACI_COEF_SIZE; i++)
1312 {
1313 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ACI_table[i]); // write data to VD MCU 51 code sram
1314 }
1315
1316 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1317 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1318
1319 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
1320
1321 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1322 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
1323
1324 MsOS_DelayTask(20);
1325
1326 return TRUE;
1327 }
1328
_HAL_INTERN_DTMB_SetDtmbMode(void)1329 static MS_BOOL _HAL_INTERN_DTMB_SetDtmbMode(void)
1330 {
1331 if (_MBX_WriteReg(0x20C2, 0x03)==FALSE) return FALSE;
1332 return _MBX_WriteReg(0x20C0, 0x04);
1333 }
1334
_HAL_INTERN_DTMB_SetModeClean(void)1335 static MS_BOOL _HAL_INTERN_DTMB_SetModeClean(void)
1336 {
1337 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1338 return _MBX_WriteReg(0x20C0, 0x00);
1339 }
1340
_HAL_INTERN_DTMB_Set_QAM_SR(void)1341 static MS_BOOL _HAL_INTERN_DTMB_Set_QAM_SR(void)
1342 {
1343 if (_MBX_WriteReg(0x20C2, 0x01)==FALSE) return FALSE;
1344 return _MBX_WriteReg(0x20C0, 0x04);
1345 }
1346
_HAL_INTERN_DTMB_AGCLock(void)1347 static MS_BOOL _HAL_INTERN_DTMB_AGCLock(void)
1348 {
1349 MS_U8 data = 0;
1350
1351 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1352 _MBX_ReadReg(0x2829, &data);//AGC_LOCK
1353 #else
1354 _MBX_ReadReg(0x271D, &data);//AGC_LOCK
1355 #endif
1356 if (data&0x01)
1357 {
1358 return TRUE;
1359 }
1360 else
1361 {
1362 return FALSE;
1363 }
1364 }
1365
_HAL_INTERN_DTMB_PNP_Lock(void)1366 static MS_BOOL _HAL_INTERN_DTMB_PNP_Lock(void)
1367 {
1368 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1369 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1370 #endif
1371
1372 MS_U8 data = 0;
1373 MS_U8 data1 = 0;
1374
1375 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1376 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1377 {
1378 _MBX_ReadReg(0x3BBA, &data);
1379 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1380 }
1381 else
1382 {
1383 _MBX_ReadReg(0x22BA, &data);
1384 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1385 }
1386 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1387 _MBX_ReadReg(0x37BA, &data);
1388 _MBX_ReadReg(0x3849, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1389 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1390 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1391 _MBX_ReadReg(0x11BA, &data);
1392 _MBX_ReadReg(0x1249, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1393 #else
1394 _MBX_ReadReg(0x3BBA, &data);
1395 _MBX_ReadReg(0x3C49, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1396 #endif
1397 #else
1398 _MBX_ReadReg(0x22BA, &data);
1399 _MBX_ReadReg(0x2349, &data1);// CFO_FFT_SEC_VALID (_REG_INNDEXT(0x24)+1)
1400 #endif
1401
1402 if (((data&0x02) == 0x02)&&((data1&0x20)==0x20))
1403 {
1404 return TRUE;
1405 }
1406 else
1407 {
1408 return FALSE;
1409 }
1410 }
1411
_HAL_INTERN_DTMB_FEC_Lock(void)1412 static MS_BOOL _HAL_INTERN_DTMB_FEC_Lock(void)
1413 {
1414 MS_U8 u8state=0;
1415
1416
1417 _MBX_ReadReg(0x20C1, &u8state);
1418
1419 if ((u8state >= 0x62)&& (u8state <= 0xF0))
1420 {
1421 return TRUE;
1422 }
1423 else
1424 {
1425 return FALSE;
1426 }
1427 }
1428
_HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO * psDtmbGetModulation)1429 static MS_BOOL _HAL_INTERN_DTMB_GetModulation(DMD_DTMB_MODULATION_INFO *psDtmbGetModulation)
1430 {
1431 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1432
1433 MS_U8 CM, QAM, IL, CR, SiNR;
1434 MS_U8 data_L = 0;
1435 MS_U8 data_H = 0;
1436
1437 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1438 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1439 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1440 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1441 {
1442 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1443 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1444 {
1445 _MBX_ReadReg(0x3B90, &data_L);
1446 _MBX_ReadReg(0x3B91, &data_H);
1447 }
1448 else
1449 {
1450 _MBX_ReadReg(0x2290, &data_L);
1451 _MBX_ReadReg(0x2291, &data_H);
1452 }
1453 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1454 _MBX_ReadReg(0x3790, &data_L);
1455 _MBX_ReadReg(0x3791, &data_H);
1456 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1457 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1458 _MBX_ReadReg(0x1190, &data_L);
1459 _MBX_ReadReg(0x1191, &data_H);
1460 #else
1461 _MBX_ReadReg(0x3B90, &data_L);
1462 _MBX_ReadReg(0x3B91, &data_H);
1463 #endif
1464 #else
1465 _MBX_ReadReg(0x2290, &data_L);
1466 _MBX_ReadReg(0x2291, &data_H);
1467 #endif
1468
1469 if (data_L & 0x1)
1470 {
1471 CR = (data_L >> 6) & 0x03;
1472 IL = (data_L >> 3) & 0x01;
1473 QAM = (data_L >> 4) & 0x03;
1474 SiNR = (data_L >> 2) & 0x01;
1475 CM = (data_L >> 1) & 0x01;
1476 }
1477 else
1478 {
1479 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1480 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1481 {
1482 _MBX_ReadReg(0x3B9E, &data_L);
1483 _MBX_ReadReg(0x3B9F, &data_H);
1484 }
1485 else
1486 {
1487 _MBX_ReadReg(0x229E, &data_L);
1488 _MBX_ReadReg(0x229F, &data_H);
1489 }
1490 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1491 _MBX_ReadReg(0x379E, &data_L);
1492 _MBX_ReadReg(0x379F, &data_H);
1493 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1494 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1495 _MBX_ReadReg(0x119E, &data_L);
1496 _MBX_ReadReg(0x119F, &data_H);
1497 #else
1498 _MBX_ReadReg(0x3B9E, &data_L);
1499 _MBX_ReadReg(0x3B9F, &data_H);
1500 #endif
1501 #else
1502 _MBX_ReadReg(0x229E, &data_L);
1503 _MBX_ReadReg(0x229F, &data_H);
1504 #endif
1505
1506 CR = (data_H >> 4) & 0x03;
1507 IL = (data_H >> 6) & 0x01;
1508 QAM = (data_H >> 2) & 0x03;
1509 SiNR = (data_H >> 1) & 0x01;
1510 CM = (data_H) & 0x01;
1511 }
1512
1513 #if 1//def MSOS_TYPE_LINUX_KERNEL
1514 if (CR == 0)
1515 psDtmbGetModulation->fSiCodeRate = 4;
1516 else if (CR == 1)
1517 psDtmbGetModulation->fSiCodeRate = 6;
1518 else if (CR == 2)
1519 psDtmbGetModulation->fSiCodeRate = 8;
1520 #else
1521 if (CR == 0)
1522 psDtmbGetModulation->fSiCodeRate = 0.4;
1523 else if (CR == 1)
1524 psDtmbGetModulation->fSiCodeRate = 0.6;
1525 else if (CR == 2)
1526 psDtmbGetModulation->fSiCodeRate = 0.8;
1527 #endif
1528
1529 if (IL == 0)
1530 psDtmbGetModulation->u8SiInterLeaver = 240;
1531 else
1532 psDtmbGetModulation->u8SiInterLeaver = 720;
1533
1534 if (QAM == 0)
1535 psDtmbGetModulation->u8SiQamMode = 4;
1536 else if (QAM == 1)
1537 psDtmbGetModulation->u8SiQamMode = 16;
1538 else if (QAM == 2)
1539 psDtmbGetModulation->u8SiQamMode = 32;
1540 else if (QAM == 3)
1541 psDtmbGetModulation->u8SiQamMode = 64;
1542
1543 psDtmbGetModulation->u8SiCarrierMode = CM; // 0:Multi, 1:Single
1544 psDtmbGetModulation->u8SiNR = SiNR;
1545 }
1546 else
1547 {
1548 }
1549
1550 return TRUE;
1551 }
1552
_HAL_INTERN_DTMB_ReadIFAGC(void)1553 static MS_U8 _HAL_INTERN_DTMB_ReadIFAGC(void)
1554 {
1555 MS_U8 data = 0;
1556 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1557 _MBX_ReadReg(0x280F, &data);
1558 #else
1559 _MBX_ReadReg(0x28FD, &data);
1560 #endif
1561
1562 return data;
1563 }
1564
1565 #ifdef UTPA2
_HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 * pFftfirstCfo,MS_S8 * pFftSecondCfo,MS_S16 * pSr)1566 static MS_BOOL _HAL_INTERN_DTMB_ReadFrequencyOffset(MS_S16 *pFftfirstCfo, MS_S8 *pFftSecondCfo, MS_S16 *pSr)
1567 #else
1568 static MS_S16 _HAL_INTERN_DTMB_ReadFrequencyOffset(void)
1569 #endif
1570 {
1571 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1572
1573 MS_U8 u8Data = 0;
1574 MS_S16 fftfirstCfo = 0;
1575 MS_S8 fftSecondCfo = 0;
1576 MS_S16 sr = 0;
1577
1578 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1579 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1580 {
1581 _MBX_ReadReg(0x3C4D, &u8Data);
1582 fftfirstCfo = u8Data;
1583 _MBX_ReadReg(0x3C4C, &u8Data);
1584 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1585
1586 _MBX_ReadReg(0x3C50, &u8Data);
1587 fftSecondCfo = u8Data;
1588 }
1589 else
1590 {
1591 _MBX_ReadReg(0x234D, &u8Data);
1592 fftfirstCfo = u8Data;
1593 _MBX_ReadReg(0x234C, &u8Data);
1594 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1595
1596 _MBX_ReadReg(0x2350, &u8Data);
1597 fftSecondCfo = u8Data;
1598 }
1599 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1600 _MBX_ReadReg(0x384D, &u8Data);
1601 fftfirstCfo = u8Data;
1602 _MBX_ReadReg(0x384C, &u8Data);
1603 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1604
1605 _MBX_ReadReg(0x3850, &u8Data);
1606 fftSecondCfo = u8Data;
1607 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1608 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1609 _MBX_ReadReg(0x124D, &u8Data);
1610 fftfirstCfo = u8Data;
1611 _MBX_ReadReg(0x124C, &u8Data);
1612 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1613 _MBX_ReadReg(0x1250, &u8Data);
1614 fftSecondCfo = u8Data;
1615 #else
1616 _MBX_ReadReg(0x3C4D, &u8Data);
1617 fftfirstCfo = u8Data;
1618 _MBX_ReadReg(0x3C4C, &u8Data);
1619 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1620
1621 _MBX_ReadReg(0x3C50, &u8Data);
1622 fftSecondCfo = u8Data;
1623 #endif
1624 #else
1625 _MBX_ReadReg(0x234D, &u8Data);
1626 fftfirstCfo = u8Data;
1627 _MBX_ReadReg(0x234C, &u8Data);
1628 fftfirstCfo = (fftfirstCfo<<8)|u8Data;
1629
1630 _MBX_ReadReg(0x2350, &u8Data);
1631 fftSecondCfo = u8Data;
1632 #endif
1633
1634 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M)
1635 sr = 5670;
1636 else sr = 7560;
1637
1638 #ifdef UTPA2
1639 *pFftfirstCfo = fftfirstCfo;
1640 *pFftSecondCfo = fftSecondCfo;
1641 *pSr = sr;
1642
1643 return TRUE;
1644 #else
1645 return (MS_S16)((((double)fftfirstCfo/0x10000+(double)fftSecondCfo/0x20000))*(double)sr);
1646 #endif
1647 }
1648
_HAL_INTERN_DTMB_ReadSNRPercentage(void)1649 static MS_U8 _HAL_INTERN_DTMB_ReadSNRPercentage(void)
1650 {
1651 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1652
1653 MS_U8 data = 0;
1654 MS_U8 level = 0;
1655 MS_U32 snr = 0;
1656
1657 if (pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB ||
1658 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_7M ||
1659 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_6M ||
1660 pRes->sDMD_DTMB_PriData.eLastType == DMD_DTMB_DEMOD_DTMB_5M)
1661 {
1662 if (!_HAL_INTERN_DTMB_FEC_Lock())
1663 level = 0;
1664 else
1665 {
1666 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1667 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1668 {
1669 _MBX_ReadReg(0x3BDA, &data);
1670 snr = data&0x3F;
1671 _MBX_ReadReg(0x3BD9, &data);
1672 snr = (snr<<8)|data;
1673 _MBX_ReadReg(0x3BD8, &data);
1674 snr = (snr<<8)|data;
1675 }
1676 else
1677 {
1678 _MBX_ReadReg(0x22DA, &data);
1679 snr = data&0x3F;
1680 _MBX_ReadReg(0x22D9, &data);
1681 snr = (snr<<8)|data;
1682 _MBX_ReadReg(0x22D8, &data);
1683 snr = (snr<<8)|data;
1684 }
1685 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1686 _MBX_ReadReg(0x37DA, &data);
1687 snr = data&0x3F;
1688 _MBX_ReadReg(0x37D9, &data);
1689 snr = (snr<<8)|data;
1690 _MBX_ReadReg(0x37D8, &data);
1691 snr = (snr<<8)|data;
1692 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1693 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1694 _MBX_ReadReg(0x11DA, &data);
1695 snr = data&0x3F;
1696 _MBX_ReadReg(0x11D9, &data);
1697 snr = (snr<<8)|data;
1698 _MBX_ReadReg(0x11D8, &data);
1699 snr = (snr<<8)|data;
1700 #else
1701 _MBX_ReadReg(0x3BDA, &data);
1702 snr = data&0x3F;
1703 _MBX_ReadReg(0x3BD9, &data);
1704 snr = (snr<<8)|data;
1705 _MBX_ReadReg(0x3BD8, &data);
1706 snr = (snr<<8)|data;
1707 #endif
1708 #else
1709 _MBX_ReadReg(0x22DA, &data);
1710 snr = data&0x3F;
1711 _MBX_ReadReg(0x22D9, &data);
1712 snr = (snr<<8)|data;
1713 _MBX_ReadReg(0x22D8, &data);
1714 snr = (snr<<8)|data;
1715 #endif
1716
1717 if (snr <= 4340 ) level = 1; // SNR <= 0.6 dB
1718 else if (snr <= 4983 ) level = 2; // SNR <= 1.2 dB
1719 else if (snr <= 5721 ) level = 3; // SNR <= 1.8 dB
1720 else if (snr <= 6569 ) level = 4; // SNR <= 2.4 dB
1721 else if (snr <= 7542 ) level = 5; // SNR <= 3.0 dB
1722 else if (snr <= 8659 ) level = 6; // SNR <= 3.6 dB
1723 else if (snr <= 9942 ) level = 7; // SNR <= 4.2 dB
1724 else if (snr <= 11415 ) level = 8; // SNR <= 4.8 dB
1725 else if (snr <= 13107 ) level = 9; // SNR <= 5.4 dB
1726 else if (snr <= 15048 ) level = 10; // SNR <= 6.0 dB
1727 else if (snr <= 17278 ) level = 11; // SNR <= 6.6 dB
1728 else if (snr <= 19838 ) level = 12; // SNR <= 7.2 dB
1729 else if (snr <= 22777 ) level = 13; // SNR <= 7.8 dB
1730 else if (snr <= 26151 ) level = 14; // SNR <= 8.4 dB
1731 else if (snr <= 30026 ) level = 15; // SNR <= 9.0 dB
1732 else if (snr <= 34474 ) level = 16; // SNR <= 9.6 dB
1733 else if (snr <= 39581 ) level = 17; // SNR <= 10.2 dB
1734 else if (snr <= 45446 ) level = 18; // SNR <= 10.8 dB
1735 else if (snr <= 52179 ) level = 19; // SNR <= 11.4 dB
1736 else if (snr <= 59909 ) level = 20; // SNR <= 12.0 dB
1737 else if (snr <= 68785 ) level = 21; // SNR <= 12.6 dB
1738 else if (snr <= 78975 ) level = 22; // SNR <= 13.2 dB
1739 else if (snr <= 90676 ) level = 23; // SNR <= 13.8 dB
1740 else if (snr <= 104110 ) level = 24; // SNR <= 14.4 dB
1741 else if (snr <= 119534 ) level = 25; // SNR <= 15.0 dB
1742 else if (snr <= 137244 ) level = 26; // SNR <= 15.6 dB
1743 else if (snr <= 157577 ) level = 27; // SNR <= 16.2 dB
1744 else if (snr <= 180922 ) level = 28; // SNR <= 16.8 dB
1745 else if (snr <= 207726 ) level = 29; // SNR <= 17.4 dB
1746 else if (snr <= 238502 ) level = 30; // SNR <= 18.0 dB
1747 else if (snr <= 273837 ) level = 31; // SNR <= 18.6 dB
1748 else if (snr <= 314407 ) level = 32; // SNR <= 19.2 dB
1749 else if (snr <= 360987 ) level = 33; // SNR <= 19.8 dB
1750 else if (snr <= 414469 ) level = 34; // SNR <= 20.4 dB
1751 else if (snr <= 475874 ) level = 35; // SNR <= 21.0 dB
1752 else if (snr <= 546376 ) level = 36; // SNR <= 21.6 dB
1753 else if (snr <= 627324 ) level = 37; // SNR <= 22.2 dB
1754 else if (snr <= 720264 ) level = 38; // SNR <= 22.8 dB
1755 else if (snr <= 826974 ) level = 39; // SNR <= 23.4 dB
1756 else if (snr <= 949493 ) level = 40; // SNR <= 24.0 dB
1757 else if (snr <= 1090164) level = 41; // SNR <= 24.6 dB
1758 else if (snr <= 1251676) level = 42; // SNR <= 25.2 dB
1759 else if (snr <= 1437116) level = 43; // SNR <= 25.8 dB
1760 else if (snr <= 1650030) level = 44; // SNR <= 26.4 dB
1761 else if (snr <= 1894488) level = 45; // SNR <= 27.0 dB
1762 else if (snr <= 2175163) level = 46; // SNR <= 27.6 dB
1763 else if (snr <= 2497421) level = 47; // SNR <= 28.2 dB
1764 else if (snr <= 2867423) level = 48; // SNR <= 28.8 dB
1765 else if (snr <= 3292242) level = 49; // SNR <= 29.4 dB
1766 else if (snr > 3292242) level = 50; // SNR <= 30.0 dB
1767 }
1768 }
1769 else
1770 {
1771 level = 0;
1772 }
1773
1774 return level*2;
1775 }
1776
1777 #ifdef UTPA2
_HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 * pBitErr,MS_U16 * pError_window)1778 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(MS_U32 *pBitErr, MS_U16 *pError_window)
1779 #else
1780 static MS_BOOL _HAL_INTERN_DTMB_GetPreLdpcBer(float *pber)
1781 #endif
1782 {
1783 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1784 DMD_DTMB_ResData *pRes = psDMD_DTMB_ResData + u8DMD_DTMB_DMD_ID;
1785 #endif
1786
1787 MS_U8 u8Data=0;
1788 MS_U32 BitErr;
1789 MS_U16 error_window;
1790
1791 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1792 if (pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1793 {
1794 _MBX_ReadReg(0x3F3B, &u8Data);
1795 BitErr = u8Data;
1796 _MBX_ReadReg(0x3F3A, &u8Data);
1797 BitErr = (BitErr << 8)|u8Data;
1798 _MBX_ReadReg(0x3F39, &u8Data);
1799 BitErr = (BitErr << 8)|u8Data;
1800 _MBX_ReadReg(0x3F38, &u8Data);
1801 BitErr = (BitErr << 8)|u8Data;
1802 }
1803 else
1804 {
1805 _MBX_ReadReg(0x263B, &u8Data);
1806 BitErr = u8Data;
1807 _MBX_ReadReg(0x263A, &u8Data);
1808 BitErr = (BitErr << 8)|u8Data;
1809 _MBX_ReadReg(0x2639, &u8Data);
1810 BitErr = (BitErr << 8)|u8Data;
1811 _MBX_ReadReg(0x2638, &u8Data);
1812 BitErr = (BitErr << 8)|u8Data;
1813 }
1814 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1815 _MBX_ReadReg(0x2D3B, &u8Data);
1816 BitErr = u8Data;
1817 _MBX_ReadReg(0x2D3A, &u8Data);
1818 BitErr = (BitErr << 8)|u8Data;
1819 _MBX_ReadReg(0x2D39, &u8Data);
1820 BitErr = (BitErr << 8)|u8Data;
1821 _MBX_ReadReg(0x2D38, &u8Data);
1822 BitErr = (BitErr << 8)|u8Data;
1823 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1824 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1825 _MBX_ReadReg(0x163B, &u8Data);
1826 BitErr = u8Data;
1827 _MBX_ReadReg(0x163A, &u8Data);
1828 BitErr = (BitErr << 8)|u8Data;
1829 _MBX_ReadReg(0x1639, &u8Data);
1830 BitErr = (BitErr << 8)|u8Data;
1831 _MBX_ReadReg(0x1638, &u8Data);
1832 BitErr = (BitErr << 8)|u8Data;
1833 #else
1834 _MBX_ReadReg(0x3F3B, &u8Data);
1835 BitErr = u8Data;
1836 _MBX_ReadReg(0x3F3A, &u8Data);
1837 BitErr = (BitErr << 8)|u8Data;
1838 _MBX_ReadReg(0x3F39, &u8Data);
1839 BitErr = (BitErr << 8)|u8Data;
1840 _MBX_ReadReg(0x3F38, &u8Data);
1841 BitErr = (BitErr << 8)|u8Data;
1842 #endif
1843 #else
1844 _MBX_ReadReg(0x263B, &u8Data);
1845 BitErr = u8Data;
1846 _MBX_ReadReg(0x263A, &u8Data);
1847 BitErr = (BitErr << 8)|u8Data;
1848 _MBX_ReadReg(0x2639, &u8Data);
1849 BitErr = (BitErr << 8)|u8Data;
1850 _MBX_ReadReg(0x2638, &u8Data);
1851 BitErr = (BitErr << 8)|u8Data;
1852 #endif
1853
1854 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_NASA)
1855 if(pRes->sDMD_DTMB_PriData.u16ChipID == DMD_DTMB_CHIP_ID_WALTZ)
1856 {
1857 _MBX_ReadReg(0x3F2F, &u8Data);
1858 error_window = u8Data;
1859 _MBX_ReadReg(0x3F2E, &u8Data);
1860 error_window = (error_window << 8)|u8Data;
1861 }
1862 else
1863 {
1864 _MBX_ReadReg(0x262F, &u8Data);
1865 error_window = u8Data;
1866 _MBX_ReadReg(0x262E, &u8Data);
1867 error_window = (error_window << 8)|u8Data;
1868 }
1869 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MADISON)
1870 _MBX_ReadReg(0x2D2F, &u8Data);
1871 error_window = u8Data;
1872 _MBX_ReadReg(0x2D2E, &u8Data);
1873 error_window = (error_window << 8)|u8Data;
1874 #elif (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MONACO || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MUJI || DMD_DTMB_CHIP_VERSION >= DMD_DTMB_CHIP_MONET)
1875 #if (DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MACAN || DMD_DTMB_CHIP_VERSION == DMD_DTMB_CHIP_MASERATI)
1876 _MBX_ReadReg(0x162F, &u8Data);
1877 error_window = u8Data;
1878 _MBX_ReadReg(0x162E, &u8Data);
1879 error_window = (error_window << 8)|u8Data;
1880 #else
1881 _MBX_ReadReg(0x3F2F, &u8Data);
1882 error_window = u8Data;
1883 _MBX_ReadReg(0x3F2E, &u8Data);
1884 error_window = (error_window << 8)|u8Data;
1885 #endif
1886 #else
1887 _MBX_ReadReg(0x262F, &u8Data);
1888 error_window = u8Data;
1889 _MBX_ReadReg(0x262E, &u8Data);
1890 error_window = (error_window << 8)|u8Data;
1891 #endif
1892
1893 #ifdef UTPA2
1894 *pBitErr = BitErr;
1895 *pError_window = error_window;
1896 #else
1897 *pber=(float)BitErr/7488.0/(float)error_window;
1898 #endif
1899
1900 return TRUE;
1901 }
1902
_HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)1903 static MS_BOOL _HAL_INTERN_DTMB_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
1904 {
1905 return _MBX_ReadReg(u16Addr, pu8Data);
1906 }
1907
_HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr,MS_U8 u8Data)1908 static MS_BOOL _HAL_INTERN_DTMB_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
1909 {
1910 return _MBX_WriteReg(u16Addr, u8Data);
1911 }
1912
1913 //-------------------------------------------------------------------------------------------------
1914 // Global Functions
1915 //-------------------------------------------------------------------------------------------------
HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd,void * pArgs)1916 MS_BOOL HAL_INTERN_DTMB_IOCTL_CMD(DMD_DTMB_HAL_COMMAND eCmd, void *pArgs)
1917 {
1918 MS_BOOL bResult = TRUE;
1919
1920 switch(eCmd)
1921 {
1922 case DMD_DTMB_HAL_CMD_Exit:
1923 bResult = _HAL_INTERN_DTMB_Exit();
1924 break;
1925 case DMD_DTMB_HAL_CMD_InitClk:
1926 _HAL_INTERN_DTMB_InitClk();
1927 break;
1928 case DMD_DTMB_HAL_CMD_Download:
1929 bResult = _HAL_INTERN_DTMB_Download();
1930 break;
1931 case DMD_DTMB_HAL_CMD_FWVERSION:
1932 _HAL_INTERN_DTMB_FWVERSION();
1933 break;
1934 case DMD_DTMB_HAL_CMD_SoftReset:
1935 bResult = _HAL_INTERN_DTMB_SoftReset();
1936 break;
1937 case DMD_DTMB_HAL_CMD_SetACICoef:
1938 bResult = _HAL_INTERN_DTMB_SetACICoef();
1939 break;
1940 case DMD_DTMB_HAL_CMD_SetDTMBMode:
1941 bResult = _HAL_INTERN_DTMB_SetDtmbMode();
1942 break;
1943 case DMD_DTMB_HAL_CMD_SetModeClean:
1944 bResult = _HAL_INTERN_DTMB_SetModeClean();
1945 break;
1946 case DMD_DTMB_HAL_CMD_Set_QAM_SR:
1947 bResult = _HAL_INTERN_DTMB_Set_QAM_SR();
1948 break;
1949 case DMD_DTMB_HAL_CMD_Active:
1950 break;
1951 case DMD_DTMB_HAL_CMD_AGCLock:
1952 bResult = _HAL_INTERN_DTMB_AGCLock();
1953 break;
1954 case DMD_DTMB_HAL_CMD_DTMB_PNP_Lock:
1955 bResult = _HAL_INTERN_DTMB_PNP_Lock();
1956 break;
1957 case DMD_DTMB_HAL_CMD_DTMB_FEC_Lock:
1958 bResult = _HAL_INTERN_DTMB_FEC_Lock();
1959 break;
1960 case DMD_DTMB_HAL_CMD_DVBC_PreLock:
1961 break;
1962 case DMD_DTMB_HAL_CMD_DVBC_Main_Lock:
1963 break;
1964 case DMD_DTMB_HAL_CMD_GetModulation:
1965 bResult = _HAL_INTERN_DTMB_GetModulation((DMD_DTMB_MODULATION_INFO *)pArgs);
1966 case DMD_DTMB_HAL_CMD_ReadIFAGC:
1967 *((MS_U16 *)pArgs) = _HAL_INTERN_DTMB_ReadIFAGC();
1968 break;
1969 case DMD_DTMB_HAL_CMD_ReadFrequencyOffset:
1970 #ifdef UTPA2
1971 bResult = _HAL_INTERN_DTMB_ReadFrequencyOffset(&((*((DMD_DTMB_CFO_DATA *)pArgs)).fftfirstCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).fftSecondCfo), &((*((DMD_DTMB_CFO_DATA *)pArgs)).sr));
1972 #else
1973 *((MS_S16 *)pArgs) = _HAL_INTERN_DTMB_ReadFrequencyOffset();
1974 #endif
1975 break;
1976 case DMD_DTMB_HAL_CMD_ReadSNRPercentage:
1977 *((MS_U8 *)pArgs) = _HAL_INTERN_DTMB_ReadSNRPercentage();
1978 break;
1979 case DMD_DTMB_HAL_CMD_GetPreLdpcBer:
1980 #ifdef UTPA2
1981 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer(&((*((DMD_DTMB_BER_DATA *)pArgs)).BitErr), &((*((DMD_DTMB_BER_DATA *)pArgs)).Error_window));
1982 #else
1983 bResult = _HAL_INTERN_DTMB_GetPreLdpcBer((float *)pArgs);
1984 #endif
1985 break;
1986 case DMD_DTMB_HAL_CMD_GetPreViterbiBer:
1987 break;
1988 case DMD_DTMB_HAL_CMD_GetPostViterbiBer:
1989 break;
1990 // case DMD_DTMB_HAL_CMD_GetSNR:
1991 // break;
1992 case DMD_DTMB_HAL_CMD_TS_INTERFACE_CONFIG:
1993 break;
1994 case DMD_DTMB_HAL_CMD_IIC_Bypass_Mode:
1995 break;
1996 case DMD_DTMB_HAL_CMD_SSPI_TO_GPIO:
1997 break;
1998 case DMD_DTMB_HAL_CMD_GPIO_GET_LEVEL:
1999 break;
2000 case DMD_DTMB_HAL_CMD_GPIO_SET_LEVEL:
2001 break;
2002 case DMD_DTMB_HAL_CMD_GPIO_OUT_ENABLE:
2003 break;
2004 // case DMD_DTMB_HAL_CMD_DoIQSwap:
2005 // break;
2006 case DMD_DTMB_HAL_CMD_GET_REG:
2007 bResult = _HAL_INTERN_DTMB_GetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, &((*((DMD_DTMB_REG_DATA *)pArgs)).u8Data));
2008 break;
2009 case DMD_DTMB_HAL_CMD_SET_REG:
2010 bResult = _HAL_INTERN_DTMB_SetReg((*((DMD_DTMB_REG_DATA *)pArgs)).u16Addr, (*((DMD_DTMB_REG_DATA *)pArgs)).u8Data);
2011 break;
2012 default:
2013 break;
2014 }
2015
2016 return bResult;
2017 }
2018
MDrv_DMD_DTMB_Initial_Hal_Interface(void)2019 MS_BOOL MDrv_DMD_DTMB_Initial_Hal_Interface(void)
2020 {
2021 return TRUE;
2022 }
2023
2024