| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-pll.c | 439 u32 con0, con1; in samsung_pll45xx_set_rate() local
450 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
453 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
455 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); in samsung_pll45xx_set_rate()
456 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; in samsung_pll45xx_set_rate()
457 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
463 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
466 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | in samsung_pll45xx_set_rate()
489 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
590 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
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| /OK3568_Linux_fs/kernel/drivers/pwm/ |
| H A D | pwm-mtk-disp.c | 32 unsigned int con0; member
111 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_config()
226 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_probe()
254 .con0 = 0xa8,
264 .con0 = 0x10,
274 .con0 = 0x18,
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/ |
| H A D | clk-regmap-pll.c | 70 unsigned int con0, con1, con2; in clk_regmap_pll_recalc_rate() local
73 regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(0), &con0); in clk_regmap_pll_recalc_rate()
77 bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT; in clk_regmap_pll_recalc_rate()
78 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in clk_regmap_pll_recalc_rate()
79 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in clk_regmap_pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/misc/rk628/ |
| H A D | rk628_cru.c | 64 u32 con0, con1, con2; in rk628_cru_clk_get_rate_pll() local
85 rk628_i2c_read(rk628, offset + CRU_CPLL_CON0, &con0); in rk628_cru_clk_get_rate_pll()
89 bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT; in rk628_cru_clk_get_rate_pll()
90 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rk628_cru_clk_get_rate_pll()
91 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
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| /OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/ |
| H A D | rk628_cru.c | 65 u32 con0, con1, con2; in rk628_cru_clk_get_rate_pll() local
86 rk628_i2c_read(rk628, offset + CRU_CPLL_CON0, &con0); in rk628_cru_clk_get_rate_pll()
90 bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT; in rk628_cru_clk_get_rate_pll()
91 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rk628_cru_clk_get_rate_pll()
92 fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 488 u32 con0, u32 con1) in rockchip_rk3036_pll_con_to_rate() argument
493 fbdiv = ((con0 >> RK3036_PLLCON0_FBDIV_SHIFT) & in rockchip_rk3036_pll_con_to_rate()
495 postdiv1 = ((con0 >> RK3036_PLLCON0_POSTDIV1_SHIFT) & in rockchip_rk3036_pll_con_to_rate()
1784 u32 con0, u32 con1) in rockchip_pll_con_to_rate() argument
1789 return rockchip_rk3036_pll_con_to_rate(pll, con0, con1); in rockchip_pll_con_to_rate()
1805 u32 value, con0, con1; in rockchip_boost_init() local
1821 if (!of_property_read_u32(np, "rockchip,boost-low-con0", &con0) && in rockchip_boost_init()
1823 pr_debug("boost-low-con=0x%x 0x%x\n", con0, con1); in rockchip_boost_init()
1825 HIWORD_UPDATE(con0, BOOST_PLL_CON_MASK, 0)); in rockchip_boost_init()
1828 pll->boost_low_rate = rockchip_pll_con_to_rate(pll, con0, in rockchip_boost_init()
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
121 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
129 con0 = readl(&pll->con0); in rkclk_pll_get_rate()
131 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; in rkclk_pll_get_rate()
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| H A D | clk_rk3066.c | 125 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
267 con = readl(&pll->con0); in rkclk_pll_get_rate()
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| H A D | clk_rk3188.c | 123 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
265 con = readl(&pll->con0); in rkclk_pll_get_rate()
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| H A D | clk_rk3036.c | 85 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
229 con = readl(&pll->con0); in rkclk_pll_get_rate()
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3188.h | 41 u32 con0; member
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| H A D | cru_rk3066.h | 41 u32 con0; member
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| H A D | sdram_rk3308.h | 21 u32 con0; member
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| H A D | cru_rk3368.h | 31 unsigned int con0; member
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| H A D | cru_rk3128.h | 34 unsigned int con0; member
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| H A D | cru_rk3036.h | 40 unsigned int con0; member
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| H A D | cru_rk322x.h | 33 unsigned int con0; member
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| H A D | cru_rv1108.h | 28 unsigned int con0; member
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| H A D | cru_rk3288.h | 44 u32 con0; member
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| H A D | cru_rv1106.h | 56 unsigned int con0; member
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| H A D | cru_rk1808.h | 49 unsigned int con0; member
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| H A D | cru_rk3528.h | 49 unsigned int con0; member
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| H A D | cru_rv1126.h | 82 unsigned int con0; member
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| H A D | cru_px30.h | 58 unsigned int con0; member
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/ |
| H A D | pxa168fb.h | 357 #define CFG_COS0(con0) (con0) argument
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