1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __PXA168FB_H__ 3*4882a593Smuzhiyun #define __PXA168FB_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* ------------< LCD register >------------ */ 6*4882a593Smuzhiyun /* Video Frame 0&1 start address registers */ 7*4882a593Smuzhiyun #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 8*4882a593Smuzhiyun #define LCD_SPU_DMA_START_ADDR_U0 0x00C4 9*4882a593Smuzhiyun #define LCD_SPU_DMA_START_ADDR_V0 0x00C8 10*4882a593Smuzhiyun #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */ 11*4882a593Smuzhiyun #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0 12*4882a593Smuzhiyun #define LCD_SPU_DMA_START_ADDR_U1 0x00D4 13*4882a593Smuzhiyun #define LCD_SPU_DMA_START_ADDR_V1 0x00D8 14*4882a593Smuzhiyun #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* YC & UV Pitch */ 17*4882a593Smuzhiyun #define LCD_SPU_DMA_PITCH_YC 0x00E0 18*4882a593Smuzhiyun #define SPU_DMA_PITCH_C(c) ((c) << 16) 19*4882a593Smuzhiyun #define SPU_DMA_PITCH_Y(y) (y) 20*4882a593Smuzhiyun #define LCD_SPU_DMA_PITCH_UV 0x00E4 21*4882a593Smuzhiyun #define SPU_DMA_PITCH_V(v) ((v) << 16) 22*4882a593Smuzhiyun #define SPU_DMA_PITCH_U(u) (u) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Video Starting Point on Screen Register */ 25*4882a593Smuzhiyun #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8 26*4882a593Smuzhiyun #define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */ 27*4882a593Smuzhiyun #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Video Size Register */ 30*4882a593Smuzhiyun #define LCD_SPU_DMA_HPXL_VLN 0x00EC 31*4882a593Smuzhiyun #define CFG_DMA_VLN(y) ((y) << 16) 32*4882a593Smuzhiyun #define CFG_DMA_HPXL(x) (x) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Video Size After zooming Register */ 35*4882a593Smuzhiyun #define LCD_SPU_DZM_HPXL_VLN 0x00F0 36*4882a593Smuzhiyun #define CFG_DZM_VLN(y) ((y) << 16) 37*4882a593Smuzhiyun #define CFG_DZM_HPXL(x) (x) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Graphic Frame 0&1 Starting Address Register */ 40*4882a593Smuzhiyun #define LCD_CFG_GRA_START_ADDR0 0x00F4 41*4882a593Smuzhiyun #define LCD_CFG_GRA_START_ADDR1 0x00F8 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Graphic Frame Pitch */ 44*4882a593Smuzhiyun #define LCD_CFG_GRA_PITCH 0x00FC 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Graphic Starting Point on Screen Register */ 47*4882a593Smuzhiyun #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100 48*4882a593Smuzhiyun #define CFG_GRA_OVSA_VLN(y) ((y) << 16) 49*4882a593Smuzhiyun #define CFG_GRA_OVSA_HPXL(x) (x) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Graphic Size Register */ 52*4882a593Smuzhiyun #define LCD_SPU_GRA_HPXL_VLN 0x0104 53*4882a593Smuzhiyun #define CFG_GRA_VLN(y) ((y) << 16) 54*4882a593Smuzhiyun #define CFG_GRA_HPXL(x) (x) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Graphic Size after Zooming Register */ 57*4882a593Smuzhiyun #define LCD_SPU_GZM_HPXL_VLN 0x0108 58*4882a593Smuzhiyun #define CFG_GZM_VLN(y) ((y) << 16) 59*4882a593Smuzhiyun #define CFG_GZM_HPXL(x) (x) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* HW Cursor Starting Point on Screen Register */ 62*4882a593Smuzhiyun #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C 63*4882a593Smuzhiyun #define CFG_HWC_OVSA_VLN(y) ((y) << 16) 64*4882a593Smuzhiyun #define CFG_HWC_OVSA_HPXL(x) (x) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* HW Cursor Size */ 67*4882a593Smuzhiyun #define LCD_SPU_HWC_HPXL_VLN 0x0110 68*4882a593Smuzhiyun #define CFG_HWC_VLN(y) ((y) << 16) 69*4882a593Smuzhiyun #define CFG_HWC_HPXL(x) (x) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Total Screen Size Register */ 72*4882a593Smuzhiyun #define LCD_SPUT_V_H_TOTAL 0x0114 73*4882a593Smuzhiyun #define CFG_V_TOTAL(y) ((y) << 16) 74*4882a593Smuzhiyun #define CFG_H_TOTAL(x) (x) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Total Screen Active Size Register */ 77*4882a593Smuzhiyun #define LCD_SPU_V_H_ACTIVE 0x0118 78*4882a593Smuzhiyun #define CFG_V_ACTIVE(y) ((y) << 16) 79*4882a593Smuzhiyun #define CFG_H_ACTIVE(x) (x) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Screen H&V Porch Register */ 82*4882a593Smuzhiyun #define LCD_SPU_H_PORCH 0x011C 83*4882a593Smuzhiyun #define CFG_H_BACK_PORCH(b) ((b) << 16) 84*4882a593Smuzhiyun #define CFG_H_FRONT_PORCH(f) (f) 85*4882a593Smuzhiyun #define LCD_SPU_V_PORCH 0x0120 86*4882a593Smuzhiyun #define CFG_V_BACK_PORCH(b) ((b) << 16) 87*4882a593Smuzhiyun #define CFG_V_FRONT_PORCH(f) (f) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Screen Blank Color Register */ 90*4882a593Smuzhiyun #define LCD_SPU_BLANKCOLOR 0x0124 91*4882a593Smuzhiyun #define CFG_BLANKCOLOR_MASK 0x00FFFFFF 92*4882a593Smuzhiyun #define CFG_BLANKCOLOR_R_MASK 0x000000FF 93*4882a593Smuzhiyun #define CFG_BLANKCOLOR_G_MASK 0x0000FF00 94*4882a593Smuzhiyun #define CFG_BLANKCOLOR_B_MASK 0x00FF0000 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* HW Cursor Color 1&2 Register */ 97*4882a593Smuzhiyun #define LCD_SPU_ALPHA_COLOR1 0x0128 98*4882a593Smuzhiyun #define CFG_HWC_COLOR1 0x00FFFFFF 99*4882a593Smuzhiyun #define CFG_HWC_COLOR1_R(red) ((red) << 16) 100*4882a593Smuzhiyun #define CFG_HWC_COLOR1_G(green) ((green) << 8) 101*4882a593Smuzhiyun #define CFG_HWC_COLOR1_B(blue) (blue) 102*4882a593Smuzhiyun #define CFG_HWC_COLOR1_R_MASK 0x000000FF 103*4882a593Smuzhiyun #define CFG_HWC_COLOR1_G_MASK 0x0000FF00 104*4882a593Smuzhiyun #define CFG_HWC_COLOR1_B_MASK 0x00FF0000 105*4882a593Smuzhiyun #define LCD_SPU_ALPHA_COLOR2 0x012C 106*4882a593Smuzhiyun #define CFG_HWC_COLOR2 0x00FFFFFF 107*4882a593Smuzhiyun #define CFG_HWC_COLOR2_R_MASK 0x000000FF 108*4882a593Smuzhiyun #define CFG_HWC_COLOR2_G_MASK 0x0000FF00 109*4882a593Smuzhiyun #define CFG_HWC_COLOR2_B_MASK 0x00FF0000 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Video YUV Color Key Control */ 112*4882a593Smuzhiyun #define LCD_SPU_COLORKEY_Y 0x0130 113*4882a593Smuzhiyun #define CFG_CKEY_Y2(y2) ((y2) << 24) 114*4882a593Smuzhiyun #define CFG_CKEY_Y2_MASK 0xFF000000 115*4882a593Smuzhiyun #define CFG_CKEY_Y1(y1) ((y1) << 16) 116*4882a593Smuzhiyun #define CFG_CKEY_Y1_MASK 0x00FF0000 117*4882a593Smuzhiyun #define CFG_CKEY_Y(y) ((y) << 8) 118*4882a593Smuzhiyun #define CFG_CKEY_Y_MASK 0x0000FF00 119*4882a593Smuzhiyun #define CFG_ALPHA_Y(y) (y) 120*4882a593Smuzhiyun #define CFG_ALPHA_Y_MASK 0x000000FF 121*4882a593Smuzhiyun #define LCD_SPU_COLORKEY_U 0x0134 122*4882a593Smuzhiyun #define CFG_CKEY_U2(u2) ((u2) << 24) 123*4882a593Smuzhiyun #define CFG_CKEY_U2_MASK 0xFF000000 124*4882a593Smuzhiyun #define CFG_CKEY_U1(u1) ((u1) << 16) 125*4882a593Smuzhiyun #define CFG_CKEY_U1_MASK 0x00FF0000 126*4882a593Smuzhiyun #define CFG_CKEY_U(u) ((u) << 8) 127*4882a593Smuzhiyun #define CFG_CKEY_U_MASK 0x0000FF00 128*4882a593Smuzhiyun #define CFG_ALPHA_U(u) (u) 129*4882a593Smuzhiyun #define CFG_ALPHA_U_MASK 0x000000FF 130*4882a593Smuzhiyun #define LCD_SPU_COLORKEY_V 0x0138 131*4882a593Smuzhiyun #define CFG_CKEY_V2(v2) ((v2) << 24) 132*4882a593Smuzhiyun #define CFG_CKEY_V2_MASK 0xFF000000 133*4882a593Smuzhiyun #define CFG_CKEY_V1(v1) ((v1) << 16) 134*4882a593Smuzhiyun #define CFG_CKEY_V1_MASK 0x00FF0000 135*4882a593Smuzhiyun #define CFG_CKEY_V(v) ((v) << 8) 136*4882a593Smuzhiyun #define CFG_CKEY_V_MASK 0x0000FF00 137*4882a593Smuzhiyun #define CFG_ALPHA_V(v) (v) 138*4882a593Smuzhiyun #define CFG_ALPHA_V_MASK 0x000000FF 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* SPI Read Data Register */ 141*4882a593Smuzhiyun #define LCD_SPU_SPI_RXDATA 0x0140 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* Smart Panel Read Data Register */ 144*4882a593Smuzhiyun #define LCD_SPU_ISA_RSDATA 0x0144 145*4882a593Smuzhiyun #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF 146*4882a593Smuzhiyun #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00 147*4882a593Smuzhiyun #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000 148*4882a593Smuzhiyun #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000 149*4882a593Smuzhiyun #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* HWC SRAM Read Data Register */ 152*4882a593Smuzhiyun #define LCD_SPU_HWC_RDDAT 0x0158 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Gamma Table SRAM Read Data Register */ 155*4882a593Smuzhiyun #define LCD_SPU_GAMMA_RDDAT 0x015c 156*4882a593Smuzhiyun #define CFG_GAMMA_RDDAT_MASK 0x000000FF 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Palette Table SRAM Read Data Register */ 159*4882a593Smuzhiyun #define LCD_SPU_PALETTE_RDDAT 0x0160 160*4882a593Smuzhiyun #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* I/O Pads Input Read Only Register */ 163*4882a593Smuzhiyun #define LCD_SPU_IOPAD_IN 0x0178 164*4882a593Smuzhiyun #define CFG_IOPAD_IN_MASK 0x0FFFFFFF 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* Reserved Read Only Registers */ 167*4882a593Smuzhiyun #define LCD_CFG_RDREG5F 0x017C 168*4882a593Smuzhiyun #define IRE_FRAME_CNT_MASK 0x000000C0 169*4882a593Smuzhiyun #define IPE_FRAME_CNT_MASK 0x00000030 170*4882a593Smuzhiyun #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */ 171*4882a593Smuzhiyun #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */ 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /* SPI Control Register. */ 174*4882a593Smuzhiyun #define LCD_SPU_SPI_CTRL 0x0180 175*4882a593Smuzhiyun #define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */ 176*4882a593Smuzhiyun #define CFG_SCLKCNT_MASK 0xFF000000 177*4882a593Smuzhiyun #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */ 178*4882a593Smuzhiyun #define CFG_RXBITS_MASK 0x00FF0000 179*4882a593Smuzhiyun #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */ 180*4882a593Smuzhiyun #define CFG_TXBITS_MASK 0x0000FF00 181*4882a593Smuzhiyun #define CFG_CLKINV(clk) ((clk) << 7) 182*4882a593Smuzhiyun #define CFG_CLKINV_MASK 0x00000080 183*4882a593Smuzhiyun #define CFG_KEEPXFER(transfer) ((transfer) << 6) 184*4882a593Smuzhiyun #define CFG_KEEPXFER_MASK 0x00000040 185*4882a593Smuzhiyun #define CFG_RXBITSTO0(rx) ((rx) << 5) 186*4882a593Smuzhiyun #define CFG_RXBITSTO0_MASK 0x00000020 187*4882a593Smuzhiyun #define CFG_TXBITSTO0(tx) ((tx) << 4) 188*4882a593Smuzhiyun #define CFG_TXBITSTO0_MASK 0x00000010 189*4882a593Smuzhiyun #define CFG_SPI_ENA(spi) ((spi) << 3) 190*4882a593Smuzhiyun #define CFG_SPI_ENA_MASK 0x00000008 191*4882a593Smuzhiyun #define CFG_SPI_SEL(spi) ((spi) << 2) 192*4882a593Smuzhiyun #define CFG_SPI_SEL_MASK 0x00000004 193*4882a593Smuzhiyun #define CFG_SPI_3W4WB(wire) ((wire) << 1) 194*4882a593Smuzhiyun #define CFG_SPI_3W4WB_MASK 0x00000002 195*4882a593Smuzhiyun #define CFG_SPI_START(start) (start) 196*4882a593Smuzhiyun #define CFG_SPI_START_MASK 0x00000001 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* SPI Tx Data Register */ 199*4882a593Smuzhiyun #define LCD_SPU_SPI_TXDATA 0x0184 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* 202*4882a593Smuzhiyun 1. Smart Pannel 8-bit Bus Control Register. 203*4882a593Smuzhiyun 2. AHB Slave Path Data Port Register 204*4882a593Smuzhiyun */ 205*4882a593Smuzhiyun #define LCD_SPU_SMPN_CTRL 0x0188 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* DMA Control 0 Register */ 208*4882a593Smuzhiyun #define LCD_SPU_DMA_CTRL0 0x0190 209*4882a593Smuzhiyun #define CFG_NOBLENDING(nb) ((nb) << 31) 210*4882a593Smuzhiyun #define CFG_NOBLENDING_MASK 0x80000000 211*4882a593Smuzhiyun #define CFG_GAMMA_ENA(gn) ((gn) << 30) 212*4882a593Smuzhiyun #define CFG_GAMMA_ENA_MASK 0x40000000 213*4882a593Smuzhiyun #define CFG_CBSH_ENA(cn) ((cn) << 29) 214*4882a593Smuzhiyun #define CFG_CBSH_ENA_MASK 0x20000000 215*4882a593Smuzhiyun #define CFG_PALETTE_ENA(pn) ((pn) << 28) 216*4882a593Smuzhiyun #define CFG_PALETTE_ENA_MASK 0x10000000 217*4882a593Smuzhiyun #define CFG_ARBFAST_ENA(an) ((an) << 27) 218*4882a593Smuzhiyun #define CFG_ARBFAST_ENA_MASK 0x08000000 219*4882a593Smuzhiyun #define CFG_HWC_1BITMOD(mode) ((mode) << 26) 220*4882a593Smuzhiyun #define CFG_HWC_1BITMOD_MASK 0x04000000 221*4882a593Smuzhiyun #define CFG_HWC_1BITENA(mn) ((mn) << 25) 222*4882a593Smuzhiyun #define CFG_HWC_1BITENA_MASK 0x02000000 223*4882a593Smuzhiyun #define CFG_HWC_ENA(cn) ((cn) << 24) 224*4882a593Smuzhiyun #define CFG_HWC_ENA_MASK 0x01000000 225*4882a593Smuzhiyun #define CFG_DMAFORMAT(dmaformat) ((dmaformat) << 20) 226*4882a593Smuzhiyun #define CFG_DMAFORMAT_MASK 0x00F00000 227*4882a593Smuzhiyun #define CFG_GRAFORMAT(graformat) ((graformat) << 16) 228*4882a593Smuzhiyun #define CFG_GRAFORMAT_MASK 0x000F0000 229*4882a593Smuzhiyun /* for graphic part */ 230*4882a593Smuzhiyun #define CFG_GRA_FTOGGLE(toggle) ((toggle) << 15) 231*4882a593Smuzhiyun #define CFG_GRA_FTOGGLE_MASK 0x00008000 232*4882a593Smuzhiyun #define CFG_GRA_HSMOOTH(smooth) ((smooth) << 14) 233*4882a593Smuzhiyun #define CFG_GRA_HSMOOTH_MASK 0x00004000 234*4882a593Smuzhiyun #define CFG_GRA_TSTMODE(test) ((test) << 13) 235*4882a593Smuzhiyun #define CFG_GRA_TSTMODE_MASK 0x00002000 236*4882a593Smuzhiyun #define CFG_GRA_SWAPRB(swap) ((swap) << 12) 237*4882a593Smuzhiyun #define CFG_GRA_SWAPRB_MASK 0x00001000 238*4882a593Smuzhiyun #define CFG_GRA_SWAPUV(swap) ((swap) << 11) 239*4882a593Smuzhiyun #define CFG_GRA_SWAPUV_MASK 0x00000800 240*4882a593Smuzhiyun #define CFG_GRA_SWAPYU(swap) ((swap) << 10) 241*4882a593Smuzhiyun #define CFG_GRA_SWAPYU_MASK 0x00000400 242*4882a593Smuzhiyun #define CFG_YUV2RGB_GRA(cvrt) ((cvrt) << 9) 243*4882a593Smuzhiyun #define CFG_YUV2RGB_GRA_MASK 0x00000200 244*4882a593Smuzhiyun #define CFG_GRA_ENA(gra) ((gra) << 8) 245*4882a593Smuzhiyun #define CFG_GRA_ENA_MASK 0x00000100 246*4882a593Smuzhiyun /* for video part */ 247*4882a593Smuzhiyun #define CFG_DMA_FTOGGLE(toggle) ((toggle) << 7) 248*4882a593Smuzhiyun #define CFG_DMA_FTOGGLE_MASK 0x00000080 249*4882a593Smuzhiyun #define CFG_DMA_HSMOOTH(smooth) ((smooth) << 6) 250*4882a593Smuzhiyun #define CFG_DMA_HSMOOTH_MASK 0x00000040 251*4882a593Smuzhiyun #define CFG_DMA_TSTMODE(test) ((test) << 5) 252*4882a593Smuzhiyun #define CFG_DMA_TSTMODE_MASK 0x00000020 253*4882a593Smuzhiyun #define CFG_DMA_SWAPRB(swap) ((swap) << 4) 254*4882a593Smuzhiyun #define CFG_DMA_SWAPRB_MASK 0x00000010 255*4882a593Smuzhiyun #define CFG_DMA_SWAPUV(swap) ((swap) << 3) 256*4882a593Smuzhiyun #define CFG_DMA_SWAPUV_MASK 0x00000008 257*4882a593Smuzhiyun #define CFG_DMA_SWAPYU(swap) ((swap) << 2) 258*4882a593Smuzhiyun #define CFG_DMA_SWAPYU_MASK 0x00000004 259*4882a593Smuzhiyun #define CFG_DMA_SWAP_MASK 0x0000001C 260*4882a593Smuzhiyun #define CFG_YUV2RGB_DMA(cvrt) ((cvrt) << 1) 261*4882a593Smuzhiyun #define CFG_YUV2RGB_DMA_MASK 0x00000002 262*4882a593Smuzhiyun #define CFG_DMA_ENA(video) (video) 263*4882a593Smuzhiyun #define CFG_DMA_ENA_MASK 0x00000001 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun /* DMA Control 1 Register */ 266*4882a593Smuzhiyun #define LCD_SPU_DMA_CTRL1 0x0194 267*4882a593Smuzhiyun #define CFG_FRAME_TRIG(trig) ((trig) << 31) 268*4882a593Smuzhiyun #define CFG_FRAME_TRIG_MASK 0x80000000 269*4882a593Smuzhiyun #define CFG_VSYNC_TRIG(trig) ((trig) << 28) 270*4882a593Smuzhiyun #define CFG_VSYNC_TRIG_MASK 0x70000000 271*4882a593Smuzhiyun #define CFG_VSYNC_INV(inv) ((inv) << 27) 272*4882a593Smuzhiyun #define CFG_VSYNC_INV_MASK 0x08000000 273*4882a593Smuzhiyun #define CFG_COLOR_KEY_MODE(cmode) ((cmode) << 24) 274*4882a593Smuzhiyun #define CFG_COLOR_KEY_MASK 0x07000000 275*4882a593Smuzhiyun #define CFG_CARRY(carry) ((carry) << 23) 276*4882a593Smuzhiyun #define CFG_CARRY_MASK 0x00800000 277*4882a593Smuzhiyun #define CFG_LNBUF_ENA(lnbuf) ((lnbuf) << 22) 278*4882a593Smuzhiyun #define CFG_LNBUF_ENA_MASK 0x00400000 279*4882a593Smuzhiyun #define CFG_GATED_ENA(gated) ((gated) << 21) 280*4882a593Smuzhiyun #define CFG_GATED_ENA_MASK 0x00200000 281*4882a593Smuzhiyun #define CFG_PWRDN_ENA(power) ((power) << 20) 282*4882a593Smuzhiyun #define CFG_PWRDN_ENA_MASK 0x00100000 283*4882a593Smuzhiyun #define CFG_DSCALE(dscale) ((dscale) << 18) 284*4882a593Smuzhiyun #define CFG_DSCALE_MASK 0x000C0000 285*4882a593Smuzhiyun #define CFG_ALPHA_MODE(amode) ((amode) << 16) 286*4882a593Smuzhiyun #define CFG_ALPHA_MODE_MASK 0x00030000 287*4882a593Smuzhiyun #define CFG_ALPHA(alpha) ((alpha) << 8) 288*4882a593Smuzhiyun #define CFG_ALPHA_MASK 0x0000FF00 289*4882a593Smuzhiyun #define CFG_PXLCMD(pxlcmd) (pxlcmd) 290*4882a593Smuzhiyun #define CFG_PXLCMD_MASK 0x000000FF 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* SRAM Control Register */ 293*4882a593Smuzhiyun #define LCD_SPU_SRAM_CTRL 0x0198 294*4882a593Smuzhiyun #define CFG_SRAM_INIT_WR_RD(mode) ((mode) << 14) 295*4882a593Smuzhiyun #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000 296*4882a593Smuzhiyun #define CFG_SRAM_ADDR_LCDID(id) ((id) << 8) 297*4882a593Smuzhiyun #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00 298*4882a593Smuzhiyun #define CFG_SRAM_ADDR(addr) (addr) 299*4882a593Smuzhiyun #define CFG_SRAM_ADDR_MASK 0x000000FF 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* SRAM Write Data Register */ 302*4882a593Smuzhiyun #define LCD_SPU_SRAM_WRDAT 0x019C 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* SRAM RTC/WTC Control Register */ 305*4882a593Smuzhiyun #define LCD_SPU_SRAM_PARA0 0x01A0 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* SRAM Power Down Control Register */ 308*4882a593Smuzhiyun #define LCD_SPU_SRAM_PARA1 0x01A4 309*4882a593Smuzhiyun #define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */ 310*4882a593Smuzhiyun #define CFG_CSB_256x32_MASK 0x00008000 311*4882a593Smuzhiyun #define CFG_CSB_256x24(palette) ((palette) << 14) /* Palette */ 312*4882a593Smuzhiyun #define CFG_CSB_256x24_MASK 0x00004000 313*4882a593Smuzhiyun #define CFG_CSB_256x8(gamma) ((gamma) << 13) /* Gamma */ 314*4882a593Smuzhiyun #define CFG_CSB_256x8_MASK 0x00002000 315*4882a593Smuzhiyun #define CFG_PDWN256x32(pdwn) ((pdwn) << 7) /* HWC */ 316*4882a593Smuzhiyun #define CFG_PDWN256x32_MASK 0x00000080 317*4882a593Smuzhiyun #define CFG_PDWN256x24(pdwn) ((pdwn) << 6) /* Palette */ 318*4882a593Smuzhiyun #define CFG_PDWN256x24_MASK 0x00000040 319*4882a593Smuzhiyun #define CFG_PDWN256x8(pdwn) ((pdwn) << 5) /* Gamma */ 320*4882a593Smuzhiyun #define CFG_PDWN256x8_MASK 0x00000020 321*4882a593Smuzhiyun #define CFG_PDWN32x32(pdwn) ((pdwn) << 3) 322*4882a593Smuzhiyun #define CFG_PDWN32x32_MASK 0x00000008 323*4882a593Smuzhiyun #define CFG_PDWN16x66(pdwn) ((pdwn) << 2) 324*4882a593Smuzhiyun #define CFG_PDWN16x66_MASK 0x00000004 325*4882a593Smuzhiyun #define CFG_PDWN32x66(pdwn) ((pdwn) << 1) 326*4882a593Smuzhiyun #define CFG_PDWN32x66_MASK 0x00000002 327*4882a593Smuzhiyun #define CFG_PDWN64x66(pdwn) (pdwn) 328*4882a593Smuzhiyun #define CFG_PDWN64x66_MASK 0x00000001 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun /* Smart or Dumb Panel Clock Divider */ 331*4882a593Smuzhiyun #define LCD_CFG_SCLK_DIV 0x01A8 332*4882a593Smuzhiyun #define SCLK_SOURCE_SELECT(src) ((src) << 31) 333*4882a593Smuzhiyun #define SCLK_SOURCE_SELECT_MASK 0x80000000 334*4882a593Smuzhiyun #define CLK_FRACDIV(frac) ((frac) << 16) 335*4882a593Smuzhiyun #define CLK_FRACDIV_MASK 0x0FFF0000 336*4882a593Smuzhiyun #define CLK_INT_DIV(div) (div) 337*4882a593Smuzhiyun #define CLK_INT_DIV_MASK 0x0000FFFF 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun /* Video Contrast Register */ 340*4882a593Smuzhiyun #define LCD_SPU_CONTRAST 0x01AC 341*4882a593Smuzhiyun #define CFG_BRIGHTNESS(bright) ((bright) << 16) 342*4882a593Smuzhiyun #define CFG_BRIGHTNESS_MASK 0xFFFF0000 343*4882a593Smuzhiyun #define CFG_CONTRAST(contrast) (contrast) 344*4882a593Smuzhiyun #define CFG_CONTRAST_MASK 0x0000FFFF 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun /* Video Saturation Register */ 347*4882a593Smuzhiyun #define LCD_SPU_SATURATION 0x01B0 348*4882a593Smuzhiyun #define CFG_C_MULTS(mult) ((mult) << 16) 349*4882a593Smuzhiyun #define CFG_C_MULTS_MASK 0xFFFF0000 350*4882a593Smuzhiyun #define CFG_SATURATION(sat) (sat) 351*4882a593Smuzhiyun #define CFG_SATURATION_MASK 0x0000FFFF 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun /* Video Hue Adjust Register */ 354*4882a593Smuzhiyun #define LCD_SPU_CBSH_HUE 0x01B4 355*4882a593Smuzhiyun #define CFG_SIN0(sin0) ((sin0) << 16) 356*4882a593Smuzhiyun #define CFG_SIN0_MASK 0xFFFF0000 357*4882a593Smuzhiyun #define CFG_COS0(con0) (con0) 358*4882a593Smuzhiyun #define CFG_COS0_MASK 0x0000FFFF 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun /* Dump LCD Panel Control Register */ 361*4882a593Smuzhiyun #define LCD_SPU_DUMB_CTRL 0x01B8 362*4882a593Smuzhiyun #define CFG_DUMBMODE(mode) ((mode) << 28) 363*4882a593Smuzhiyun #define CFG_DUMBMODE_MASK 0xF0000000 364*4882a593Smuzhiyun #define CFG_LCDGPIO_O(data) ((data) << 20) 365*4882a593Smuzhiyun #define CFG_LCDGPIO_O_MASK 0x0FF00000 366*4882a593Smuzhiyun #define CFG_LCDGPIO_ENA(gpio) ((gpio) << 12) 367*4882a593Smuzhiyun #define CFG_LCDGPIO_ENA_MASK 0x000FF000 368*4882a593Smuzhiyun #define CFG_BIAS_OUT(bias) ((bias) << 8) 369*4882a593Smuzhiyun #define CFG_BIAS_OUT_MASK 0x00000100 370*4882a593Smuzhiyun #define CFG_REVERSE_RGB(rRGB) ((rRGB) << 7) 371*4882a593Smuzhiyun #define CFG_REVERSE_RGB_MASK 0x00000080 372*4882a593Smuzhiyun #define CFG_INV_COMPBLANK(blank) ((blank) << 6) 373*4882a593Smuzhiyun #define CFG_INV_COMPBLANK_MASK 0x00000040 374*4882a593Smuzhiyun #define CFG_INV_COMPSYNC(sync) ((sync) << 5) 375*4882a593Smuzhiyun #define CFG_INV_COMPSYNC_MASK 0x00000020 376*4882a593Smuzhiyun #define CFG_INV_HENA(hena) ((hena) << 4) 377*4882a593Smuzhiyun #define CFG_INV_HENA_MASK 0x00000010 378*4882a593Smuzhiyun #define CFG_INV_VSYNC(vsync) ((vsync) << 3) 379*4882a593Smuzhiyun #define CFG_INV_VSYNC_MASK 0x00000008 380*4882a593Smuzhiyun #define CFG_INV_HSYNC(hsync) ((hsync) << 2) 381*4882a593Smuzhiyun #define CFG_INV_HSYNC_MASK 0x00000004 382*4882a593Smuzhiyun #define CFG_INV_PCLK(pclk) ((pclk) << 1) 383*4882a593Smuzhiyun #define CFG_INV_PCLK_MASK 0x00000002 384*4882a593Smuzhiyun #define CFG_DUMB_ENA(dumb) (dumb) 385*4882a593Smuzhiyun #define CFG_DUMB_ENA_MASK 0x00000001 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /* LCD I/O Pads Control Register */ 388*4882a593Smuzhiyun #define SPU_IOPAD_CONTROL 0x01BC 389*4882a593Smuzhiyun #define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */ 390*4882a593Smuzhiyun #define CFG_GRA_VM_ENA_MASK 0x00008000 391*4882a593Smuzhiyun #define CFG_DMA_VM_ENA(vm) ((vm) << 13) /* video */ 392*4882a593Smuzhiyun #define CFG_DMA_VM_ENA_MASK 0x00002000 393*4882a593Smuzhiyun #define CFG_CMD_VM_ENA(vm) ((vm) << 13) 394*4882a593Smuzhiyun #define CFG_CMD_VM_ENA_MASK 0x00000800 395*4882a593Smuzhiyun #define CFG_CSC(csc) ((csc) << 8) /* csc */ 396*4882a593Smuzhiyun #define CFG_CSC_MASK 0x00000300 397*4882a593Smuzhiyun #define CFG_AXICTRL(axi) ((axi) << 4) 398*4882a593Smuzhiyun #define CFG_AXICTRL_MASK 0x000000F0 399*4882a593Smuzhiyun #define CFG_IOPADMODE(iopad) (iopad) 400*4882a593Smuzhiyun #define CFG_IOPADMODE_MASK 0x0000000F 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun /* LCD Interrupt Control Register */ 403*4882a593Smuzhiyun #define SPU_IRQ_ENA 0x01C0 404*4882a593Smuzhiyun #define DMA_FRAME_IRQ0_ENA(irq) ((irq) << 31) 405*4882a593Smuzhiyun #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000 406*4882a593Smuzhiyun #define DMA_FRAME_IRQ1_ENA(irq) ((irq) << 30) 407*4882a593Smuzhiyun #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000 408*4882a593Smuzhiyun #define DMA_FF_UNDERFLOW_ENA(ff) ((ff) << 29) 409*4882a593Smuzhiyun #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000 410*4882a593Smuzhiyun #define GRA_FRAME_IRQ0_ENA(irq) ((irq) << 27) 411*4882a593Smuzhiyun #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000 412*4882a593Smuzhiyun #define GRA_FRAME_IRQ1_ENA(irq) ((irq) << 26) 413*4882a593Smuzhiyun #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000 414*4882a593Smuzhiyun #define GRA_FF_UNDERFLOW_ENA(ff) ((ff) << 25) 415*4882a593Smuzhiyun #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000 416*4882a593Smuzhiyun #define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq) << 23) 417*4882a593Smuzhiyun #define VSYNC_IRQ_ENA_MASK 0x00800000 418*4882a593Smuzhiyun #define DUMB_FRAMEDONE_ENA(fdone) ((fdone) << 22) 419*4882a593Smuzhiyun #define DUMB_FRAMEDONE_ENA_MASK 0x00400000 420*4882a593Smuzhiyun #define TWC_FRAMEDONE_ENA(fdone) ((fdone) << 21) 421*4882a593Smuzhiyun #define TWC_FRAMEDONE_ENA_MASK 0x00200000 422*4882a593Smuzhiyun #define HWC_FRAMEDONE_ENA(fdone) ((fdone) << 20) 423*4882a593Smuzhiyun #define HWC_FRAMEDONE_ENA_MASK 0x00100000 424*4882a593Smuzhiyun #define SLV_IRQ_ENA(irq) ((irq) << 19) 425*4882a593Smuzhiyun #define SLV_IRQ_ENA_MASK 0x00080000 426*4882a593Smuzhiyun #define SPI_IRQ_ENA(irq) ((irq) << 18) 427*4882a593Smuzhiyun #define SPI_IRQ_ENA_MASK 0x00040000 428*4882a593Smuzhiyun #define PWRDN_IRQ_ENA(irq) ((irq) << 17) 429*4882a593Smuzhiyun #define PWRDN_IRQ_ENA_MASK 0x00020000 430*4882a593Smuzhiyun #define ERR_IRQ_ENA(irq) ((irq) << 16) 431*4882a593Smuzhiyun #define ERR_IRQ_ENA_MASK 0x00010000 432*4882a593Smuzhiyun #define CLEAN_SPU_IRQ_ISR(irq) (irq) 433*4882a593Smuzhiyun #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun /* LCD Interrupt Status Register */ 436*4882a593Smuzhiyun #define SPU_IRQ_ISR 0x01C4 437*4882a593Smuzhiyun #define DMA_FRAME_IRQ0(irq) ((irq) << 31) 438*4882a593Smuzhiyun #define DMA_FRAME_IRQ0_MASK 0x80000000 439*4882a593Smuzhiyun #define DMA_FRAME_IRQ1(irq) ((irq) << 30) 440*4882a593Smuzhiyun #define DMA_FRAME_IRQ1_MASK 0x40000000 441*4882a593Smuzhiyun #define DMA_FF_UNDERFLOW(ff) ((ff) << 29) 442*4882a593Smuzhiyun #define DMA_FF_UNDERFLOW_MASK 0x20000000 443*4882a593Smuzhiyun #define GRA_FRAME_IRQ0(irq) ((irq) << 27) 444*4882a593Smuzhiyun #define GRA_FRAME_IRQ0_MASK 0x08000000 445*4882a593Smuzhiyun #define GRA_FRAME_IRQ1(irq) ((irq) << 26) 446*4882a593Smuzhiyun #define GRA_FRAME_IRQ1_MASK 0x04000000 447*4882a593Smuzhiyun #define GRA_FF_UNDERFLOW(ff) ((ff) << 25) 448*4882a593Smuzhiyun #define GRA_FF_UNDERFLOW_MASK 0x02000000 449*4882a593Smuzhiyun #define VSYNC_IRQ(vsync_irq) ((vsync_irq) << 23) 450*4882a593Smuzhiyun #define VSYNC_IRQ_MASK 0x00800000 451*4882a593Smuzhiyun #define DUMB_FRAMEDONE(fdone) ((fdone) << 22) 452*4882a593Smuzhiyun #define DUMB_FRAMEDONE_MASK 0x00400000 453*4882a593Smuzhiyun #define TWC_FRAMEDONE(fdone) ((fdone) << 21) 454*4882a593Smuzhiyun #define TWC_FRAMEDONE_MASK 0x00200000 455*4882a593Smuzhiyun #define HWC_FRAMEDONE(fdone) ((fdone) << 20) 456*4882a593Smuzhiyun #define HWC_FRAMEDONE_MASK 0x00100000 457*4882a593Smuzhiyun #define SLV_IRQ(irq) ((irq) << 19) 458*4882a593Smuzhiyun #define SLV_IRQ_MASK 0x00080000 459*4882a593Smuzhiyun #define SPI_IRQ(irq) ((irq) << 18) 460*4882a593Smuzhiyun #define SPI_IRQ_MASK 0x00040000 461*4882a593Smuzhiyun #define PWRDN_IRQ(irq) ((irq) << 17) 462*4882a593Smuzhiyun #define PWRDN_IRQ_MASK 0x00020000 463*4882a593Smuzhiyun #define ERR_IRQ(irq) ((irq) << 16) 464*4882a593Smuzhiyun #define ERR_IRQ_MASK 0x00010000 465*4882a593Smuzhiyun /* read-only */ 466*4882a593Smuzhiyun #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000 467*4882a593Smuzhiyun #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000 468*4882a593Smuzhiyun #define DMA_FRAME_CNT_ISR_MASK 0x00003000 469*4882a593Smuzhiyun #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800 470*4882a593Smuzhiyun #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400 471*4882a593Smuzhiyun #define GRA_FRAME_CNT_ISR_MASK 0x00000300 472*4882a593Smuzhiyun #define VSYNC_IRQ_LEVEL_MASK 0x00000080 473*4882a593Smuzhiyun #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040 474*4882a593Smuzhiyun #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020 475*4882a593Smuzhiyun #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010 476*4882a593Smuzhiyun #define SLV_FF_EMPTY_MASK 0x00000008 477*4882a593Smuzhiyun #define DMA_FF_ALLEMPTY_MASK 0x00000004 478*4882a593Smuzhiyun #define GRA_FF_ALLEMPTY_MASK 0x00000002 479*4882a593Smuzhiyun #define PWRDN_IRQ_LEVEL_MASK 0x00000001 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun /* 483*4882a593Smuzhiyun * defined Video Memory Color format for DMA control 0 register 484*4882a593Smuzhiyun * DMA0 bit[23:20] 485*4882a593Smuzhiyun */ 486*4882a593Smuzhiyun #define VMODE_RGB565 0x0 487*4882a593Smuzhiyun #define VMODE_RGB1555 0x1 488*4882a593Smuzhiyun #define VMODE_RGB888PACKED 0x2 489*4882a593Smuzhiyun #define VMODE_RGB888UNPACKED 0x3 490*4882a593Smuzhiyun #define VMODE_RGBA888 0x4 491*4882a593Smuzhiyun #define VMODE_YUV422PACKED 0x5 492*4882a593Smuzhiyun #define VMODE_YUV422PLANAR 0x6 493*4882a593Smuzhiyun #define VMODE_YUV420PLANAR 0x7 494*4882a593Smuzhiyun #define VMODE_SMPNCMD 0x8 495*4882a593Smuzhiyun #define VMODE_PALETTE4BIT 0x9 496*4882a593Smuzhiyun #define VMODE_PALETTE8BIT 0xa 497*4882a593Smuzhiyun #define VMODE_RESERVED 0xb 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun /* 500*4882a593Smuzhiyun * defined Graphic Memory Color format for DMA control 0 register 501*4882a593Smuzhiyun * DMA0 bit[19:16] 502*4882a593Smuzhiyun */ 503*4882a593Smuzhiyun #define GMODE_RGB565 0x0 504*4882a593Smuzhiyun #define GMODE_RGB1555 0x1 505*4882a593Smuzhiyun #define GMODE_RGB888PACKED 0x2 506*4882a593Smuzhiyun #define GMODE_RGB888UNPACKED 0x3 507*4882a593Smuzhiyun #define GMODE_RGBA888 0x4 508*4882a593Smuzhiyun #define GMODE_YUV422PACKED 0x5 509*4882a593Smuzhiyun #define GMODE_YUV422PLANAR 0x6 510*4882a593Smuzhiyun #define GMODE_YUV420PLANAR 0x7 511*4882a593Smuzhiyun #define GMODE_SMPNCMD 0x8 512*4882a593Smuzhiyun #define GMODE_PALETTE4BIT 0x9 513*4882a593Smuzhiyun #define GMODE_PALETTE8BIT 0xa 514*4882a593Smuzhiyun #define GMODE_RESERVED 0xb 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun /* 517*4882a593Smuzhiyun * define for DMA control 1 register 518*4882a593Smuzhiyun */ 519*4882a593Smuzhiyun #define DMA1_FRAME_TRIG 31 /* bit location */ 520*4882a593Smuzhiyun #define DMA1_VSYNC_MODE 28 521*4882a593Smuzhiyun #define DMA1_VSYNC_INV 27 522*4882a593Smuzhiyun #define DMA1_CKEY 24 523*4882a593Smuzhiyun #define DMA1_CARRY 23 524*4882a593Smuzhiyun #define DMA1_LNBUF_ENA 22 525*4882a593Smuzhiyun #define DMA1_GATED_ENA 21 526*4882a593Smuzhiyun #define DMA1_PWRDN_ENA 20 527*4882a593Smuzhiyun #define DMA1_DSCALE 18 528*4882a593Smuzhiyun #define DMA1_ALPHA_MODE 16 529*4882a593Smuzhiyun #define DMA1_ALPHA 08 530*4882a593Smuzhiyun #define DMA1_PXLCMD 00 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun /* 533*4882a593Smuzhiyun * defined for Configure Dumb Mode 534*4882a593Smuzhiyun * DUMB LCD Panel bit[31:28] 535*4882a593Smuzhiyun */ 536*4882a593Smuzhiyun #define DUMB16_RGB565_0 0x0 537*4882a593Smuzhiyun #define DUMB16_RGB565_1 0x1 538*4882a593Smuzhiyun #define DUMB18_RGB666_0 0x2 539*4882a593Smuzhiyun #define DUMB18_RGB666_1 0x3 540*4882a593Smuzhiyun #define DUMB12_RGB444_0 0x4 541*4882a593Smuzhiyun #define DUMB12_RGB444_1 0x5 542*4882a593Smuzhiyun #define DUMB24_RGB888_0 0x6 543*4882a593Smuzhiyun #define DUMB_BLANK 0x7 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun /* 546*4882a593Smuzhiyun * defined for Configure I/O Pin Allocation Mode 547*4882a593Smuzhiyun * LCD LCD I/O Pads control register bit[3:0] 548*4882a593Smuzhiyun */ 549*4882a593Smuzhiyun #define IOPAD_DUMB24 0x0 550*4882a593Smuzhiyun #define IOPAD_DUMB18SPI 0x1 551*4882a593Smuzhiyun #define IOPAD_DUMB18GPIO 0x2 552*4882a593Smuzhiyun #define IOPAD_DUMB16SPI 0x3 553*4882a593Smuzhiyun #define IOPAD_DUMB16GPIO 0x4 554*4882a593Smuzhiyun #define IOPAD_DUMB12 0x5 555*4882a593Smuzhiyun #define IOPAD_SMART18SPI 0x6 556*4882a593Smuzhiyun #define IOPAD_SMART16SPI 0x7 557*4882a593Smuzhiyun #define IOPAD_SMART8BOTH 0x8 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun #endif /* __PXA168FB_H__ */ 560