1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_SDRAM_RK3308_H 7*4882a593Smuzhiyun #define _ASM_ARCH_SDRAM_RK3308_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <ram.h> 10*4882a593Smuzhiyun #include <asm/arch/cru_rk3308.h> 11*4882a593Smuzhiyun #include <asm/arch/grf_rk3308.h> 12*4882a593Smuzhiyun #include <asm/arch/pmu_rk3308.h> 13*4882a593Smuzhiyun #include <asm/arch/sdram_common.h> 14*4882a593Smuzhiyun #include <asm/arch/sdram_rv1108_pctl_phy.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CG_EXIT_TH (250) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define PATTERN (0x5aa5f00f) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct rk3308_ddr_standby { 21*4882a593Smuzhiyun u32 con0; 22*4882a593Smuzhiyun u32 con1; 23*4882a593Smuzhiyun u32 status0; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct rk3308_service_msch { 27*4882a593Smuzhiyun u32 id_coreid; 28*4882a593Smuzhiyun u32 id_revisionid; 29*4882a593Smuzhiyun u32 ddrconf; 30*4882a593Smuzhiyun u32 ddrtiming; 31*4882a593Smuzhiyun u32 ddrmode; 32*4882a593Smuzhiyun u32 readlatency; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum { 36*4882a593Smuzhiyun /* ddr standby */ 37*4882a593Smuzhiyun IDLE_TH_SHIFT = 16, 38*4882a593Smuzhiyun /* can not gate msch clk */ 39*4882a593Smuzhiyun MSCH_GATE_CLK_SHIFT = 7, 40*4882a593Smuzhiyun MSCH_GATE_CLK_EN = 1, 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun DDRPHY4X_GATE_SHIFT = 6, 43*4882a593Smuzhiyun DDRPHY4X_GATE_EN = 1, 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun UPCTL_CORE_CLK_GATE_SHIFT = 5, 46*4882a593Smuzhiyun UPCTL_CORE_CLK_GATE_EN = 1, 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun UPCTL_ACLK_GATE_SHIFT = 4, 49*4882a593Smuzhiyun UPCTL_ACLK_GATE_EN = 1, 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun CTL_IDLR_SHIFT = 1, 52*4882a593Smuzhiyun CTL_IDLR_EN = 1, 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun STDBY_EN_SHIFT = 0, 55*4882a593Smuzhiyun STDBY_EN = 1, 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun CG_EXIT_TH_SHIFT = 16, 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun STDBY_STATUS_SHIFT = 0, 60*4882a593Smuzhiyun STDBY_STATUS_MASK = 0x7f << STDBY_STATUS_SHIFT, 61*4882a593Smuzhiyun ST_STDBY = 0x10, 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun enum { 65*4882a593Smuzhiyun /* memory scheduler ddrtiming */ 66*4882a593Smuzhiyun BWRATIO_HALF_BW = 0x80000000, 67*4882a593Smuzhiyun BWRATIO_HALF_BW_DIS = 0x0, 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun PHY_TX_DE_SKEW_SHIFT = 3, 70*4882a593Smuzhiyun PHY_TX_DE_SKEW_EN = 1, 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct dram_info { 74*4882a593Smuzhiyun struct rk3308_cru *cru; 75*4882a593Smuzhiyun struct rk3308_grf *grf; 76*4882a593Smuzhiyun struct rk3308_sgrf *sgrf; 77*4882a593Smuzhiyun struct rk3308_pmu *pmu; 78*4882a593Smuzhiyun struct ddr_phy *phy; 79*4882a593Smuzhiyun struct ddr_pctl *pctl; 80*4882a593Smuzhiyun struct rk3308_ddr_standby *standby; 81*4882a593Smuzhiyun struct rk3308_service_msch *service_msch; 82*4882a593Smuzhiyun struct ram_info info; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct sdram_params { 86*4882a593Smuzhiyun u32 idle_pd; 87*4882a593Smuzhiyun u32 idle_sr; 88*4882a593Smuzhiyun u32 ddr_2t_en; 89*4882a593Smuzhiyun u32 stdby_idle; 90*4882a593Smuzhiyun struct ddr_config ddr_config_t; 91*4882a593Smuzhiyun struct ddr_timing ddr_timing_t; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct rk3308_ddr_skew { 95*4882a593Smuzhiyun u32 a0_a1_skew[14]; 96*4882a593Smuzhiyun u32 cs0_dm0_skew[22]; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct rk3308_ddr_gd { 100*4882a593Smuzhiyun struct sdram_head_info_v0 head_info; 101*4882a593Smuzhiyun struct rk3308_ddr_skew ddr_skew; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun int check_rd_gate(struct dram_info *priv); 105*4882a593Smuzhiyun void copy_to_reg(u32 *dest, const u32 *src, u32 n); 106*4882a593Smuzhiyun void enable_low_power(struct dram_info *priv, 107*4882a593Smuzhiyun struct sdram_params *params_priv); 108*4882a593Smuzhiyun void ddr_cap_info(size_t size); 109*4882a593Smuzhiyun void ddr_msch_cfg(struct dram_info *priv, 110*4882a593Smuzhiyun struct sdram_params *params_priv); 111*4882a593Smuzhiyun void ddr_msch_cfg_rbc(struct sdram_params *params_priv, 112*4882a593Smuzhiyun struct dram_info *priv); 113*4882a593Smuzhiyun void ddr_msch_get_max_col(struct dram_info *priv, 114*4882a593Smuzhiyun struct ddr_schedule *sch_priv); 115*4882a593Smuzhiyun void ddr_msch_get_max_row(struct dram_info *priv, 116*4882a593Smuzhiyun struct ddr_schedule *sch_priv); 117*4882a593Smuzhiyun void ddr_phy_skew_cfg(struct dram_info *priv); 118*4882a593Smuzhiyun void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq); 119*4882a593Smuzhiyun void enable_ddr_io_ret(struct dram_info *priv); 120*4882a593Smuzhiyun void modify_data_training(struct dram_info *priv, 121*4882a593Smuzhiyun struct sdram_params *params_priv); 122*4882a593Smuzhiyun void move_to_config_state(struct dram_info *priv); 123*4882a593Smuzhiyun void move_to_access_state(struct dram_info *priv); 124*4882a593Smuzhiyun void pctl_cfg_grf(struct dram_info *priv, 125*4882a593Smuzhiyun struct sdram_params *params_priv); 126*4882a593Smuzhiyun void phy_pctrl_reset_cru(struct dram_info *priv); 127*4882a593Smuzhiyun void print_dec(u32 n); 128*4882a593Smuzhiyun void rkdclk_init(struct dram_info *priv, 129*4882a593Smuzhiyun struct sdram_params *params_priv); 130*4882a593Smuzhiyun int rv1108_sdram_init(struct dram_info *sdram_priv, 131*4882a593Smuzhiyun struct sdram_params *params_priv); 132*4882a593Smuzhiyun void set_bw_grf(struct dram_info *priv); 133*4882a593Smuzhiyun void set_ds_odt(struct dram_info *priv, 134*4882a593Smuzhiyun struct sdram_params *params_priv); 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif 137