1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * Author: Andy Yan <andy.yan@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3368_H 7 #define _ASM_ARCH_CRU_RK3368_H 8 9 #include <common.h> 10 11 12 /* RK3368 clock numbers */ 13 enum rk3368_pll_id { 14 APLLB, 15 APLLL, 16 DPLL, 17 CPLL, 18 GPLL, 19 NPLL, 20 PLL_COUNT, 21 }; 22 23 struct rk3368_clk_info { 24 unsigned long id; 25 char *name; 26 bool is_cru; 27 }; 28 29 struct rk3368_cru { 30 struct rk3368_pll { 31 unsigned int con0; 32 unsigned int con1; 33 unsigned int con2; 34 unsigned int con3; 35 } pll[6]; 36 unsigned int reserved[0x28]; 37 unsigned int clksel_con[56]; 38 unsigned int reserved1[8]; 39 unsigned int clkgate_con[25]; 40 unsigned int reserved2[7]; 41 unsigned int glb_srst_fst_val; 42 unsigned int glb_srst_snd_val; 43 unsigned int reserved3[0x1e]; 44 unsigned int softrst_con[15]; 45 unsigned int reserved4[0x11]; 46 unsigned int misc_con; 47 unsigned int glb_cnt_th; 48 unsigned int glb_rst_con; 49 unsigned int glb_rst_st; 50 unsigned int reserved5[0x1c]; 51 unsigned int sdmmc_con[2]; 52 unsigned int sdio0_con[2]; 53 unsigned int sdio1_con[2]; 54 unsigned int emmc_con[2]; 55 }; 56 check_member(rk3368_cru, emmc_con[1], 0x41c); 57 58 struct rk3368_clk_priv { 59 struct rk3368_cru *cru; 60 ulong armlclk_hz; 61 ulong armlclk_enter_hz; 62 ulong armlclk_init_hz; 63 ulong armbclk_hz; 64 ulong armbclk_enter_hz; 65 ulong armbclk_init_hz; 66 bool sync_kernel; 67 bool set_armclk_rate; 68 }; 69 70 enum { 71 /* PLL CON0 */ 72 PLL_NR_SHIFT = 8, 73 PLL_NR_MASK = GENMASK(13, 8), 74 PLL_OD_SHIFT = 0, 75 PLL_OD_MASK = GENMASK(3, 0), 76 77 /* PLL CON1 */ 78 PLL_LOCK_STA = BIT(31), 79 PLL_NF_SHIFT = 0, 80 PLL_NF_MASK = GENMASK(12, 0), 81 82 /* PLL CON2 */ 83 PLL_BWADJ_SHIFT = 0, 84 PLL_BWADJ_MASK = GENMASK(11, 0), 85 86 /* PLL CON3 */ 87 PLL_MODE_SHIFT = 8, 88 PLL_MODE_MASK = GENMASK(9, 8), 89 PLL_MODE_SLOW = 0, 90 PLL_MODE_NORMAL = 1, 91 PLL_MODE_DEEP_SLOW = 3, 92 PLL_RESET_SHIFT = 5, 93 PLL_RESET = 1, 94 PLL_RESET_MASK = GENMASK(5, 5), 95 96 /* CLKSEL1CON */ 97 CORE_ACLK_DIV_SHIFT = 0, 98 CORE_ACLK_DIV_MASK = 0x1f << CORE_ACLK_DIV_SHIFT, 99 CORE_DBG_DIV_SHIFT = 8, 100 CORE_DBG_DIV_MASK = 0x1f << CORE_DBG_DIV_SHIFT, 101 102 CORE_CLK_PLL_SEL_SHIFT = 7, 103 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 104 CORE_CLK_PLL_SEL_APLL = 0, 105 CORE_CLK_PLL_SEL_GPLL, 106 CORE_DIV_CON_SHIFT = 0, 107 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 108 109 /* CLKSEL8CON */ 110 PCLK_BUS_DIV_CON_SHIFT = 12, 111 PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT, 112 HCLK_BUS_DIV_CON_SHIFT = 8, 113 HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT, 114 CLK_BUS_PLL_SEL_CPLL = 0, 115 CLK_BUS_PLL_SEL_GPLL = 1, 116 CLK_BUS_PLL_SEL_SHIFT = 7, 117 CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, 118 ACLK_BUS_DIV_CON_SHIFT = 0, 119 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 120 121 /* CLKSEL9CON */ 122 PCLK_PERI_DIV_CON_SHIFT = 12, 123 PCLK_PERI_DIV_CON_MASK = 0x3 << PCLK_PERI_DIV_CON_SHIFT, 124 HCLK_PERI_DIV_CON_SHIFT = 8, 125 HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT, 126 CLK_PERI_PLL_SEL_CPLL = 0, 127 CLK_PERI_PLL_SEL_GPLL, 128 CLK_PERI_PLL_SEL_SHIFT = 7, 129 CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, 130 ACLK_PERI_DIV_CON_SHIFT = 0, 131 ACLK_PERI_DIV_CON_MASK = 0x1f, 132 133 /* CLKSEL10CON */ 134 CLK_CRYPTO_DIV_CON_SHIFT = 14, 135 CLK_CRYPTO_DIV_CON_MASK = 0x3 << CLK_CRYPTO_DIV_CON_SHIFT, 136 PCLK_ALIVE_DIV_CON_SHIFT = 8, 137 PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, 138 139 /* CLKSEL12_CON */ 140 MCU_STCLK_DIV_SHIFT = 8, 141 MCU_STCLK_DIV_MASK = GENMASK(10, 8), 142 MCU_PLL_SEL_SHIFT = 7, 143 MCU_PLL_SEL_MASK = BIT(7), 144 MCU_PLL_SEL_CPLL = 0, 145 MCU_PLL_SEL_GPLL = 1, 146 MCU_CLK_DIV_SHIFT = 0, 147 MCU_CLK_DIV_MASK = GENMASK(4, 0), 148 149 /* CLKSEL19_CON */ 150 ACLK_VOP_PLL_SEL_SHIFT = 6, 151 ACLK_VOP_PLL_SEL_MASK = GENMASK(7, 6), 152 ACLK_VOP_PLL_SEL_CPLL = 0, 153 ACLK_VOP_PLL_SEL_GPLL = 1, 154 ACLK_VOP_DIV_SHIFT = 0, 155 ACLK_VOP_DIV_MASK = GENMASK(4, 0), 156 157 /* CLKSEL20_CON */ 158 DCLK_VOP_PLL_SEL_SHIFT = 8, 159 DCLK_VOP_PLL_SEL_MASK = GENMASK(9, 8), 160 DCLK_VOP_PLL_SEL_CPLL = 0, 161 DCLK_VOP_PLL_SEL_GPLL = 1, 162 DCLK_VOP_PLL_SEL_NPLL = 2, 163 DCLK_VOP_DIV_SHIFT = 0, 164 DCLK_VOP_DIV_MASK = GENMASK(7, 0), 165 166 /* CLKSEL_CON25 */ 167 CLK_SARADC_DIV_CON_SHIFT = 8, 168 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 169 CLK_SARADC_DIV_CON_WIDTH = 8, 170 171 /* CLKSEL43_CON */ 172 GMAC_DIV_CON_SHIFT = 0x0, 173 GMAC_DIV_CON_MASK = GENMASK(4, 0), 174 GMAC_PLL_SHIFT = 6, 175 GMAC_PLL_MASK = GENMASK(7, 6), 176 GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT), 177 GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT), 178 GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT), 179 GMAC_MUX_SEL_EXTCLK = BIT(8), 180 181 /* CLKSEL51_CON */ 182 MMC_PLL_SEL_SHIFT = 8, 183 MMC_PLL_SEL_MASK = GENMASK(9, 8), 184 MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), 185 MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), 186 MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), 187 MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), 188 MMC_CLK_DIV_SHIFT = 0, 189 MMC_CLK_DIV_MASK = GENMASK(6, 0), 190 191 /* SOFTRST1_CON */ 192 MCU_PO_SRST_MASK = BIT(13), 193 MCU_SYS_SRST_MASK = BIT(12), 194 DMA1_SRST_REQ = BIT(2), 195 196 /* SOFTRST4_CON */ 197 DMA2_SRST_REQ = BIT(0), 198 199 /* GLB_RST_CON */ 200 PMU_GLB_SRST_CTRL_SHIFT = 2, 201 PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), 202 PMU_RST_BY_FST_GLB_SRST = 0, 203 PMU_RST_BY_SND_GLB_SRST = 1, 204 PMU_RST_DISABLE = 2, 205 WDT_GLB_SRST_CTRL_SHIFT = 1, 206 WDT_GLB_SRST_CTRL_MASK = BIT(1), 207 WDT_TRIGGER_SND_GLB_SRST = 0, 208 WDT_TRIGGER_FST_GLB_SRST = 1, 209 TSADC_GLB_SRST_CTRL_SHIFT = 0, 210 TSADC_GLB_SRST_CTRL_MASK = BIT(0), 211 TSADC_TRIGGER_SND_GLB_SRST = 0, 212 TSADC_TRIGGER_FST_GLB_SRST = 1, 213 214 }; 215 #endif 216