1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_RK3308_H 7 #define _ASM_ARCH_SDRAM_RK3308_H 8 9 #include <ram.h> 10 #include <asm/arch/cru_rk3308.h> 11 #include <asm/arch/grf_rk3308.h> 12 #include <asm/arch/pmu_rk3308.h> 13 #include <asm/arch/sdram_common.h> 14 #include <asm/arch/sdram_rv1108_pctl_phy.h> 15 16 #define CG_EXIT_TH (250) 17 18 #define PATTERN (0x5aa5f00f) 19 20 struct rk3308_ddr_standby { 21 u32 con0; 22 u32 con1; 23 u32 status0; 24 }; 25 26 struct rk3308_service_msch { 27 u32 id_coreid; 28 u32 id_revisionid; 29 u32 ddrconf; 30 u32 ddrtiming; 31 u32 ddrmode; 32 u32 readlatency; 33 }; 34 35 enum { 36 /* ddr standby */ 37 IDLE_TH_SHIFT = 16, 38 /* can not gate msch clk */ 39 MSCH_GATE_CLK_SHIFT = 7, 40 MSCH_GATE_CLK_EN = 1, 41 42 DDRPHY4X_GATE_SHIFT = 6, 43 DDRPHY4X_GATE_EN = 1, 44 45 UPCTL_CORE_CLK_GATE_SHIFT = 5, 46 UPCTL_CORE_CLK_GATE_EN = 1, 47 48 UPCTL_ACLK_GATE_SHIFT = 4, 49 UPCTL_ACLK_GATE_EN = 1, 50 51 CTL_IDLR_SHIFT = 1, 52 CTL_IDLR_EN = 1, 53 54 STDBY_EN_SHIFT = 0, 55 STDBY_EN = 1, 56 57 CG_EXIT_TH_SHIFT = 16, 58 59 STDBY_STATUS_SHIFT = 0, 60 STDBY_STATUS_MASK = 0x7f << STDBY_STATUS_SHIFT, 61 ST_STDBY = 0x10, 62 }; 63 64 enum { 65 /* memory scheduler ddrtiming */ 66 BWRATIO_HALF_BW = 0x80000000, 67 BWRATIO_HALF_BW_DIS = 0x0, 68 69 PHY_TX_DE_SKEW_SHIFT = 3, 70 PHY_TX_DE_SKEW_EN = 1, 71 }; 72 73 struct dram_info { 74 struct rk3308_cru *cru; 75 struct rk3308_grf *grf; 76 struct rk3308_sgrf *sgrf; 77 struct rk3308_pmu *pmu; 78 struct ddr_phy *phy; 79 struct ddr_pctl *pctl; 80 struct rk3308_ddr_standby *standby; 81 struct rk3308_service_msch *service_msch; 82 struct ram_info info; 83 }; 84 85 struct sdram_params { 86 u32 idle_pd; 87 u32 idle_sr; 88 u32 ddr_2t_en; 89 u32 stdby_idle; 90 struct ddr_config ddr_config_t; 91 struct ddr_timing ddr_timing_t; 92 }; 93 94 struct rk3308_ddr_skew { 95 u32 a0_a1_skew[14]; 96 u32 cs0_dm0_skew[22]; 97 }; 98 99 struct rk3308_ddr_gd { 100 struct sdram_head_info_v0 head_info; 101 struct rk3308_ddr_skew ddr_skew; 102 }; 103 104 int check_rd_gate(struct dram_info *priv); 105 void copy_to_reg(u32 *dest, const u32 *src, u32 n); 106 void enable_low_power(struct dram_info *priv, 107 struct sdram_params *params_priv); 108 void ddr_cap_info(size_t size); 109 void ddr_msch_cfg(struct dram_info *priv, 110 struct sdram_params *params_priv); 111 void ddr_msch_cfg_rbc(struct sdram_params *params_priv, 112 struct dram_info *priv); 113 void ddr_msch_get_max_col(struct dram_info *priv, 114 struct ddr_schedule *sch_priv); 115 void ddr_msch_get_max_row(struct dram_info *priv, 116 struct ddr_schedule *sch_priv); 117 void ddr_phy_skew_cfg(struct dram_info *priv); 118 void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq); 119 void enable_ddr_io_ret(struct dram_info *priv); 120 void modify_data_training(struct dram_info *priv, 121 struct sdram_params *params_priv); 122 void move_to_config_state(struct dram_info *priv); 123 void move_to_access_state(struct dram_info *priv); 124 void pctl_cfg_grf(struct dram_info *priv, 125 struct sdram_params *params_priv); 126 void phy_pctrl_reset_cru(struct dram_info *priv); 127 void print_dec(u32 n); 128 void rkdclk_init(struct dram_info *priv, 129 struct sdram_params *params_priv); 130 int rv1108_sdram_init(struct dram_info *sdram_priv, 131 struct sdram_params *params_priv); 132 void set_bw_grf(struct dram_info *priv); 133 void set_ds_odt(struct dram_info *priv, 134 struct sdram_params *params_priv); 135 136 #endif 137