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Searched +full:pll +full:- +full:periph (Results 1 – 25 of 65) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/socfpga/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
3 obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
4 obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
5 obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
6 obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
7 obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3066.c5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3066a-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
71 /* PLL CON0 */
74 /* PLL CON1 */
77 /* PLL CON2 */
80 /* PLL CON3 */
[all …]
H A Dclk_rk3188.c5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3188-cru.h>
22 #include <dm/device-internal.h>
24 #include <dm/uclass-internal.h>
72 /* PLL CON0 */
75 /* PLL CON1 */
78 /* PLL CON2 */
81 /* PLL CON3 */
[all …]
H A Dclk_rk3288.c4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
86 /* PLL CON0 */
89 /* PLL CON1 */
92 /* PLL CON2 */
95 /* PLL CON3 */
[all …]
H A Dclk_rk3036.c4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3036-cru.h>
45 ((input_rate) / (output_rate) - 1);
55 #hz "Hz cannot be hit with PLL "\
66 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
72 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
88 return -EINVAL; in of_to_struct()
96 *val = fdtdec_get_uint(blob, node, "clock-frequency", 0); in of_get_input_clks()
98 return -EINVAL; in of_get_input_clks()
112 return -EINVAL; in of_get_clk_cfg()
116 return -EINVAL; in of_get_clk_cfg()
120 return -EINVAL; in of_get_clk_cfg()
127 return -EINVAL; in of_get_clk_cfg()
130 return -EINVAL; in of_get_clk_cfg()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
36 .hw.init = CLK_HW_INIT("pll-core",
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * pll audio).
48 * With sigma-delta modulation for fractional-N on the audio PLL,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
89 .hw.init = CLK_HW_INIT("pll-video0",
104 .hw.init = CLK_HW_INIT("pll-ve",
[all …]
H A Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
38 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
45 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
47 * pll audio).
49 * With sigma-delta modulation for fractional-N on the audio PLL,
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
H A Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
23 #include "ccu-sun8i-a23-a33.h"
36 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * pll audio).
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
[all …]
H A Dccu-sun8i-a83t.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
66 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
92 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
[all …]
H A Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
34 .hw.init = CLK_HW_INIT("pll-core",
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * pll audio).
46 * With sigma-delta modulation for fractional-N on the audio PLL,
74 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
[all …]
H A Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
41 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
43 * pll audio).
45 * With sigma-delta modulation for fractional-N on the audio PLL,
[all …]
H A Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "ccu-suniv-f1c100s.h"
38 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
45 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
47 * pll audio).
54 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dat91sam9263.dtsi2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
18 interrupt-parent = <&aic>;
39 #address-cells = <0>;
40 #size-cells = <0>;
43 compatible = "arm,arm926ej-s";
[all …]
H A Dat91sam9260.dtsi2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
40 #address-cells = <0>;
41 #size-cells = <0>;
44 compatible = "arm,arm926ej-s";
[all …]
H A Dat91sam9n12.dtsi2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
20 interrupt-parent = <&aic>;
41 #address-cells = <0>;
42 #size-cells = <0>;
45 compatible = "arm,arm926ej-s";
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
[all …]
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
30 * memory clock PLL.
48 CLOCK_TYPE_NONE = -1, /* invalid clock type */
65 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
68 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
71 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
74 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
30 * memory clock PLL.
48 CLOCK_TYPE_NONE = -1, /* invalid clock type */
65 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
68 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
71 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
74 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk_pic32.c4 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
16 #include <dt-bindings/clock/microchip,clock.h>
71 /* Memory PLL */
97 v = readl(priv->iobase + SPLLCON); in pic32_get_pll_rate()
123 v = readl(priv->iobase + OSCCON); in pic32_get_sysclk()
150 static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph) in pic32_get_pbclk() argument
155 WARN_ON((periph < PB1CLK) || (periph > PB7CLK)); in pic32_get_pbclk()
159 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; in pic32_get_pbclk()
170 static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph, in pic32_set_refclk() argument
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c3 * (C) Copyright 2010-2015
6 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
31 * memory clock PLL.
41 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
46 CLOCK_TYPE_NONE = -1, /* invalid clock type */
62 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
63 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
64 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
[all …]
/OK3568_Linux_fs/kernel/arch/mips/bcm63xx/
H A Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
287 * HSSPI PLL
401 return clk->rate; in clk_get_rate()
420 CLKDEV_INIT(NULL, "periph", &clk_periph),
437 CLKDEV_INIT(NULL, "periph", &clk_periph),
440 CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c2 * (C) Copyright 2013-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
30 * memory clock PLL.
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
58 CLOCK_TYPE_NONE = -1, /* invalid clock type */
75 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
78 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
81 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ccu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
17 "#reset-cells":
22 - allwinner,sun4i-a10-ccu
23 - allwinner,sun5i-a10s-ccu
[all …]

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