mach-tegra/tegra30/clock.c

2  * (C) Copyright 2010-2015
5  * SPDX-License-Identifier:     GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
30  * memory clock PLL.
48 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
65 	{ CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
68 	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
71 	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
74 	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
77 	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
80 	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
83 	{ CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
86 	{ CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
89 	{ CLK(AUDIO),   CLK(SFROM32KHZ),	CLK(PERIPH),   CLK(OSC),
92 	{ CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
95 	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
142 	TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),       /* MIPI base-band HSI */
176 	/* 0x38h */	     /* Jumps to reg offset 0x3B0h - new for T30 */
221  *	SPDIF - which is both 0x08 and 0x0c
224 #define NONE(name) (-1)
409  * PLL divider shift/mask tables for all PLL IDs.
414 	 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
415 	 *       If lock_ena or lock_det are >31, they're not used in that PLL.
449 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
467 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
471 	assert(internal_id != -1);  in get_periph_source_reg()
473 		internal_id -= PERIPHC_VW_FIRST;  in get_periph_source_reg()
474 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
476 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
485 		return -1;  in get_periph_clock_info()
489 		return -1;  in get_periph_clock_info()
493 		return -1;  in get_periph_clock_info()
531  * @param source	PLL id of required parent clock
534  * @return mux value (0-4, or -1 if not found)
550 	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,  in get_periph_clock_source()
552 	return -1;  in get_periph_clock_source()
565 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
567 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
586 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
588 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
696 	} while (--timeout);  in tegra_plle_train()
700 		return -ETIMEDOUT;  in tegra_plle_train()
772 	} while (--timeout);  in tegra_plle_enable()
776 		return -ETIMEDOUT;  in tegra_plle_enable()
819 	{ -1, },