mach-tegra/tegra20/clock.c

3  * (C) Copyright 2010-2015
6  * SPDX-License-Identifier:	GPL-2.0+
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
31  * memory clock PLL.
41 	CLOCK_TYPE_PCMT16,	/* CLOCK_TYPE_PCMT with 16-bit divider */
46 	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
62 	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC)	},
63 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO)	},
64 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC)	},
65 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE)	},
66 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
67 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
68 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(XCPU),	CLK(OSC)	},
69 	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC)	},
74  * not in the header file since it is for purely internal use - we want
156 	PERIPHC_NONE = -1,
239  *	SPDIF - which is both 0x08 and 0x0c
242 #define NONE(name) (-1)
360  * PLL divider shift/mask tables for all PLL IDs.
365 	 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
366 	 *       If lock_ena or lock_det are >31, they're not used in that PLL.
399 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
412 	assert(internal_id != -1);  in get_periph_source_reg()
413 	return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
422 		return -1;  in get_periph_clock_info()
426 		return -1;  in get_periph_clock_info()
430 		return -1;  in get_periph_clock_info()
433 	 * Special cases here for the clock with a 4-bit source mux and I2C  in get_periph_clock_info()
434 	 * with its 16-bit divisor  in get_periph_clock_info()
474  * @param source	PLL id of required parent clock
477  * @return mux value (0-4, or -1 if not found)
503 	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,  in get_periph_clock_source()
505 	return -1;  in get_periph_clock_source()
512 	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
529 	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
585 	 * TODO: Can we calculate these values instead of hard-coding?  in clock_early_init()
667 	} while (--timeout);  in tegra_plle_train()
671 		return -ETIMEDOUT;  in tegra_plle_train()
726 	} while (--timeout);  in tegra_plle_enable()
730 		return -ETIMEDOUT;  in tegra_plle_enable()
771 	{ -1, },