Lines Matching +full:pll +full:- +full:periph
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3188-cru.h>
22 #include <dm/device-internal.h>
24 #include <dm/uclass-internal.h>
72 /* PLL CON0 */
75 /* PLL CON1 */
78 /* PLL CON2 */
81 /* PLL CON3 */
96 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
109 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
111 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
112 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
114 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
115 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
118 (div->no == 1 || !(div->no % 2))); in rkclk_set_pll()
121 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
123 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
125 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
126 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
129 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
134 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
165 return -EINVAL; in rkclk_configure_ddr()
168 /* pll enter slow-mode */ in rkclk_configure_ddr()
169 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
174 /* wait for pll lock */ in rkclk_configure_ddr()
175 while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) in rkclk_configure_ddr()
178 /* PLL enter normal-mode */ in rkclk_configure_ddr()
179 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
214 return -EINVAL; in rkclk_configure_cpu()
217 /* pll enter slow-mode */ in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
223 /* waiting for pll lock */ in rkclk_configure_cpu()
224 while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) in rkclk_configure_cpu()
228 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
233 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
237 /* PLL enter normal-mode */ in rkclk_configure_cpu()
238 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
244 /* Get pll rate by id */
251 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
258 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
265 con = readl(&pll->con0); in rkclk_pll_get_rate()
268 con = readl(&pll->con1); in rkclk_pll_get_rate()
279 int periph) in rockchip_mmc_get_clk() argument
284 switch (periph) { in rockchip_mmc_get_clk()
287 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
292 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
297 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
301 return -EINVAL; in rockchip_mmc_get_clk()
308 int periph, uint freq) in rockchip_mmc_set_clk() argument
314 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1; in rockchip_mmc_set_clk()
317 switch (periph) { in rockchip_mmc_set_clk()
320 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
326 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
332 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
337 return -EINVAL; in rockchip_mmc_set_clk()
340 return rockchip_mmc_get_clk(cru, gclk_rate, periph); in rockchip_mmc_set_clk()
344 int periph) in rockchip_spi_get_clk() argument
349 switch (periph) { in rockchip_spi_get_clk()
351 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
355 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
359 return -EINVAL; in rockchip_spi_get_clk()
366 int periph, uint freq) in rockchip_spi_set_clk() argument
368 int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
371 switch (periph) { in rockchip_spi_set_clk()
374 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
380 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
385 return -EINVAL; in rockchip_spi_set_clk()
388 return rockchip_spi_get_clk(cru, gclk_rate, periph); in rockchip_spi_set_clk()
395 val = readl(&cru->cru_clksel_con[24]); in rk3188_saradc_get_clk()
405 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3188_saradc_set_clk()
408 rk_clrsetreg(&cru->cru_clksel_con[24], in rk3188_saradc_set_clk()
421 /* pll enter slow-mode */ in rkclk_init()
422 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
428 /* init pll */ in rkclk_init()
432 /* waiting for pll lock */ in rkclk_init()
433 while ((readl(&grf->soc_status0) & in rkclk_init()
439 * cpu clock pll source selection and in rkclk_init()
443 aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; in rkclk_init()
446 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
459 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
468 * peri clock pll source selection and in rkclk_init()
471 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
482 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
491 /* PLL enter normal-mode */ in rkclk_init()
492 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
504 struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); in rk3188_clk_get_rate()
507 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3188_clk_get_rate()
508 switch (clk->id) { in rk3188_clk_get_rate()
510 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3188_clk_get_rate()
518 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, in rk3188_clk_get_rate()
519 clk->id); in rk3188_clk_get_rate()
523 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, in rk3188_clk_get_rate()
524 clk->id); in rk3188_clk_get_rate()
533 new_rate = rk3188_saradc_get_clk(priv->cru); in rk3188_clk_get_rate()
535 return -ENOENT; in rk3188_clk_get_rate()
543 struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); in rk3188_clk_set_rate()
544 struct rk3188_cru *cru = priv->cru; in rk3188_clk_set_rate()
547 switch (clk->id) { in rk3188_clk_set_rate()
549 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
550 priv->has_bwadj); in rk3188_clk_set_rate()
553 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, in rk3188_clk_set_rate()
554 priv->has_bwadj); in rk3188_clk_set_rate()
563 clk->id, rate); in rk3188_clk_set_rate()
568 clk->id, rate); in rk3188_clk_set_rate()
571 new_rate = rk3188_saradc_set_clk(priv->cru, rate); in rk3188_clk_set_rate()
574 return -ENOENT; in rk3188_clk_set_rate()
590 priv->cru = dev_read_addr_ptr(dev); in rk3188_clk_ofdata_to_platdata()
601 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3188_clk_probe()
602 if (IS_ERR(priv->grf)) in rk3188_clk_probe()
603 return PTR_ERR(priv->grf); in rk3188_clk_probe()
604 priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; in rk3188_clk_probe()
610 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3188_clk_probe()
612 priv->sync_kernel = false; in rk3188_clk_probe()
613 if (!priv->armclk_enter_hz) in rk3188_clk_probe()
614 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3188_clk_probe()
616 rkclk_init(priv->cru, priv->grf, priv->has_bwadj); in rk3188_clk_probe()
617 if (!priv->armclk_init_hz) in rk3188_clk_probe()
618 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3188_clk_probe()
639 priv->glb_srst_fst_value = offsetof(struct rk3188_cru, in rk3188_clk_bind()
641 priv->glb_srst_snd_value = offsetof(struct rk3188_cru, in rk3188_clk_bind()
643 sys_child->priv = priv; in rk3188_clk_bind()
652 sf_priv->sf_reset_offset = offsetof(struct rk3188_cru, in rk3188_clk_bind()
654 sf_priv->sf_reset_num = 9; in rk3188_clk_bind()
655 sf_child->priv = sf_priv; in rk3188_clk_bind()
662 { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
663 { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
681 * soc_clk_dump() - Print clock frequencies
706 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
707 priv->armclk_enter_hz / 1000, in soc_clk_dump()
708 priv->armclk_init_hz / 1000, in soc_clk_dump()
709 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
710 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
713 if (clk_dump->name) { in soc_clk_dump()
714 clk.id = clk_dump->id; in soc_clk_dump()
715 if (clk_dump->is_cru) in soc_clk_dump()
724 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
727 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
731 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
734 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()