Lines Matching +full:pll +full:- +full:periph
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3036-cru.h>
45 ((input_rate) / (output_rate) - 1);
55 #hz "Hz cannot be hit with PLL "\
66 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
72 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ in rkclk_set_pll()
74 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
75 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
85 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
90 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
95 /* waiting for pll lock */ in rkclk_set_pll()
96 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
109 /* pll enter slow-mode */ in rkclk_init()
110 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
115 /* init pll */ in rkclk_init()
120 * select apll as cpu/core clock pll source and in rkclk_init()
124 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; in rkclk_init()
127 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()
130 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
135 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
144 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
147 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
150 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
153 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
158 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
167 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
178 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
188 rk_clrsetreg(&cru->cru_clksel_con[16], in rkclk_init()
193 /* PLL enter normal-mode */ in rkclk_init()
194 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
200 /* Get pll rate by id */
207 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
219 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
229 con = readl(&pll->con0); in rkclk_pll_get_rate()
232 con = readl(&pll->con1); in rkclk_pll_get_rate()
243 int periph) in rockchip_mmc_get_clk() argument
249 switch (periph) { in rockchip_mmc_get_clk()
252 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
258 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
263 return -EINVAL; in rockchip_mmc_get_clk()
271 int periph, uint freq) in rockchip_mmc_set_clk() argument
283 assert(src_clk_div - 1 < 128); in rockchip_mmc_set_clk()
289 switch (periph) { in rockchip_mmc_set_clk()
292 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
295 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
299 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
302 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
305 return -EINVAL; in rockchip_mmc_set_clk()
308 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); in rockchip_mmc_set_clk()
315 con = readl(&cru->cru_clksel_con[25]); in rk3036_spi_get_clk()
328 assert(div - 1 < 128); in rk3036_spi_set_clk()
329 rk_clrsetreg(&cru->cru_clksel_con[25], in rk3036_spi_set_clk()
332 (div - 1) << SPI_DIV_SHIFT); in rk3036_spi_set_clk()
341 con = readl(&cru->cru_clksel_con[28]); in rockchip_dclk_lcdc_get_clk()
347 return -ENOENT; in rockchip_dclk_lcdc_get_clk()
358 assert(src_clk_div - 1 <= 255); in rockchip_dclk_lcdc_set_clk()
360 rk_clrsetreg(&cru->cru_clksel_con[28], in rockchip_dclk_lcdc_set_clk()
363 (src_clk_div - 1) << LCDC_DCLK_DIV_SHIFT); in rockchip_dclk_lcdc_set_clk()
373 con = readl(&cru->cru_clksel_con[31]); in rockchip_aclk_lcdc_get_clk()
379 return -ENOENT; in rockchip_aclk_lcdc_get_clk()
390 assert(src_clk_div - 1 <= 31); in rockchip_aclk_lcdc_set_clk()
392 rk_clrsetreg(&cru->cru_clksel_con[31], in rockchip_aclk_lcdc_set_clk()
395 (src_clk_div - 1) << LCDC_ACLK_DIV_SHIFT); in rockchip_aclk_lcdc_set_clk()
403 struct rk3036_cru *cru = priv->cru; in rk3036_peri_get_clk()
408 con = readl(&cru->cru_clksel_con[10]); in rk3036_peri_get_clk()
413 con = readl(&cru->cru_clksel_con[10]); in rk3036_peri_get_clk()
419 return -EINVAL; in rk3036_peri_get_clk()
429 struct rk3036_cru *cru = priv->cru; in rk3036_peri_set_clk()
435 assert(src_clk_div - 1 < 32); in rk3036_peri_set_clk()
436 rk_clrsetreg(&cru->cru_clksel_con[10], in rk3036_peri_set_clk()
439 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); in rk3036_peri_set_clk()
446 assert(src_clk_div - 1 < 8); in rk3036_peri_set_clk()
447 rk_clrsetreg(&cru->cru_clksel_con[10], in rk3036_peri_set_clk()
449 (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT); in rk3036_peri_set_clk()
453 return -EINVAL; in rk3036_peri_set_clk()
461 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); in rk3036_clk_get_rate()
462 ulong gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3036_clk_get_rate()
464 switch (clk->id) { in rk3036_clk_get_rate()
466 return rkclk_pll_get_rate(priv->cru, clk->id); in rk3036_clk_get_rate()
468 return rockchip_dclk_lcdc_get_clk(priv->cru, gclk_rate); in rk3036_clk_get_rate()
470 return rockchip_aclk_lcdc_get_clk(priv->cru, gclk_rate); in rk3036_clk_get_rate()
472 return rk3036_spi_get_clk(priv->cru, gclk_rate); in rk3036_clk_get_rate()
474 return rk3036_peri_get_clk(priv, clk->id, gclk_rate); in rk3036_clk_get_rate()
476 return -ENOENT; in rk3036_clk_get_rate()
482 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); in rk3036_clk_set_rate()
485 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3036_clk_set_rate()
486 switch (clk->id) { in rk3036_clk_set_rate()
491 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
492 clk->id, rate); in rk3036_clk_set_rate()
495 new_rate = rockchip_dclk_lcdc_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
499 new_rate = rockchip_aclk_lcdc_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
503 new_rate = rk3036_spi_set_clk(priv->cru, gclk_rate, in rk3036_clk_set_rate()
507 new_rate = rk3036_peri_set_clk(priv, clk->id, gclk_rate, in rk3036_clk_set_rate()
511 return -ENOENT; in rk3036_clk_set_rate()
526 priv->cru = dev_read_addr_ptr(dev); in rk3036_clk_ofdata_to_platdata()
535 priv->sync_kernel = false; in rk3036_clk_probe()
536 if (!priv->armclk_enter_hz) in rk3036_clk_probe()
537 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3036_clk_probe()
539 rkclk_init(priv->cru); in rk3036_clk_probe()
540 if (!priv->armclk_init_hz) in rk3036_clk_probe()
541 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3036_clk_probe()
561 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, in rk3036_clk_bind()
563 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, in rk3036_clk_bind()
565 sys_child->priv = priv; in rk3036_clk_bind()
574 sf_priv->sf_reset_offset = offsetof(struct rk3036_cru, in rk3036_clk_bind()
576 sf_priv->sf_reset_num = 9; in rk3036_clk_bind()
577 sf_child->priv = sf_priv; in rk3036_clk_bind()
584 { .compatible = "rockchip,rk3036-cru" },
601 * soc_clk_dump() - Print clock frequencies
626 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
627 priv->armclk_enter_hz / 1000, in soc_clk_dump()
628 priv->armclk_init_hz / 1000, in soc_clk_dump()
629 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
630 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
633 if (clk_dump->name) { in soc_clk_dump()
634 clk.id = clk_dump->id; in soc_clk_dump()
635 if (clk_dump->is_cru) in soc_clk_dump()
644 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
647 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
651 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
654 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()