Lines Matching +full:pll +full:- +full:periph
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3066a-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
71 /* PLL CON0 */
74 /* PLL CON1 */
77 /* PLL CON2 */
80 /* PLL CON3 */
91 ((input_rate) / (output_rate) - 1);
98 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
111 struct rk3066_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll() local
113 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
114 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
116 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
117 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
120 (div->no == 1 || !(div->no % 2))); in rkclk_set_pll()
123 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
125 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
127 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
128 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
131 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
136 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
167 return -EINVAL; in rkclk_configure_ddr()
170 /* pll enter slow-mode */ in rkclk_configure_ddr()
171 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
176 /* wait for pll lock */ in rkclk_configure_ddr()
177 while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) in rkclk_configure_ddr()
180 /* PLL enter normal-mode */ in rkclk_configure_ddr()
181 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
216 return -EINVAL; in rkclk_configure_cpu()
219 /* pll enter slow-mode */ in rkclk_configure_cpu()
220 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rkclk_configure_cpu()
225 /* waiting for pll lock */ in rkclk_configure_cpu()
226 while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) in rkclk_configure_cpu()
230 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
235 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
239 /* PLL enter normal-mode */ in rkclk_configure_cpu()
240 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rkclk_configure_cpu()
246 /* Get pll rate by id */
253 struct rk3066_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate() local
260 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
267 con = readl(&pll->con0); in rkclk_pll_get_rate()
270 con = readl(&pll->con1); in rkclk_pll_get_rate()
281 int periph) in rockchip_mmc_get_clk() argument
286 switch (periph) { in rockchip_mmc_get_clk()
288 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
292 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
296 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
300 return -EINVAL; in rockchip_mmc_get_clk()
307 int periph, uint freq) in rockchip_mmc_set_clk() argument
316 switch (periph) { in rockchip_mmc_set_clk()
318 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
323 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
328 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
333 return -EINVAL; in rockchip_mmc_set_clk()
336 return rockchip_mmc_get_clk(cru, gclk_rate, periph); in rockchip_mmc_set_clk()
340 int periph) in rockchip_spi_get_clk() argument
345 switch (periph) { in rockchip_spi_get_clk()
347 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
351 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
355 return -EINVAL; in rockchip_spi_get_clk()
362 int periph, uint freq) in rockchip_spi_set_clk() argument
366 switch (periph) { in rockchip_spi_set_clk()
369 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
375 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
380 return -EINVAL; in rockchip_spi_set_clk()
383 return rockchip_spi_get_clk(cru, gclk_rate, periph); in rockchip_spi_set_clk()
391 /* pll enter slow-mode */ in rkclk_init()
392 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
398 /* init pll */ in rkclk_init()
402 /* waiting for pll lock */ in rkclk_init()
403 while ((readl(&grf->soc_status0) & in rkclk_init()
409 * cpu clock pll source selection and in rkclk_init()
416 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
429 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
438 * peri clock pll source selection and in rkclk_init()
441 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
452 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
461 /* PLL enter normal-mode */ in rkclk_init()
462 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
474 struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); in rk3066_clk_get_rate()
477 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3066_clk_get_rate()
478 switch (clk->id) { in rk3066_clk_get_rate()
480 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3066_clk_get_rate()
485 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, in rk3066_clk_get_rate()
486 clk->id); in rk3066_clk_get_rate()
490 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, in rk3066_clk_get_rate()
491 clk->id); in rk3066_clk_get_rate()
500 return -ENOENT; in rk3066_clk_get_rate()
508 struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); in rk3066_clk_set_rate()
509 struct rk3066_cru *cru = priv->cru; in rk3066_clk_set_rate()
512 switch (clk->id) { in rk3066_clk_set_rate()
514 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, in rk3066_clk_set_rate()
515 priv->has_bwadj); in rk3066_clk_set_rate()
518 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, in rk3066_clk_set_rate()
519 priv->has_bwadj); in rk3066_clk_set_rate()
525 clk->id, rate); in rk3066_clk_set_rate()
530 clk->id, rate); in rk3066_clk_set_rate()
533 return -ENOENT; in rk3066_clk_set_rate()
549 priv->cru = dev_read_addr_ptr(dev); in rk3066_clk_ofdata_to_platdata()
559 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3066_clk_probe()
560 if (IS_ERR(priv->grf)) in rk3066_clk_probe()
561 return PTR_ERR(priv->grf); in rk3066_clk_probe()
567 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3066_clk_probe()
569 priv->sync_kernel = false; in rk3066_clk_probe()
570 if (!priv->armclk_enter_hz) in rk3066_clk_probe()
571 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3066_clk_probe()
573 rkclk_init(priv->cru, priv->grf, 1); in rk3066_clk_probe()
574 if (!priv->armclk_init_hz) in rk3066_clk_probe()
575 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3066_clk_probe()
595 priv->glb_srst_fst_value = offsetof(struct rk3066_cru, in rk3066_clk_bind()
597 priv->glb_srst_snd_value = offsetof(struct rk3066_cru, in rk3066_clk_bind()
599 sys_child->priv = priv; in rk3066_clk_bind()
608 sf_priv->sf_reset_offset = offsetof(struct rk3066_cru, in rk3066_clk_bind()
610 sf_priv->sf_reset_num = 9; in rk3066_clk_bind()
611 sf_child->priv = sf_priv; in rk3066_clk_bind()
618 { .compatible = "rockchip,rk3066a-cru" },
636 * soc_clk_dump() - Print clock frequencies
661 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
662 priv->armclk_enter_hz / 1000, in soc_clk_dump()
663 priv->armclk_init_hz / 1000, in soc_clk_dump()
664 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
665 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
668 if (clk_dump->name) { in soc_clk_dump()
669 clk.id = clk_dump->id; in soc_clk_dump()
670 if (clk_dump->is_cru) in soc_clk_dump()
679 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
682 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
686 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
689 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()